 Phil
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1504569fb6
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debug: add waveconfigs
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2026-05-15 14:09:33 +03:00 |
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Phil
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eacffd44b3
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docs: update ctrl readme
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2026-05-12 13:47:51 +03:00 |
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Phil
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5c1866d571
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chore: re-organise designs for better hierarchy
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2026-05-12 13:25:44 +03:00 |
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Phil
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f9f4a10cdf
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infra: fix constraints - adc
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2026-05-12 13:23:42 +03:00 |
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Phil
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e6cb0e0f6e
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Merge branch 'dev/ax7102' into dev/design
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2026-05-08 19:07:58 +03:00 |
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Phil
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dad163b6ac
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infra: update scripts to auto-upgrade ip
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2026-05-08 19:04:21 +03:00 |
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Phil
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78095ad9a1
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chore: update eth_test_minimal to a100
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2026-05-08 18:49:27 +03:00 |
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Phil
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c77b54aec6
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chore: update eth_axis to a100
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2026-05-08 18:43:49 +03:00 |
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Phil
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429cf3d085
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chore: update eth_test_minimal to a100
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2026-05-08 18:43:26 +03:00 |
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Phil
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7f6a3e03a1
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infra: add constraints for ax7102 board
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2026-05-08 17:26:24 +03:00 |
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Phil
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66a15cd6e0
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test: more cases for accum
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2026-05-08 16:43:53 +03:00 |
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Phil
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f2a8d8a28e
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sw: update console with new packet changes
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2026-05-08 16:05:53 +03:00 |
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Phil
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ecb2ed3b7f
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rtl: update controller to support different smp_num for adc/dac sides
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2026-05-08 15:59:20 +03:00 |
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Phil
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2a928c2407
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rtl: add more debug nodes for reflectometer
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2026-05-08 15:58:33 +03:00 |
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Phil
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bc0a1c8b66
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fix: signal names in reflectometer
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2026-05-08 15:58:11 +03:00 |
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Phil
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179347659b
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rtl: update reflectometer top design
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2026-04-30 13:10:41 +03:00 |
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Phil
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9fd311d671
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chore: add debug XDC for main project
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2026-04-30 13:05:33 +03:00 |
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Phil
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a018b3d215
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fix: bad checksums in axis_mac
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2026-04-30 13:05:06 +03:00 |
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Phil
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16cef61a88
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rtl: add sample reflectometer project mock
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2026-04-28 17:05:14 +03:00 |
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Phil
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d68c22211d
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chore: update constraints to debug ADC + simple DAC
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2026-04-28 16:58:36 +03:00 |
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Phil
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3ea03fd40c
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docs: add README for accum
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2026-04-28 15:36:59 +03:00 |
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Phil
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ea381320f3
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Merge branch 'dev/accum' of https://git.radiophotonics.ru/baulin.fa/reflectometer_fpga_project into dev/accum
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2026-04-28 15:36:34 +03:00 |
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Phil
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d5c3ff873f
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infra: add sample makefile
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2026-04-28 14:41:56 +03:00 |
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Phil
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4efc2f02a9
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infra: increase sim time for larger tests
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2026-04-28 13:29:05 +03:00 |
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Phil
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312bc0c798
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fix: automate tb
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2026-04-28 13:28:49 +03:00 |
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Phil
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c4a7c21bea
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fix: clock name un xdc
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2026-04-28 13:13:40 +03:00 |
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Phil
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e083cd5c2e
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rtl: update accum to support real cases
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2026-04-28 13:13:27 +03:00 |
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Phil
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fc0e710b3e
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tests: add waveconfigs
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2026-04-28 12:11:41 +03:00 |
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Phil
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275055291e
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fix: update names in out_axis_fifo_tb
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2026-04-28 11:57:53 +03:00 |
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Phil
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002f0cace5
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test: add full testbenches for accum
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2026-04-28 11:57:13 +03:00 |
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Phil
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91eaf6c4f8
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fix: out_axis_fifo states
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2026-04-28 11:56:19 +03:00 |
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Phil
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9b189f931f
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rtl: update accum design
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2026-04-28 11:55:46 +03:00 |
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Phil
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a8a3aff498
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rtl: first impl of adder+accum
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2026-04-22 16:38:22 +03:00 |
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Phil
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b54e69dec0
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chore: add clocks for accum_fifo impl test
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2026-04-21 19:48:20 +03:00 |
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Phil
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7be26d9d1a
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chore: update tb files
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2026-04-21 19:47:56 +03:00 |
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Phil
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3dcaaf8ea5
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fix: better sync for accum fifo
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2026-04-21 19:47:46 +03:00 |
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Phil
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dfccc01225
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tests: auto tb for out_axis_fifo
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2026-04-21 19:47:27 +03:00 |
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Phil
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4eb937e13f
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infra: make default sim longer
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2026-04-21 19:46:51 +03:00 |
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Phil
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21785aaac7
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rtl: send part of out_axis_fifo
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2026-04-21 17:26:02 +03:00 |
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Phil
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8e46f965df
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fix: incorrect fifo threshold value
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2026-04-17 21:58:20 +03:00 |
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Phil
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7f9ad95e68
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tests: add simple tb for accum output fifo
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2026-04-17 21:51:00 +03:00 |
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Phil
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4786d2d7f6
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rtl: wip accum output module, currently only with write part
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2026-04-17 21:50:30 +03:00 |
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Phil
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8b1e209da6
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rtl: add project with eth and generator
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2026-04-17 14:53:14 +03:00 |
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Phil
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924f94986c
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chore: exclude bitstreams from git
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2026-04-17 14:50:23 +03:00 |
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Phil
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83c714cd6f
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sw: update console, now can send actual data
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2026-04-17 14:44:27 +03:00 |
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Phil
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f54883a9e7
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fix: constraint re-pin DAC to J11 header
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2026-04-17 14:43:31 +03:00 |
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Phil
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b9c75b823f
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fix: generator wrt signal incorrect clocking
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2026-04-17 14:42:20 +03:00 |
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Phil
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597be48407
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docs: fix typos
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2026-04-15 18:56:46 +03:00 |
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Phil
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f98051bc53
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docs: add controller READMEs
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2026-04-15 18:54:07 +03:00 |
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Phil
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eea031c6c1
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fix: broken (stuck) sim
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2026-04-15 18:53:49 +03:00 |
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Phil
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500b10b327
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sw: add console script prototype
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2026-04-15 18:28:03 +03:00 |
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Phil
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851851828e
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fix: add missing constrain to Makefile
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2026-04-15 18:23:52 +03:00 |
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Phil
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35e9feb87b
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tests: add sample project for eth+ctrl
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2026-04-15 17:57:16 +03:00 |
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Phil
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c41b08f539
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fix: tricky packet check in ctrl
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2026-04-15 17:56:22 +03:00 |
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Phil
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ea7af4ed62
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infra: init designs folder
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2026-04-15 13:40:19 +03:00 |
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Phil
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6bb4f1efd8
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infra: sim_top auto pick if exists in sim fileset
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2026-04-15 13:31:47 +03:00 |
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Phil
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dcf93fb307
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infra: add build Makefile for controller test project
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2026-04-15 13:31:28 +03:00 |
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Phil
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23f82b9445
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tests: add controller tb
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2026-04-15 13:30:56 +03:00 |
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Phil
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bdb75fa298
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infra: exclude temp scripts from git
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2026-04-15 13:19:08 +03:00 |
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Phil
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003750d972
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rtl: add controller first version
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2026-04-15 12:47:10 +03:00 |
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Phil
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7d1bfe25b4
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infra: update constraints to use unified ones for board and additional for debug nodes
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2026-04-14 15:39:21 +03:00 |
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Phil
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df6c204cbd
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docs: add readme to ethernet-udp
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2026-04-14 12:36:05 +03:00 |
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Phil
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8907fea8a4
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fix: signal in axis_mac
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2026-04-14 12:32:10 +03:00 |
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Phil
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1c654f4e8e
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tests: add tb to axis_mac project
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2026-04-14 12:31:21 +03:00 |
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Phil
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c372dcd942
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infra: add sim support to vivado.mk targets
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2026-04-14 12:30:30 +03:00 |
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Phil
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a3ed4919bc
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chore: add debug for base ethernet test
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2026-04-10 15:40:29 +03:00 |
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Phil
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d813855224
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tests: add test project for ethernet echo & axis_mac tests
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2026-04-10 15:39:59 +03:00 |
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Phil
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0480642167
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chore: little refactor in eth stack
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2026-04-10 15:38:09 +03:00 |
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Phil
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c33afac783
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rtl: implement axis UDP TX logic
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2026-04-10 15:37:19 +03:00 |
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Phil
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26c627c988
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rtl: add udp ram data count signal logic
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2026-04-10 15:35:26 +03:00 |
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Phil
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879c4d49b2
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infra: add vivado builds to gitignore
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2026-04-10 15:19:43 +03:00 |
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Phil
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3544e3e2dc
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test: add sample top for axis loopback test
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2026-04-08 19:58:34 +03:00 |
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Phil
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100feb0ea1
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rtl: add constrains for axis eth fpga project
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2026-04-01 18:10:17 +03:00 |
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Phil
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1310555b55
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chore: remove old file
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2026-04-01 18:08:50 +03:00 |
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Phil
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c75443d170
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test: udp axis rx
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2026-04-01 18:04:01 +03:00 |
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Phil
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3a58119960
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rtl: eth udp rx -> axis
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2026-04-01 18:03:47 +03:00 |
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Phil
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0b9fb64193
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rtl: add axis eth rx prototype
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2026-04-01 11:44:46 +03:00 |
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Phil
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a1386fc8a4
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infra: add vivado.mk target for generic builds
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2026-03-31 15:08:28 +03:00 |
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Phil
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7fedc36562
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tests: add sample project for minimal eth udp echo
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2026-03-31 15:08:12 +03:00 |
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Phil
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0dd0006e47
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infra: add gitignore
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2026-03-31 12:53:25 +03:00 |
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Phil
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ded2afc0db
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rtl: add sources for ethernet udp stack
|
2026-03-31 12:53:16 +03:00 |
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Phil
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1c9bce7927
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chore: update readme
|
2026-03-25 15:57:00 +03:00 |
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