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  • 56a0240f8e upd: sampler & TB complete dev/design babintsev.lv 2026-07-24 17:54:37 +03:00
  • ee83bcbb9e debugging testbench dev/controller otroubi 2026-07-22 22:07:03 +03:00
  • 8648747380 debugging a module and its wrappers otroubi 2026-07-22 22:06:44 +03:00
  • e06ef3a16b changing the addition of interfaces otroubi 2026-07-21 22:37:24 +03:00
  • c121c2c103 test environment for controller and dma project otroubi 2026-07-21 22:36:55 +03:00
  • 56c33d2769 makefile for test project otroubi 2026-07-21 22:35:32 +03:00
  • 81970c8b42 upd: new TB, sampler refactor babintsev.lv 2026-07-21 16:54:06 +03:00
  • fc33aa6862 rtl: little changes otroubi 2026-07-21 14:07:44 +03:00
  • 490d3dcfd0 creation of project for dma tests otroubi 2026-07-20 17:29:15 +03:00
  • 1c2eccaf1d rtl: reconstruction of registers for dma otroubi 2026-07-20 17:28:48 +03:00
  • a528838741 fix: patch for sampler upd: reflectometer TB readaout data task babintsev.lv 2026-07-17 17:29:58 +03:00
  • 04eb927a25 fix: encoding issues, generator explicit default state babintsev.lv 2026-07-17 15:21:49 +03:00
  • 4240604f26 sampler version with debugged OTR and debugged testbench otroubi 2026-07-17 13:38:47 +03:00
  • ef65dd1a97 upd: DUT fully working. TB tests WIP Zer0Nu11 2026-07-16 22:45:21 +03:00
  • 71b825ef2c upd: fix axi-stream interface definition; successful TB DUT launch Zer0Nu11 2026-07-16 19:33:51 +03:00
  • 076ad542b2 test: add all controller tests Phil 2026-07-14 20:07:52 +03:00
  • e685a6a9fc fix: rework wrapper for tests Phil 2026-07-14 20:07:34 +03:00
  • c057890007 fix: invalid signals Phil 2026-07-14 20:07:23 +03:00
  • 42df57be7d axis flat to if / if to flat correction otroubi 2026-07-14 19:24:25 +03:00
  • 606d1d7f1c little axis desc status correction otroubi 2026-07-14 19:07:32 +03:00
  • 8aefa4f3f6 axis dma desc and status interface otroubi 2026-07-14 18:39:48 +03:00
  • 7cf727883f test: add proper cfg tests Phil 2026-07-14 18:06:29 +03:00
  • cec4c84fd9 fix: controller reg map invalid mapping Phil 2026-07-14 17:43:47 +03:00
  • 691e69693a infra: update makefile for cocotb Phil 2026-07-14 16:48:45 +03:00
  • e467700368 tests: update testbench for controller reg map Phil 2026-07-14 16:34:35 +03:00
  • 984461afc0 shapper syntaxis corrected otroubi 2026-07-14 13:55:58 +03:00
  • 6c171c55d7 controller_wrapper_axil syntaxis corrected otroubi 2026-07-14 13:55:42 +03:00
  • c1031f6a26 DMA control module otroubi 2026-07-14 13:08:10 +03:00
  • d0f48ba513 controller_wrapper_axil with DMA control registers otroubi 2026-07-14 13:07:48 +03:00
  • d80f5ff31f fix: revert synchronizer changes (false changes) and sampler babintsev.lv 2026-07-14 13:02:55 +03:00
  • 19bade1c8c infra: update rtl_libs Phil 2026-07-14 12:18:57 +03:00
  • 493d6844c0 bug: TB tasks broken babintsev.lv 2026-07-10 18:52:52 +03:00
  • 11a9e97691 upd: reflectometer on axis bus iface + TB babintsev.lv 2026-07-10 18:46:48 +03:00
  • 0866b5da8d tests: add minimal tests for controller axi4l Phil 2026-07-10 17:51:48 +03:00
  • 126b66e4f5 fix: port names in axi4l reg_map Phil 2026-07-10 17:51:30 +03:00
  • 1ba94690d5 infra: update rtl libs Phil 2026-07-10 17:34:37 +03:00
  • 0ba25a3541 add: vrtual DAC & ADC subsystem for TB fix: makefile upd: clocking wiz IP babintsev.lv 2026-07-10 14:15:49 +03:00
  • c0a2f0e403 add window_size register otroubi 2026-07-10 14:15:17 +03:00
  • 7bd1aa68da add window_sizereg and cfg_bus_valid_reg otroubi 2026-07-10 14:03:07 +03:00
  • 061f8fe12b debugged controller otroubi 2026-07-10 13:13:18 +03:00
  • 99a344d534 debugging controller otroubi 2026-07-08 17:53:25 +03:00
  • 64f94a90e6 add: virtual DAC (100%) and ADC (80%) upd: makefile babintsev.lv 2026-07-08 17:47:56 +03:00
  • 7665afd50b add: half-baked reflectometer TB fix: constraints port names; ready: reflectometer top module babintsev.lv 2026-07-08 14:56:51 +03:00
  • e7c45101d1 rst added otroubi 2026-07-08 12:51:38 +03:00
  • fc3134f2d8 controller's changes otroubi 2026-07-08 12:50:28 +03:00
  • a82140feda add send signal to start a dma transaction otroubi 2026-07-08 12:49:51 +03:00
  • 9f99021168 infra: update gitignore for questa folder dev/accum_rework Phil 2026-07-07 17:47:21 +03:00
  • 9c70029f3e infra: add questa makefile Phil 2026-07-07 17:47:03 +03:00
  • 177c7d0bc2 infra: update makefile Phil 2026-07-07 17:45:32 +03:00
  • bafd084f0d rtl: dma descriptor and status transmitter logic otroubi 2026-07-07 17:33:53 +03:00
  • d71655885c rtl: axil wrapper logic for controller otroubi 2026-07-07 17:33:25 +03:00
  • 56e31a6cc6 rtl: add window_size register otroubi 2026-07-07 17:32:42 +03:00
  • 14a1df8bae rtl: controller module deconstruction otroubi 2026-07-07 17:32:13 +03:00
  • c3275d5b46 upd: ref babintsev.lv 2026-07-07 15:09:04 +03:00
  • 7b96fbddbf rtl: sampler modified otroubi 2026-07-07 15:05:14 +03:00
  • 2282eb4e16 Merge branch 'dev/design' of https://git.radiophotonics.ru/baulin.fa/reflectometer_fpga_project into dev/design otroubi 2026-07-07 14:58:18 +03:00
  • 287d855df4 rtl: sampler modified otroubi 2026-07-07 14:47:34 +03:00
  • 8e5b3929ac fix: missing state update Phil 2026-07-03 18:35:58 +03:00
  • df5469d538 tests: add new tests for accum Phil 2026-07-03 18:03:04 +03:00
  • 725826b07c add: new reflectometer top design (not ready) babintsev.lv 2026-07-03 16:32:48 +03:00
  • a6ade44b4d rtl: eth remove otroubi 2026-07-03 16:28:08 +03:00
  • 77526c44c2 tests: update accum TB Phil 2026-07-02 11:49:31 +03:00
  • 5010c42ae3 rtl: update accum_top to use dynamic window_size Phil 2026-07-02 11:33:40 +03:00
  • f0542845b0 rtl: rework out_axis_fifo Phil 2026-07-01 18:21:11 +03:00
  • 46333c3601 rtl: rework adder for dynamic window_size Phil 2026-07-01 18:06:56 +03:00
  • 2a3796a60f rtl: update accum - change window size to signal Phil 2026-07-01 14:57:23 +03:00
  • d878bac42a upd: new top design WIP babintsev.lv 2026-06-30 17:21:49 +03:00
  • 14f4a5eb2a rtl: register map addition for DMA control otroubi 2026-06-30 17:13:00 +03:00
  • 1eb21b5087 rtl: controller adc_dac management register map otroubi 2026-06-30 13:12:51 +03:00
  • 425c922690 rtl: update accum to support window_size < 3 Phil 2026-06-26 18:39:33 +03:00
  • 02416a9621 rtl: rework memory controls in accum Phil 2026-06-26 18:07:02 +03:00
  • 9285ce42e1 infra: add submodule otroubi 2026-06-26 17:52:26 +03:00
  • 771225cd77 fix: post-implementation timing sim TB passed babintsev.lv 2026-06-23 17:27:20 +03:00
  • b38a693676 fix: timing. New DAC-ADC line code Zer0Nu11 2026-06-20 09:33:33 +03:00
  • 789255fa04 fix: add timing sim tricks Zer0Nu11 2026-06-20 04:05:37 +03:00
  • efcd6ef5d0 upd: fast fix of sampler OTR. fix debug.xdc Major add of full automated testing for TB. Zer0Nu11 2026-06-20 03:07:05 +03:00
  • 4fbecd5e30 upd: sync design log verbosity + optimal delay latency Zer0Nu11 2026-06-19 20:49:17 +03:00
  • 8f342eebd7 Merge pull request 'dev/sw' (#14) from dev/sw into master master Филипп Баулин 2026-06-19 13:20:58 +03:00
  • 646cbb4c31 Merge branch 'master' into dev/sw dev/sw Филипп Баулин 2026-06-19 13:20:44 +03:00
  • d71aaf1650 fix: request/done protocol Zer0Nu11 2026-06-19 08:05:03 +03:00
  • 035d02234c Merge branch 'dev/design' of https://git.radiophotonics.ru/baulin.fa/reflectometer_fpga_project into dev/design Zer0Nu11 2026-06-19 08:00:44 +03:00
  • 4923f01322 upd: TB automation, DA->AD delay line for signal integrity Zer0Nu11 2026-06-19 08:00:00 +03:00
  • 45a57d57e4 sampler fix: made it beauty otroubi 2026-06-17 19:54:19 +03:00
  • 29e1541ffb Merge branch 'dev/design' of https://git.radiophotonics.ru/baulin.fa/reflectometer_fpga_project into dev/design otroubi 2026-06-17 19:32:46 +03:00
  • fd9280737d fix: refactoring babintsev.lv 2026-06-16 20:26:45 +03:00
  • 64843b462d rtl: sampler validation changes otroubi 2026-06-10 17:07:40 +03:00
  • c0714f271e Merge remote-tracking branch 'refs/remotes/origin/dev/design' into dev/design babintsev.lv 2026-06-10 16:44:00 +03:00
  • c165d346a0 update: new synchronizer + half-baked TB babintsev.lv 2026-06-10 16:40:53 +03:00
  • 753f4a2128 readme sampler modification otroubi 2026-06-10 16:31:02 +03:00
  • 6155c6a9fb change: sampler remark 2 otroubi 2026-06-10 16:23:20 +03:00
  • bb65aea4f1 change: sampler remarks otroubi 2026-06-10 16:22:05 +03:00
  • 5d3b761b07 change: delete makefile otroubi 2026-06-10 16:16:33 +03:00
  • d7e46445d8 change: delete tb otroubi 2026-06-10 16:15:53 +03:00
  • cacfe04061 change: naming problem otroubi 2026-06-10 16:14:29 +03:00
  • 4270c2fca8 rtl: final modified sampler otroubi 2026-06-10 15:50:39 +03:00
  • cf2985813a rtl: sampler synchronization modification otroubi 2026-06-10 13:10:50 +03:00
  • f670df9b54 Merge branch 'dev/design' of https://git.radiophotonics.ru/baulin.fa/reflectometer_fpga_project into dev/design Zer0Nu11 2026-06-10 12:01:57 +03:00
  • 6542995930 change: remove DAC strobing generation. RTL+TB complete Zer0Nu11 2026-06-10 11:59:36 +03:00
  • b0e886893b rtl: sampler synchronization work, not totally ready otroubi 2026-06-09 21:07:09 +03:00
  • d90167984a update: doc Zer0Nu11 2026-06-09 16:47:16 +03:00