baulin.fa/reflectometer_fpga_project
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Commit Graph

  • b54e69dec0 chore: add clocks for accum_fifo impl test dev/accum Phil 2026-04-21 19:48:20 +03:00
  • 7be26d9d1a chore: update tb files Phil 2026-04-21 19:47:56 +03:00
  • 3dcaaf8ea5 fix: better sync for accum fifo Phil 2026-04-21 19:47:46 +03:00
  • dfccc01225 tests: auto tb for out_axis_fifo Phil 2026-04-21 19:47:27 +03:00
  • 4eb937e13f infra: make default sim longer Phil 2026-04-21 19:46:51 +03:00
  • 21785aaac7 rtl: send part of out_axis_fifo Phil 2026-04-21 17:26:02 +03:00
  • 8e46f965df fix: incorrect fifo threshold value Phil 2026-04-17 21:58:20 +03:00
  • 7f9ad95e68 tests: add simple tb for accum output fifo Phil 2026-04-17 21:51:00 +03:00
  • 4786d2d7f6 rtl: wip accum output module, currently only with write part Phil 2026-04-17 21:50:30 +03:00
  • 58500b7549 Merge pull request 'dev/debug' (#6) from dev/debug into master master Филипп Баулин 2026-04-17 15:30:07 +03:00
  • 8b1e209da6 rtl: add project with eth and generator dev/debug Phil 2026-04-17 14:53:14 +03:00
  • 924f94986c chore: exclude bitstreams from git Phil 2026-04-17 14:50:23 +03:00
  • 83c714cd6f sw: update console, now can send actual data Phil 2026-04-17 14:44:27 +03:00
  • f54883a9e7 fix: constraint re-pin DAC to J11 header Phil 2026-04-17 14:43:31 +03:00
  • b9c75b823f fix: generator wrt signal incorrect clocking Phil 2026-04-17 14:42:20 +03:00
  • f863d09fb8 Merge pull request 'dev/controller' (#5) from dev/controller into master Филипп Баулин 2026-04-15 18:58:23 +03:00
  • 597be48407 docs: fix typos dev/controller Phil 2026-04-15 18:56:46 +03:00
  • f98051bc53 docs: add controller READMEs Phil 2026-04-15 18:54:07 +03:00
  • eea031c6c1 fix: broken (stuck) sim Phil 2026-04-15 18:53:49 +03:00
  • 500b10b327 sw: add console script prototype Phil 2026-04-15 18:28:03 +03:00
  • 851851828e fix: add missing constrain to Makefile Phil 2026-04-15 18:23:52 +03:00
  • 35e9feb87b tests: add sample project for eth+ctrl Phil 2026-04-15 17:57:16 +03:00
  • c41b08f539 fix: tricky packet check in ctrl Phil 2026-04-15 17:56:22 +03:00
  • ea7af4ed62 infra: init designs folder Phil 2026-04-15 13:40:19 +03:00
  • 6bb4f1efd8 infra: sim_top auto pick if exists in sim fileset Phil 2026-04-15 13:31:47 +03:00
  • dcf93fb307 infra: add build Makefile for controller test project Phil 2026-04-15 13:31:28 +03:00
  • 23f82b9445 tests: add controller tb Phil 2026-04-15 13:30:56 +03:00
  • bdb75fa298 infra: exclude temp scripts from git Phil 2026-04-15 13:19:08 +03:00
  • 003750d972 rtl: add controller first version Phil 2026-04-15 12:47:10 +03:00
  • 966d0379b7 Merge pull request 'dev/ethernet' (#4) from dev/ethernet into master Филипп Баулин 2026-04-14 15:42:08 +03:00
  • 7d1bfe25b4 infra: update constraints to use unified ones for board and additional for debug nodes dev/ethernet Phil 2026-04-14 15:39:21 +03:00
  • df6c204cbd docs: add readme to ethernet-udp Phil 2026-04-14 12:36:05 +03:00
  • 8907fea8a4 fix: signal in axis_mac Phil 2026-04-14 12:32:10 +03:00
  • 1c654f4e8e tests: add tb to axis_mac project Phil 2026-04-14 12:31:21 +03:00
  • c372dcd942 infra: add sim support to vivado.mk targets Phil 2026-04-14 12:30:30 +03:00
  • a3ed4919bc chore: add debug for base ethernet test Phil 2026-04-10 15:40:29 +03:00
  • d813855224 tests: add test project for ethernet echo & axis_mac tests Phil 2026-04-10 15:39:59 +03:00
  • 0480642167 chore: little refactor in eth stack Phil 2026-04-10 15:38:09 +03:00
  • c33afac783 rtl: implement axis UDP TX logic Phil 2026-04-10 15:37:19 +03:00
  • 26c627c988 rtl: add udp ram data count signal logic Phil 2026-04-10 15:35:26 +03:00
  • 879c4d49b2 infra: add vivado builds to gitignore Phil 2026-04-10 15:19:43 +03:00
  • 3544e3e2dc test: add sample top for axis loopback test Phil 2026-04-08 19:58:34 +03:00
  • 88db70ede8 Merge pull request 'rtl: generator added' (#1) from dev/generator into master ilianova.ds 2026-04-08 15:25:25 +03:00
  • ad6d6a4e2b Merge pull request 'rtl: sampler ready' (#2) from dev/sampler into master Филипп Баулин 2026-04-08 15:25:03 +03:00
  • 7a1c838de3 rtl: generator added dev/generator otroubi 2026-04-08 15:13:57 +03:00
  • 100feb0ea1 rtl: add constrains for axis eth fpga project Phil 2026-04-01 18:10:17 +03:00
  • 1310555b55 chore: remove old file Phil 2026-04-01 18:08:50 +03:00
  • c75443d170 test: udp axis rx Phil 2026-04-01 18:04:01 +03:00
  • 3a58119960 rtl: eth udp rx -> axis Phil 2026-04-01 18:03:47 +03:00
  • 221cb055f1 rtl: sampler ready dev/sampler otroubi 2026-04-01 11:46:59 +03:00
  • 0b9fb64193 rtl: add axis eth rx prototype Phil 2026-04-01 11:44:46 +03:00
  • a1386fc8a4 infra: add vivado.mk target for generic builds Phil 2026-03-31 15:08:28 +03:00
  • 7fedc36562 tests: add sample project for minimal eth udp echo Phil 2026-03-31 15:08:12 +03:00
  • 0dd0006e47 infra: add gitignore Phil 2026-03-31 12:53:25 +03:00
  • ded2afc0db rtl: add sources for ethernet udp stack Phil 2026-03-31 12:53:16 +03:00
  • aa1d45fe15 infra: init project structure baulin.fa 2026-03-25 16:17:55 +03:00
  • 1c9bce7927 chore: update readme Phil 2026-03-25 15:57:00 +03:00
  • 9d6cf8c0fb Initial commit Филипп Баулин 2026-03-25 15:48:16 +03:00