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sampler fix: made it beauty

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otroubi
2026-06-17 19:54:19 +03:00
parent 29e1541ffb
commit 45a57d57e4
1 changed files with 65 additions and 69 deletions
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134
rtl/sampler/src/sampler.sv
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@ -18,10 +18,10 @@ module sampler
output logic m_axis_tvalid,
output logic request
);
(* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] data_converted;
(* MARK_DEBUG="true" *) logic out_of_range_reg;
(* MARK_DEBUG="true" *) logic [31:0] smp_num_reg, cnt_smp_num;
(* MARK_DEBUG="true" *) logic enable, enable_d;
logic [DATA_WIDTH-1:0] data_converted;
logic out_of_range_reg;
logic [31:0] smp_num_reg, cnt_smp_num;
logic enable;
generate
if (PROCESS_MODE) begin
@ -53,42 +53,40 @@ module sampler
end
endgenerate
(* MARK_DEBUG="true" *) logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
(* MARK_DEBUG="true" *) logic buffer_ready;
logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
logic buffer_ready;
logic [$clog2(PACK_FACTOR):0] cnt;
generate
if (PACK_FACTOR == 1) begin
always @(posedge clk_in) begin
if (rst) begin
buffer <= '0;
buffer_ready <= 0;
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= 0;
request <= 0;
end
else begin
buffer_ready <= 0;
if (!enable) begin
if (request && done) begin
enable <= 1;
request <= 0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end else begin
request <= 1;
end
end else begin
if (cnt_smp_num != smp_num_reg) begin
cnt_smp_num <= cnt_smp_num +1;
buffer_ready <= 1;
if (!out_of_range_reg) begin
buffer <= data_converted;
end
if (PACK_FACTOR == 1) begin
always @(posedge clk_in) begin
if (rst) begin
buffer <= '0;
buffer_ready <= 0;
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= 0;
request <= 0;
end
else begin
buffer_ready <= 0;
if (!enable) begin
if (request && done) begin
enable <= 1;
request <= 0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end else begin
request <= 1;
end
else begin
end else begin
if (cnt_smp_num != smp_num_reg) begin
cnt_smp_num <= cnt_smp_num +1;
buffer_ready <= 1;
if (!out_of_range_reg) begin
buffer <= data_converted;
end
end else begin
cnt_smp_num <= '0;
buffer_ready <= 0;
enable <= 0;
@ -97,44 +95,42 @@ module sampler
end
end
end
end else begin
always @(posedge clk_in) begin
if (rst) begin
buffer <= '0;
cnt <= '0; //
buffer_ready <= 0;
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= 0;
request <= 0;
end
else begin
buffer_ready <= 0;
if (!enable) begin
if (request && done) begin
enable <= 1;
request <= 0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end else begin
request <= 1;
end
end else begin
always @(posedge clk_in) begin
if (rst) begin
buffer <= '0;
cnt <= '0;
buffer_ready <= 0;
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= 0;
request <= 0;
end else begin
if (cnt_smp_num != smp_num_reg) begin
cnt_smp_num <= cnt_smp_num +1;
buffer_ready <= 1;
if (!out_of_range_reg) begin
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
if (cnt == PACK_FACTOR-1) begin
cnt <= 0;
buffer_ready <= 0;
if (!enable) begin
if (request && done) begin
enable <= 1;
request <= 0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end else begin
request <= 1;
end
end else begin
if (cnt_smp_num != smp_num_reg) begin
cnt_smp_num <= cnt_smp_num +1;
buffer_ready <= 1;
if (!out_of_range_reg) begin
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
end
if (cnt == PACK_FACTOR-1) begin
cnt <= 0;
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
end
else begin
cnt <= cnt + 1;
end
end
end
else begin
end else begin
cnt_smp_num <= '0;
buffer_ready <= 0;
enable <= 0;
@ -142,8 +138,8 @@ module sampler
end
end
end
end
end
end
endgenerate
assign m_axis_tdata = buffer;