update: new synchronizer + half-baked TB
This commit is contained in:
@ -1,10 +1,3 @@
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# Primary clocks
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create_clock -name eth_clk -period 8.000 [get_ports dac_clk_in]
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create_clock -name acc_clk -period 15.385 [get_ports adc_clk_in]
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# Asynchronous clock groups
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set_clock_groups -name ASYNC_ETH_ACC -asynchronous \
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-group [get_clocks eth_clk] \
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-group [get_clocks acc_clk]
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create_clock -name acc_clk -period 15.385 [get_ports adc_clk_in]
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@ -2,113 +2,104 @@
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module sync_top
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#(
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parameter int unsigned DAC_DATA_WIDTH = 14,
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parameter int unsigned ADC_DATA_WIDTH = 12,
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parameter int unsigned PACK_FACTOR = 1,
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parameter int unsigned PROCESS_MODE = 0
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parameter int unsigned DAC_DATA_WIDTH = 14, // DAC bit-width
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parameter int unsigned ADC_DATA_WIDTH = 12, // ADC bit-width
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parameter int unsigned PACK_FACTOR = 1, // number of ADC readings per transaction
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parameter int unsigned PROCESS_MODE = 0, // representation format of ADC readings (0 - direct code, 1 - 2's completment)
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parameter int unsigned ZERO_LEVEL = 0
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)
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(
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input adc_clk_in,
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input adc_rst,
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input dac_clk_in,
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input dac_rst,
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input dac_start,
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input clk_adc,
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input rst_adc,
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input clk_dac,
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input rst_dac,
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input start,
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input out_of_range,
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input [31:0] pulse_width,
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input [31:0] pulse_period,
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input [DAC_DATA_WIDTH-1:0] pulse_height,
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input [15:0] pulse_num,
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input [31:0] smp_num,
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output logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
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output logic m_axis_tvalid
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input [15:0] pulse_num, // DAC counter limit
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input [31:0] smp_num, // ADC counter limit
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output [ADC_DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
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output m_axis_tvalid
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);
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//------------------------------------------------------------
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// Internal signals
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//------------------------------------------------------------
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(* MARK_DEBUG="true" *) logic sample_req;
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(* MARK_DEBUG="true" *) logic sample_req_sync1;
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(* MARK_DEBUG="true" *) logic sample_req_sync2;
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(* MARK_DEBUG="true" *) logic sample_req_sync3;
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(* MARK_DEBUG="true" *) logic sample_done;
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(* MARK_DEBUG="true" *) logic sample_done_sync1;
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(* MARK_DEBUG="true" *) logic sample_done_sync2;
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(* MARK_DEBUG="true" *) logic sample_done_sync3;
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(* MARK_DEBUG="true" *) logic pulse;
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(* MARK_DEBUG="true" *) logic [DAC_DATA_WIDTH-1:0] pulse_height_out;
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//------------------------------------------------------------
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// Simple DAC -> ADC test source
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//
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// generator output is directly connected to sampler input
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// with width truncation:
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//
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// pulse_height_out[13:0] -> data_in[11:0]
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//------------------------------------------------------------
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(* MARK_DEBUG="true" *) logic [ADC_DATA_WIDTH-1:0] data_in;
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(* MARK_DEBUG="true" *) logic out_of_range;
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assign data_in = pulse_height_out[ADC_DATA_WIDTH-1:0];
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assign out_of_range = 1'b0;
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wire dac_done, dac_request, adc_done, adc_request;
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wire [DAC_DATA_WIDTH-1:0] dac_signal;
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wire [ADC_DATA_WIDTH-1:0] adc_singnal;
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generate
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if (ADC_DATA_WIDTH > DAC_DATA_WIDTH) begin : g_pad_zeros
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assign adc_singnal = { {(ADC_DATA_WIDTH - DAC_DATA_WIDTH){1'b0}}, dac_signal };
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end
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else begin : g_truncate
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assign adc_singnal = dac_signal[ADC_DATA_WIDTH-1:0];
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end
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endgenerate
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//------------------------------------------------------------
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// DAC -> ADC CDC
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//------------------------------------------------------------
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always_ff @(posedge adc_clk_in or posedge adc_rst) begin
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if (adc_rst) begin
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sample_req <= 1'b0;
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sample_req_sync2 <= 1'b0;
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sample_req_sync3 <= 1'b0;
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end
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logic [2:0] stretch; // 125/65~=2. Чтобы поймать единичный импульс, растянем его во времени
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logic [1:0] sync_DA;
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wire dac_done_stretched;
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always_ff @(posedge clk_dac or posedge rst_dac)
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begin
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if (rst_dac)
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stretch <= 0;
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else begin
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sample_req_sync2 <= sample_req_sync1;
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sample_req_sync3 <= sample_req_sync2;
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sample_req <= sample_req_sync3;
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stretch[0] <= dac_done;
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stretch[1] <= stretch[0];
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stretch[2] <= stretch[1];
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end
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end
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assign dac_done_stretched = |stretch;
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always_ff @(posedge clk_adc or posedge rst_adc) begin
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if (rst_adc)
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sync_DA <= 0;
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else begin
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sync_DA[0] <= dac_done_stretched;
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sync_DA[1] <= sync_DA[0];
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end
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end
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assign adc_request = sync_DA[1];
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//------------------------------------------------------------
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// ADC -> DAC CDC
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//------------------------------------------------------------
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always_ff @(posedge dac_clk_in or posedge dac_rst) begin
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if (dac_rst) begin
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sample_done <= 1'b0;
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sample_done_sync2 <= 1'b0;
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sample_done_sync3 <= 1'b0;
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end
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logic [1:0] sync_AD;
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always_ff @(posedge clk_dac or posedge rst_dac) begin
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if (rst_dac)
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sync_AD <= 0;
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else begin
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sample_done_sync2 <= sample_done_sync1;
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sample_done_sync3 <= sample_done_sync2;
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sample_done <= sample_done_sync3;
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sync_AD[0] <= adc_done;
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sync_AD[1] <= sync_AD[0];
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end
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end
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assign dac_request = sync_AD[1];
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//------------------------------------------------------------
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// Generator
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//------------------------------------------------------------
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generator #(
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.DATA_WIDTH(DAC_DATA_WIDTH)
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.DATA_WIDTH(DAC_DATA_WIDTH),
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.ZERO_LEVEL(ZERO_LEVEL)
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) generator_inst (
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.clk_in(dac_clk_in),
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.rst(dac_rst),
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.start(dac_start),
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.clk_dac(clk_dac),
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.rst(rst_dac),
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.start(start),
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.pulse_width(pulse_width),
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.pulse_period(pulse_period),
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.pulse_height(pulse_height),
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.pulse_num(pulse_num),
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.sample_done(sample_done),
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.pulse(pulse),
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.pulse_height_out(pulse_height_out),
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.sample_req(sample_req_sync1)
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.dac_out(dac_signal),
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.request(dac_request),
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.done(dac_done)
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);
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//------------------------------------------------------------
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@ -119,18 +110,15 @@ module sync_top
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.PACK_FACTOR(PACK_FACTOR),
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.PROCESS_MODE(PROCESS_MODE)
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) sampler_inst (
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.clk_in(adc_clk_in),
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.rst(adc_rst),
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.data_in(data_in),
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.clk_in(clk_adc),
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.rst(rst_adc),
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.data_in(adc_singnal),
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.out_of_range(out_of_range),
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.smp_num(smp_num),
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.sample_req(sample_req),
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.m_axis_tdata(m_axis_tdata),
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.m_axis_tvalid(m_axis_tvalid),
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.sample_done(sample_done_sync1)
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.request(adc_request),
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.done(adc_done)
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);
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endmodule
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@ -2,39 +2,45 @@
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module tb_top;
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localparam DAC_DATA_WIDTH = 14;
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localparam ADC_DATA_WIDTH = 12;
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localparam PACK_FACTOR = 1;
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localparam PROCESS_MODE = 0;
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//------------------------------------------------------------
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// Параметры
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//------------------------------------------------------------
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localparam DAC_DATA_WIDTH = 14;
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localparam ADC_DATA_WIDTH = 12;
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localparam PACK_FACTOR = 1;
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localparam PROCESS_MODE = 0;
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localparam LOGIC_ZERO_LEVEL = 0; // DAC -5V for logic zero
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localparam VOLTAGE_ZERO_LEVEL = 2**(DAC_DATA_WIDTH-1); // DAC 0V for logic zero
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localparam CLK_DAC_PERIOD = 8;
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localparam CLK_ADC_PERIOD = 15.385;
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localparam ZERO_LEVEL = LOGIC_ZERO_LEVEL; // "logic" VS "true"
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//------------------------------------------------------------
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// clocks / reset
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// Тактовые сигналы и сброс
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//------------------------------------------------------------
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logic adc_clk_in;
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logic adc_rst;
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logic dac_clk_in;
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logic dac_rst;
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logic clk_dac;
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logic rst_dac;
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logic clk_adc;
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logic rst_adc;
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//------------------------------------------------------------
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// control
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// Управление и конфиг
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//------------------------------------------------------------
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logic dac_start;
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logic [31:0] pulse_width;
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logic [31:0] pulse_period;
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logic [DAC_DATA_WIDTH-1:0] pulse_height;
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logic [15:0] pulse_num;
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logic [31:0] smp_num;
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logic [31:0] pulse_width;
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logic [31:0] pulse_period;
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logic [DAC_DATA_WIDTH-1:0] pulse_height;
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logic [15:0] pulse_num;
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logic [31:0] smp_num;
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//------------------------------------------------------------
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// outputs
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// Входы
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//------------------------------------------------------------
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logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
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logic m_axis_tvalid;
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integer valid_count;
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reg out_of_range;
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//------------------------------------------------------------
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// Выходы
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//------------------------------------------------------------
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wire [ADC_DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
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wire m_axis_tvalid;
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//------------------------------------------------------------
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// DUT
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//------------------------------------------------------------
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@ -42,127 +48,260 @@ module tb_top;
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
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.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
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.PACK_FACTOR(PACK_FACTOR),
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.PROCESS_MODE(PROCESS_MODE)
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.PROCESS_MODE(PROCESS_MODE),
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.ZERO_LEVEL(ZERO_LEVEL)
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) dut (
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.adc_clk_in(adc_clk_in),
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.adc_rst(adc_rst),
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.dac_clk_in(dac_clk_in),
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.dac_rst(dac_rst),
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.dac_start(dac_start),
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.clk_adc(clk_adc),
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.clk_dac(clk_dac),
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.rst_adc(rst_adc),
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.rst_dac(rst_dac),
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.start(dac_start),
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.pulse_width(pulse_width),
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.pulse_period(pulse_period),
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.pulse_height(pulse_height),
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.pulse_num(pulse_num),
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.smp_num(smp_num),
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.m_axis_tdata(m_axis_tdata),
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.m_axis_tvalid(m_axis_tvalid)
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.m_axis_tvalid(m_axis_tvalid),
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.out_of_range(out_of_range)
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);
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//------------------------------------------------------------
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// ADC clock
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//------------------------------------------------------------
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// Тактовые сигналы
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initial begin
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adc_clk_in = 1'b0;
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forever #5 adc_clk_in = ~adc_clk_in; // 100 MHz
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clk_adc = 0;
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forever #(CLK_ADC_PERIOD/2) clk_adc = ~clk_adc;
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end
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initial begin
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clk_dac = 0;
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forever #(CLK_DAC_PERIOD/2) clk_dac = ~clk_dac;
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end
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//------------------------------------------------------------
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// DAC clock
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//------------------------------------------------------------
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// === Таски для тестипрования ===
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// Таска сброса DAC DUT
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task automatic reset_dut_dac(
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input int rst_duration // сколько тактов держать сброс
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);
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rst_dac <= 1;
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repeat(rst_duration) @(posedge clk_dac);
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rst_dac <= 0;
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endtask
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// Таска сброса ADC DUT
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task automatic reset_dut_adc(
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input int rst_duration // сколько тактов держать сброс
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);
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rst_adc <= 1;
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repeat(rst_duration) @(posedge clk_adc);
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rst_adc <= 0;
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endtask
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// Таска запуска DUT
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task automatic start_dut(
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input int start_duration // сколько тактов держать импульс
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);
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dac_start <= 1;
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repeat(start_duration) @(posedge clk_dac);
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dac_start <= 0;
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endtask
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// Таска конфигурации DUT
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task automatic set_config(
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input logic [31:0] w, // ширина импульса
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input logic [31:0] p, // период импульса
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input logic [15:0] n, // количество импульсов
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input logic [DAC_DATA_WIDTH-1:0] h, // высота импульса
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input logic [31:0] sn // число сэмплов
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);
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// Задаем конфигурационные регистры
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@(posedge clk_dac);
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pulse_width <= w;
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pulse_period <= p;
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pulse_num <= n;
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pulse_height <= h;
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smp_num <= sn;
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endtask
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// // Таска проверки устойчивости к долгим управляющим импульсам
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// task automatic check_impulses;
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// // Локальные переменные для хранения случайных параметров
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// int rand_start_duration;
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// int rand_delay;
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// int rand_ack;
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// bit rand_first;
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// int total_impulse_cycles = 0;
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// int pulse_w = 11;
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// int pulse_p = 31;
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// int pulse_n = 5;
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// int pulse_h = 1024;
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// $display("[TB] -check_impulses- Check system stability under random latencies");
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// // Установка конфигурации
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// set_config(
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// .w(pulse_w),
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// .p(pulse_p),
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// .n(pulse_n),
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// .h(pulse_h)
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// );
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// reset_dut(5);
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// repeat(2) @(posedge clk);
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// // Старт норме 1 такт. Сделаем случайным от 5 до 25 тактов.
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// rand_start_duration = $urandom_range(5, 25);
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// $display("[TB] Long start: %0d clocks", rand_start_duration);
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// // Фоновый процесс подсчета тактов импульса
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// fork
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// begin : counter_proc
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// forever begin
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// @(negedge clk); // 180 deg. phase shift for "DAC strobing signal"
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// if (dac_out == pulse_h) begin
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// total_impulse_cycles++;
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// end
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// end
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// end
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// join_none
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// // Параллельный запуск длинного старта и обработки синхронизации
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// fork
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// // Поток 1: Удерживаем старт аномально долго
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// begin
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// start_dut(rand_start_duration);
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// end
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// // Поток 2: Обслуживаем n=4 циклов синхронизации со случайными задержками
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// begin
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// repeat(pulse_n) begin
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// // Рандомизируем параметры для каждого из 4-х рукопожатий
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// rand_first = $urandom; // Случайно: Самплер первый (1) или Генератор первый (0)
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// rand_delay = $urandom_range(1, 8); // Случайная задержка ожидания (1..8 тактов)
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// rand_ack = $urandom_range(5, 10); // Аномально долгий удерживаемый импульс sampler_done (10..30 тактов)
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// synchronize(
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// .sampler_first(rand_first),
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// .delay_before_ack(rand_delay),
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// .ack_duration(rand_ack)
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// );
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// end
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// end
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// join
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// repeat(pulse_p+5) @(posedge clk);
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// disable counter_proc;
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// // Ожидание завершения переходных процессов
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// repeat(10) @(posedge clk);
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// if (total_impulse_cycles == pulse_w*pulse_n)
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// $display("[TB] -check_impulses- Pulse generation CORRECT");
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// else begin
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// $display("[ERROR] -check_impulses- Pulse generation INCORRECT. Total number of pulses: %d, must be: %d", total_impulse_cycles, pulse_w*pulse_n);
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// $finish;
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// end
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// $display("[TB] -check_impulses- Done");
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// endtask
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// task automatic run_test_case(
|
||||
// input int pulse_w,
|
||||
// input int pulse_p,
|
||||
// input int pulse_n,
|
||||
// input int pulse_h,
|
||||
// input bit skip_reset, // skip reset sequence on demand
|
||||
// input bit count_level // count ticks of amplitude == pulse_h or amplitude != pulse_h
|
||||
// );
|
||||
// int total_impulse_cycles = 0;
|
||||
|
||||
// if (!skip_reset) begin
|
||||
// reset_dut(1);
|
||||
// @(posedge clk);
|
||||
// end
|
||||
|
||||
// set_config(
|
||||
// .w(pulse_w),
|
||||
// .p(pulse_p),
|
||||
// .n(pulse_n),
|
||||
// .h(pulse_h)
|
||||
// );
|
||||
// @(posedge clk);
|
||||
|
||||
// start_dut(1);
|
||||
|
||||
// // Фоновый процесс подсчета тактов импульса
|
||||
// fork
|
||||
// begin : counter_proc
|
||||
// forever begin
|
||||
// @(negedge clk); // 180 deg. phase shift for "DAC strobing signal"
|
||||
// if (count_level) begin
|
||||
// if (dac_out == pulse_h) begin
|
||||
// total_impulse_cycles++;
|
||||
// end
|
||||
// end
|
||||
// else begin
|
||||
// if (dac_out != current_zero_level) begin
|
||||
// total_impulse_cycles++;
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
// join_none
|
||||
|
||||
// repeat(pulse_n) begin
|
||||
// synchronize(
|
||||
// .sampler_first(0),
|
||||
// .delay_before_ack(1),
|
||||
// .ack_duration(2)
|
||||
// );
|
||||
// end
|
||||
// repeat(pulse_p+5) @(posedge clk);
|
||||
// disable counter_proc;
|
||||
// repeat(10) @(posedge clk);
|
||||
|
||||
// if (count_level) begin
|
||||
// if (total_impulse_cycles == pulse_w*pulse_n)
|
||||
// $display("[TB] -run_test_case- Pulse generation CORRECT");
|
||||
// else begin
|
||||
// $display("[ERROR] -run_test_case- Pulse generation INCORRECT. Total number of pulses: %d, must be: %d", total_impulse_cycles, pulse_w*pulse_n);
|
||||
// $finish;
|
||||
// end
|
||||
// end
|
||||
// else begin
|
||||
// if (total_impulse_cycles == 0)
|
||||
// $display("[TB] -run_test_case- Pulse generation CORRECT");
|
||||
// else begin
|
||||
// $display("[ERROR] -run_test_case- Pulse generation INCORRECT. Total number of pulses: %d, must be: %d", total_impulse_cycles, 0);
|
||||
// $finish;
|
||||
// end
|
||||
// end
|
||||
// endtask
|
||||
|
||||
// --- ОСНОВНОЙ ПРОЦЕСС ТЕСТИРОВАНИЯ ---
|
||||
initial begin
|
||||
dac_clk_in = 1'b0;
|
||||
forever #8 dac_clk_in = ~dac_clk_in; // slower domain
|
||||
end
|
||||
|
||||
//------------------------------------------------------------
|
||||
// monitor output stream
|
||||
//------------------------------------------------------------
|
||||
always @(posedge adc_clk_in) begin
|
||||
if (m_axis_tvalid) begin
|
||||
valid_count = valid_count + 1;
|
||||
|
||||
$display("[%0t] VALID: data=%0d",
|
||||
$time,
|
||||
m_axis_tdata);
|
||||
end
|
||||
end
|
||||
|
||||
//------------------------------------------------------------
|
||||
// test
|
||||
//------------------------------------------------------------
|
||||
initial begin
|
||||
|
||||
adc_rst = 1'b1;
|
||||
dac_rst = 1'b1;
|
||||
|
||||
dac_start = 1'b0;
|
||||
$display("[TB] Tests start");
|
||||
|
||||
// Инициализация
|
||||
dac_start = 0;
|
||||
pulse_width = 0;
|
||||
pulse_period = 0;
|
||||
pulse_height = 0;
|
||||
pulse_num = 0;
|
||||
smp_num = 0;
|
||||
out_of_range = 0;
|
||||
fork
|
||||
reset_dut_adc(3);
|
||||
reset_dut_dac(6);
|
||||
join
|
||||
@(posedge clk_dac);
|
||||
@(posedge clk_adc);
|
||||
set_config(
|
||||
.w(50),
|
||||
.p(125),
|
||||
.n(5),
|
||||
.h(1024),
|
||||
.sn(65)
|
||||
);
|
||||
start_dut(1);
|
||||
|
||||
valid_count = 0;
|
||||
|
||||
//--------------------------------------------------------
|
||||
// reset
|
||||
//--------------------------------------------------------
|
||||
repeat (10) @(posedge adc_clk_in);
|
||||
repeat (10) @(posedge dac_clk_in);
|
||||
|
||||
adc_rst = 1'b0;
|
||||
dac_rst = 1'b0;
|
||||
|
||||
repeat (5) @(posedge dac_clk_in);
|
||||
|
||||
//--------------------------------------------------------
|
||||
// config
|
||||
//--------------------------------------------------------
|
||||
pulse_width = 32'd3;
|
||||
pulse_period = 32'd8;
|
||||
pulse_height = 14'd200;
|
||||
pulse_num = 16'd4;
|
||||
smp_num = 32'd8;
|
||||
|
||||
//--------------------------------------------------------
|
||||
// start
|
||||
//--------------------------------------------------------
|
||||
@(posedge dac_clk_in);
|
||||
dac_start = 1'b1;
|
||||
|
||||
@(posedge dac_clk_in);
|
||||
dac_start = 1'b0;
|
||||
|
||||
$display("==================================");
|
||||
$display("TEST START");
|
||||
$display("==================================");
|
||||
|
||||
//--------------------------------------------------------
|
||||
// wait
|
||||
//--------------------------------------------------------
|
||||
repeat (600) @(posedge adc_clk_in);
|
||||
|
||||
//--------------------------------------------------------
|
||||
// check
|
||||
//--------------------------------------------------------
|
||||
if (valid_count > 0) begin
|
||||
$display("==================================");
|
||||
$display("TEST PASSED");
|
||||
$display("valid_count = %0d", valid_count);
|
||||
$display("==================================");
|
||||
end
|
||||
else begin
|
||||
$display("==================================");
|
||||
$display("TEST FAILED");
|
||||
$display("No valid output detected");
|
||||
$display("==================================");
|
||||
end
|
||||
|
||||
|
||||
$display("[TB] ALL PASSED");
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
Reference in New Issue
Block a user