test: add proper cfg tests

rtl/controller/tests/test_controller.py

@@ -98,12 +98,33 @@ async def simple_controller_config_write(dut):
     assert await tb.read_reg(REG_DAC_WIDTH) == 0x10
     assert await tb.read_reg(REG_WINDOW_SIZE) == 16
 
-    # W1S pulse: bit 2 = cfg_bus_valid_o.
+    # write data: set cfg_bus_valid signal
     await tb.write_reg(REG_CONTROL, 1 << CTRL_CFG_BUS_VALID)
 
+    # wait
+    for _ in range(30):
+        await RisingEdge(dut.ctrl_clk)
+
+    # check config
+    assert int(dut.dac_pulse_width) == 0x10
+    assert int(dut.dac_pulse_period) == 0x40
+    assert int(dut.dac_pulse_num) == 3
+    assert int(dut.dac_pulse_height) == 0x7FF
+    assert int(dut.adc_pulse_period) == 0x80
+    assert int(dut.adc_window_size) == 16
+
     await RisingEdge(dut.ctrl_clk)
 
 
+@cocotb.test()
+async def simple_controller_start_check(dut):
+    tb = TB(dut)
+    await tb.reset()
+    await tb.write_reg(REG_CONTROL, 1 << CTRL_START)
+
+    await RisingEdge(dut.dac_start)
+
+
 @cocotb.test()
 async def simple_dma_desc_register_write(dut):
     tb = TB(dut)