baulin.fa/reflectometer_fpga_project
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Commit Graph

  • 51d715a728 chore: generator little fix otroubi 2026-05-15 13:47:08 +03:00
  • 9efbd6586f chore: generator evolution otroubi 2026-05-15 13:36:10 +03:00
  • eacffd44b3 docs: update ctrl readme Phil 2026-05-12 13:47:51 +03:00
  • 5c1866d571 chore: re-organise designs for better hierarchy dev/ax7102 Phil 2026-05-12 13:25:44 +03:00
  • f9f4a10cdf infra: fix constraints - adc Phil 2026-05-12 13:23:42 +03:00
  • e6cb0e0f6e Merge branch 'dev/ax7102' into dev/design Phil 2026-05-08 19:07:58 +03:00
  • dad163b6ac infra: update scripts to auto-upgrade ip Phil 2026-05-08 19:04:21 +03:00
  • 3a2d8eda2b rtl: reorganised top without eth otroubi 2026-05-08 19:03:24 +03:00
  • 78095ad9a1 chore: update eth_test_minimal to a100 Phil 2026-05-08 18:49:27 +03:00
  • c77b54aec6 chore: update eth_axis to a100 Phil 2026-05-08 18:43:49 +03:00
  • 429cf3d085 chore: update eth_test_minimal to a100 Phil 2026-05-08 18:43:26 +03:00
  • 7f6a3e03a1 infra: add constraints for ax7102 board Phil 2026-05-08 17:26:24 +03:00
  • 66a15cd6e0 test: more cases for accum Phil 2026-05-08 16:43:53 +03:00
  • f2a8d8a28e sw: update console with new packet changes Phil 2026-05-08 16:05:53 +03:00
  • ecb2ed3b7f rtl: update controller to support different smp_num for adc/dac sides Phil 2026-05-08 15:59:20 +03:00
  • 2a928c2407 rtl: add more debug nodes for reflectometer Phil 2026-05-08 15:58:33 +03:00
  • bc0a1c8b66 fix: signal names in reflectometer Phil 2026-05-08 15:58:11 +03:00
  • 9b72dfb8d9 fix: cnt_smp_num sampler otroubi 2026-05-08 14:08:01 +03:00
  • 8c4154baf0 rtl: reflectometer add synchronizer logic otroubi 2026-05-06 15:38:25 +03:00
  • c279f1158d chore: clean code sync_top otroubi 2026-05-06 15:37:15 +03:00
  • 4fc354955c rtl: debug synchronizer project makefile otroubi 2026-05-06 14:41:26 +03:00
  • 57570bea00 rtl: debug synchronizer project constraints otroubi 2026-05-06 14:41:15 +03:00
  • 03d0abbe86 rtl: debug synchronizer project testbench otroubi 2026-05-06 14:40:53 +03:00
  • d26bc29507 rtl: debug synchronizer project otroubi 2026-05-06 14:40:33 +03:00
  • e9c39ea344 rtl: generator synchronizer update otroubi 2026-05-06 14:31:37 +03:00
  • 7c3fe36df1 rtl: sampler synchronizer update otroubi 2026-05-06 14:30:23 +03:00
  • f719533eb9 chore: generator and sampler brushed otroubi 2026-04-30 13:14:26 +03:00
  • 179347659b rtl: update reflectometer top design Phil 2026-04-30 13:10:41 +03:00
  • 9fd311d671 chore: add debug XDC for main project Phil 2026-04-30 13:05:33 +03:00
  • a018b3d215 fix: bad checksums in axis_mac Phil 2026-04-30 13:05:06 +03:00
  • 138c5d7dce dev: full project reflectometer otroubi 2026-04-28 17:18:41 +03:00
  • 16cef61a88 rtl: add sample reflectometer project mock Phil 2026-04-28 17:05:14 +03:00
  • d68c22211d chore: update constraints to debug ADC + simple DAC Phil 2026-04-28 16:58:36 +03:00
  • b7409534ed Merge pull request 'dev/accum' (#7) from dev/accum into master baulin.fa 2026-04-28 16:20:58 +03:00
  • 3ea03fd40c docs: add README for accum dev/accum Phil 2026-04-28 15:36:59 +03:00
  • ea381320f3 Merge branch 'dev/accum' of https://git.radiophotonics.ru/baulin.fa/reflectometer_fpga_project into dev/accum Phil 2026-04-28 15:36:34 +03:00
  • bd8dc9d0d3 chore: fix readme otroubi 2026-04-28 15:25:51 +03:00
  • 2e22eb68df docs: add sampler_readme otroubi 2026-04-28 15:21:58 +03:00
  • d5c3ff873f infra: add sample makefile Phil 2026-04-28 14:41:56 +03:00
  • 5f1f4e5a16 rtl: new tb otroubi 2026-04-28 13:57:28 +03:00
  • 4efc2f02a9 infra: increase sim time for larger tests Phil 2026-04-28 13:29:05 +03:00
  • 312bc0c798 fix: automate tb Phil 2026-04-28 13:28:49 +03:00
  • c4a7c21bea fix: clock name un xdc Phil 2026-04-28 13:13:40 +03:00
  • e083cd5c2e rtl: update accum to support real cases Phil 2026-04-28 13:13:27 +03:00
  • 264c9ecb8e rtl: update sampler otroubi 2026-04-28 13:10:22 +03:00
  • fc0e710b3e tests: add waveconfigs Phil 2026-04-28 12:11:41 +03:00
  • 275055291e fix: update names in out_axis_fifo_tb Phil 2026-04-28 11:57:53 +03:00
  • 002f0cace5 test: add full testbenches for accum Phil 2026-04-28 11:57:13 +03:00
  • 91eaf6c4f8 fix: out_axis_fifo states Phil 2026-04-28 11:56:19 +03:00
  • 9b189f931f rtl: update accum design Phil 2026-04-28 11:55:46 +03:00
  • a8a3aff498 rtl: first impl of adder+accum Phil 2026-04-22 16:38:22 +03:00
  • b54e69dec0 chore: add clocks for accum_fifo impl test Phil 2026-04-21 19:48:20 +03:00
  • 7be26d9d1a chore: update tb files Phil 2026-04-21 19:47:56 +03:00
  • 3dcaaf8ea5 fix: better sync for accum fifo Phil 2026-04-21 19:47:46 +03:00
  • dfccc01225 tests: auto tb for out_axis_fifo Phil 2026-04-21 19:47:27 +03:00
  • 4eb937e13f infra: make default sim longer Phil 2026-04-21 19:46:51 +03:00
  • 21785aaac7 rtl: send part of out_axis_fifo Phil 2026-04-21 17:26:02 +03:00
  • 8e46f965df fix: incorrect fifo threshold value Phil 2026-04-17 21:58:20 +03:00
  • 7f9ad95e68 tests: add simple tb for accum output fifo Phil 2026-04-17 21:51:00 +03:00
  • 4786d2d7f6 rtl: wip accum output module, currently only with write part Phil 2026-04-17 21:50:30 +03:00
  • 58500b7549 Merge pull request 'dev/debug' (#6) from dev/debug into master baulin.fa 2026-04-17 15:30:07 +03:00
  • 8b1e209da6 rtl: add project with eth and generator dev/debug Phil 2026-04-17 14:53:14 +03:00
  • 924f94986c chore: exclude bitstreams from git Phil 2026-04-17 14:50:23 +03:00
  • 83c714cd6f sw: update console, now can send actual data Phil 2026-04-17 14:44:27 +03:00
  • f54883a9e7 fix: constraint re-pin DAC to J11 header Phil 2026-04-17 14:43:31 +03:00
  • b9c75b823f fix: generator wrt signal incorrect clocking Phil 2026-04-17 14:42:20 +03:00
  • f863d09fb8 Merge pull request 'dev/controller' (#5) from dev/controller into master baulin.fa 2026-04-15 18:58:23 +03:00
  • 597be48407 docs: fix typos Phil 2026-04-15 18:56:46 +03:00
  • f98051bc53 docs: add controller READMEs Phil 2026-04-15 18:54:07 +03:00
  • eea031c6c1 fix: broken (stuck) sim Phil 2026-04-15 18:53:49 +03:00
  • 500b10b327 sw: add console script prototype Phil 2026-04-15 18:28:03 +03:00
  • 851851828e fix: add missing constrain to Makefile Phil 2026-04-15 18:23:52 +03:00
  • 35e9feb87b tests: add sample project for eth+ctrl Phil 2026-04-15 17:57:16 +03:00
  • c41b08f539 fix: tricky packet check in ctrl Phil 2026-04-15 17:56:22 +03:00
  • ea7af4ed62 infra: init designs folder Phil 2026-04-15 13:40:19 +03:00
  • 6bb4f1efd8 infra: sim_top auto pick if exists in sim fileset Phil 2026-04-15 13:31:47 +03:00
  • dcf93fb307 infra: add build Makefile for controller test project Phil 2026-04-15 13:31:28 +03:00
  • 23f82b9445 tests: add controller tb Phil 2026-04-15 13:30:56 +03:00
  • bdb75fa298 infra: exclude temp scripts from git Phil 2026-04-15 13:19:08 +03:00
  • 003750d972 rtl: add controller first version Phil 2026-04-15 12:47:10 +03:00
  • 966d0379b7 Merge pull request 'dev/ethernet' (#4) from dev/ethernet into master baulin.fa 2026-04-14 15:42:08 +03:00
  • 7d1bfe25b4 infra: update constraints to use unified ones for board and additional for debug nodes dev/ethernet Phil 2026-04-14 15:39:21 +03:00
  • df6c204cbd docs: add readme to ethernet-udp Phil 2026-04-14 12:36:05 +03:00
  • 8907fea8a4 fix: signal in axis_mac Phil 2026-04-14 12:32:10 +03:00
  • 1c654f4e8e tests: add tb to axis_mac project Phil 2026-04-14 12:31:21 +03:00
  • c372dcd942 infra: add sim support to vivado.mk targets Phil 2026-04-14 12:30:30 +03:00
  • a3ed4919bc chore: add debug for base ethernet test Phil 2026-04-10 15:40:29 +03:00
  • d813855224 tests: add test project for ethernet echo & axis_mac tests Phil 2026-04-10 15:39:59 +03:00
  • 0480642167 chore: little refactor in eth stack Phil 2026-04-10 15:38:09 +03:00
  • c33afac783 rtl: implement axis UDP TX logic Phil 2026-04-10 15:37:19 +03:00
  • 26c627c988 rtl: add udp ram data count signal logic Phil 2026-04-10 15:35:26 +03:00
  • 879c4d49b2 infra: add vivado builds to gitignore Phil 2026-04-10 15:19:43 +03:00
  • 3544e3e2dc test: add sample top for axis loopback test Phil 2026-04-08 19:58:34 +03:00
  • 88db70ede8 Merge pull request 'rtl: generator added' (#1) from dev/generator into master ilianova.ds 2026-04-08 15:25:25 +03:00
  • ad6d6a4e2b Merge pull request 'rtl: sampler ready' (#2) from dev/sampler into master baulin.fa 2026-04-08 15:25:03 +03:00
  • 7a1c838de3 rtl: generator added dev/generator otroubi 2026-04-08 15:13:57 +03:00
  • 100feb0ea1 rtl: add constrains for axis eth fpga project Phil 2026-04-01 18:10:17 +03:00
  • 1310555b55 chore: remove old file Phil 2026-04-01 18:08:50 +03:00
  • c75443d170 test: udp axis rx Phil 2026-04-01 18:04:01 +03:00
  • 3a58119960 rtl: eth udp rx -> axis Phil 2026-04-01 18:03:47 +03:00