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dev/ethernet #4

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baulin.fa merged 21 commits from dev/ethernet into master 2026-04-14 15:42:09 +03:00
Conversation 0 Commits 21 Files Changed 42 +11224
baulin.fa commented 2026-04-14 15:41:52 +03:00
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работает на плате всё

работает на плате всё
baulin.fa added 21 commits 2026-04-14 15:41:52 +03:00
rtl: add sources for ethernet udp stack ded2afc0db
infra: add gitignore 0dd0006e47
tests: add sample project for minimal eth udp echo 7fedc36562
infra: add vivado.mk target for generic builds a1386fc8a4
rtl: add axis eth rx prototype 0b9fb64193
rtl: eth udp rx -> axis 3a58119960
test: udp axis rx c75443d170
chore: remove old file 1310555b55
rtl: add constrains for axis eth fpga project 100feb0ea1
test: add sample top for axis loopback test 3544e3e2dc
infra: add vivado builds to gitignore 879c4d49b2
rtl: add udp ram data count signal logic 26c627c988
rtl: implement axis UDP TX logic c33afac783
chore: little refactor in eth stack 0480642167
tests: add test project for ethernet echo & axis_mac tests d813855224
chore: add debug for base ethernet test a3ed4919bc
infra: add sim support to vivado.mk targets c372dcd942
tests: add tb to axis_mac project 1c654f4e8e
fix: signal in axis_mac 8907fea8a4
docs: add readme to ethernet-udp df6c204cbd
infra: update constraints to use unified ones for board and additional for debug nodes 7d1bfe25b4
baulin.fa merged commit 966d0379b7 into master 2026-04-14 15:42:09 +03:00
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Reference: baulin.fa/reflectometer_fpga_project#4
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