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chore: little refactor in eth stack

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Phil
2026-04-10 15:38:09 +03:00
parent c33afac783
commit 0480642167
2 changed files with 4 additions and 4 deletions
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6
rtl/ethernet-udp/src/eth/mac/mac_test.v
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@ -4,7 +4,7 @@
//Description :
//
//////////////////////////////////////////////////////////////////////////////////////
//`define TEST_SPEED
`define TEST_SPEED
`timescale 1 ns/1 ns
module mac_test
(
@ -74,7 +74,7 @@ parameter WAIT = 9'b010_000_000 ;
parameter CHECK_ARP = 9'b100_000_000 ;
reg [8:0] state ;
(* MARK_DEBUG="true" *) reg [8:0] state ;
reg [8:0] next_state ;
reg [15:0] ram_cnt ;
reg almost_full_d0 ;
@ -278,7 +278,7 @@ always@(posedge gmii_rx_clk or negedge rst_n)
udp_send_data_length <= udp_rec_data_length - 8 ;
else
`ifdef TEST_SPEED
udp_send_data_length <= 16'd1000 ;
udp_send_data_length <= 16'd100 ;
`else
udp_send_data_length <= 4*UDP_DEPTH ;
`endif

2
rtl/ethernet-udp/src/eth/util_gmii_to_rgmii.v
View File

@ -180,7 +180,7 @@ module util_gmii_to_rgmii (
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE(16), // Input delay tap setting (0-31)
.IDELAY_VALUE(16), // Input delay tap setting (0-31) May be changed for more stability
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal