rtl: add axis eth rx prototype
This commit is contained in:
Phil
@ -10,7 +10,7 @@ module mac_rx_top
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input rst_n,
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input rx_dv,
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input [7:0] mac_rx_datain,
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(* MARK_DEBUG="true" *)input [7:0] mac_rx_datain,
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input [31:0] local_ip_addr,
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input [47:0] local_mac_addr,
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@ -21,14 +21,14 @@ module mac_rx_top
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output [47:0] arp_rec_source_mac_addr,
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output [7:0] udp_rec_ram_rdata ,
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input [10:0] udp_rec_ram_read_addr,
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output [15:0] udp_rec_data_length,
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output udp_rec_data_valid,
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(* MARK_DEBUG="true" *)output [7:0] udp_rec_ram_rdata ,
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(* MARK_DEBUG="true" *)input [10:0] udp_rec_ram_read_addr,
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(* MARK_DEBUG="true" *)output [15:0] udp_rec_data_length,
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(* MARK_DEBUG="true" *)output udp_rec_data_valid,
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output [7:0] mac_rx_dataout,
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output [15:0] upper_layer_data_length ,
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output [15:0] ip_total_data_length,
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(* MARK_DEBUG="true" *)output [7:0] mac_rx_dataout,
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(* MARK_DEBUG="true" *)output [15:0] upper_layer_data_length ,
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(* MARK_DEBUG="true" *)output [15:0] ip_total_data_length,
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output icmp_rx_req,
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output icmp_rev_error,
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@ -24,13 +24,13 @@ module mac_tx_top
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input arp_request_req,
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input [7:0] ram_wr_data,
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input ram_wr_en,
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input udp_tx_req,
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output udp_ram_data_req,
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input [15:0] udp_send_data_length,
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output udp_tx_end,
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output almost_full,
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(* MARK_DEBUG="true" *)input [7:0] ram_wr_data,
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(* MARK_DEBUG="true" *)input ram_wr_en,
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(* MARK_DEBUG="true" *)input udp_tx_req,
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(* MARK_DEBUG="true" *)output udp_ram_data_req,
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(* MARK_DEBUG="true" *)input [15:0] udp_send_data_length,
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(* MARK_DEBUG="true" *)output udp_tx_end,
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(* MARK_DEBUG="true" *)output almost_full,
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output upper_data_req,
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input icmp_tx_ready,
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@ -40,9 +40,9 @@ module mac_tx_top
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output icmp_tx_ack,
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input [15:0] icmp_send_data_length,
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output mac_data_valid,
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output mac_send_end,
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output [7:0] mac_tx_data
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(* MARK_DEBUG="true" *)output mac_data_valid,
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(* MARK_DEBUG="true" *)output mac_send_end,
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(* MARK_DEBUG="true" *)output [7:0] mac_tx_data
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) ;
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47
rtl/ethernet-udp/tests/eth_axis/Makefile
Normal file
47
rtl/ethernet-udp/tests/eth_axis/Makefile
Normal file
@ -0,0 +1,47 @@
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# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# FPGA settings
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FPGA_PART = xc7a35tfgg484-1
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FPGA_TOP = ethernet_test_minimal
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FPGA_ARCH = artix7
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RTL_DIR = ../../src
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# Files for synthesis
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SYN_FILES = ethernet_test_minimal.v
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include ../../../../scripts/vivado.mk
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SYN_FILES += $(sort $(shell find ../../src -type f \( -name '*.v' -o -name '*.sv' \)))
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XCI_FILES = $(sort $(shell find ../../src -type f -name '*.xci'))
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program: $(PROJECT).bit
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echo "open_hw_manager" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
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echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
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echo "exit" >> generate_mcs.tcl
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vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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COUNT=$$((COUNT-1)); \
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for x in .mcs .prm; \
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do cp $*$$x rev/$*_rev$$COUNT$$x; \
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echo "Output: rev/$*_rev$$COUNT$$x"; done;
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229
rtl/ethernet-udp/tests/eth_minimal/axis_mac.sv
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229
rtl/ethernet-udp/tests/eth_minimal/axis_mac.sv
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@ -0,0 +1,229 @@
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`timescale 1 ns / 1 ns
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module axis_mac
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(
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input rst_n,
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input gmii_tx_clk,
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input gmii_rx_clk,
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input gmii_rx_dv,
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input [7:0] gmii_rxd,
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output reg gmii_tx_en,
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output reg [7:0] gmii_txd,
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// AXI-stream RX output (clock domain = gmii_rx_clk)
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(* MARK_DEBUG="true" *)output reg [7:0] m_axis_rx_tdata,
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(* MARK_DEBUG="true" *)output reg m_axis_rx_tvalid,
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input wire m_axis_rx_tready,
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(* MARK_DEBUG="true" *)output reg m_axis_rx_tlast
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);
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// ----------------------------------------------------------------
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// GMII RX input registering
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// ----------------------------------------------------------------
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reg gmii_rx_dv_d0;
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reg [7:0] gmii_rxd_d0;
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always @(posedge gmii_rx_clk or negedge rst_n) begin
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if (!rst_n) begin
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gmii_rx_dv_d0 <= 1'b0;
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gmii_rxd_d0 <= 8'd0;
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end else begin
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gmii_rx_dv_d0 <= gmii_rx_dv;
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gmii_rxd_d0 <= gmii_rxd;
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end
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end
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// ----------------------------------------------------------------
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// TX path from mac_top
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// ----------------------------------------------------------------
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wire gmii_tx_en_tmp;
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wire [7:0] gmii_txd_tmp;
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always @(posedge gmii_tx_clk or negedge rst_n) begin
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if (!rst_n) begin
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gmii_tx_en <= 1'b0;
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gmii_txd <= 8'd0;
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end else begin
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gmii_tx_en <= gmii_tx_en_tmp;
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gmii_txd <= gmii_txd_tmp;
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end
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end
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// ----------------------------------------------------------------
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// Unused user TX path into mac_top
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// We disable user UDP TX for now.
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// ARP replies and ICMP replies inside mac_top still work.
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// ----------------------------------------------------------------
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wire udp_ram_data_req;
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wire udp_tx_end;
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wire almost_full;
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wire mac_send_end;
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wire arp_found;
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wire mac_not_exist;
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wire [7:0] udp_rec_ram_rdata;
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reg [10:0] udp_rec_ram_read_addr;
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wire [15:0] udp_rec_data_length;
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wire udp_rec_data_valid;
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wire [7:0] tx_ram_wr_data = 8'd0;
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wire tx_ram_wr_en = 1'b0;
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wire [15:0] udp_send_data_length = 16'd0;
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wire udp_tx_req = 1'b0;
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wire arp_request_req = 1'b0;
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mac_top mac_top0 (
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.gmii_tx_clk (gmii_tx_clk),
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.gmii_rx_clk (gmii_rx_clk),
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.rst_n (rst_n),
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.source_mac_addr (48'h00_0a_35_01_fe_c0),
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.TTL (8'h80),
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.source_ip_addr (32'hc0a80002), // 192.168.0.2
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.destination_ip_addr (32'hc0a80003), // 192.168.0.3 (не используется для user TX пока)
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.udp_send_source_port (16'h1f90), // 8080
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.udp_send_destination_port (16'h1f90), // 8080
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.ram_wr_data (tx_ram_wr_data),
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.ram_wr_en (tx_ram_wr_en),
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.udp_ram_data_req (udp_ram_data_req),
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.udp_send_data_length (udp_send_data_length),
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.udp_tx_end (udp_tx_end),
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.almost_full (almost_full),
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.udp_tx_req (udp_tx_req),
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.arp_request_req (arp_request_req),
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.mac_send_end (mac_send_end),
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.mac_data_valid (gmii_tx_en_tmp),
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.mac_tx_data (gmii_txd_tmp),
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.rx_dv (gmii_rx_dv_d0),
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.mac_rx_datain (gmii_rxd_d0),
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.udp_rec_ram_rdata (udp_rec_ram_rdata),
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.udp_rec_ram_read_addr (udp_rec_ram_read_addr),
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.udp_rec_data_length (udp_rec_data_length),
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.udp_rec_data_valid (udp_rec_data_valid),
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.arp_found (arp_found),
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.mac_not_exist (mac_not_exist)
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);
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// ----------------------------------------------------------------
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// Detect "new packet ready" on udp_rec_data_valid rising edge
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// ----------------------------------------------------------------
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reg udp_rec_data_valid_d0;
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always @(posedge gmii_rx_clk or negedge rst_n) begin
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if (!rst_n)
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udp_rec_data_valid_d0 <= 1'b0;
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else
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udp_rec_data_valid_d0 <= udp_rec_data_valid;
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end
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wire udp_pkt_done = udp_rec_data_valid & ~udp_rec_data_valid_d0;
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// ----------------------------------------------------------------
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// RX RAM -> AXI-stream bridge
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//
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// Assumption:
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// udp_rec_data_length includes 8-byte UDP header,
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// so payload length = udp_rec_data_length - 8
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//
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// This implementation is simple and safe:
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// - start on udp_pkt_done
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// - read bytes 0 .. payload_len-1 from RX RAM
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// - output them on AXIS
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//
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// Because the BRAM read port is synchronous, this bridge may insert
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// bubbles between bytes. For first bring-up this is fine.
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// ----------------------------------------------------------------
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localparam RX_IDLE = 2'd0;
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localparam RX_ADDR = 2'd1;
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localparam RX_DATA = 2'd2;
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(* MARK_DEBUG="true" *) reg [1:0] rx_state;
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(* MARK_DEBUG="true" *) reg [15:0] rx_payload_len;
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(* MARK_DEBUG="true" *) reg [15:0] rx_index;
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always @(posedge gmii_rx_clk or negedge rst_n) begin
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if (!rst_n) begin
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rx_state <= RX_IDLE;
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rx_payload_len <= 16'd0;
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rx_index <= 16'd0;
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udp_rec_ram_read_addr <= 11'd0;
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m_axis_rx_tdata <= 8'd0;
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m_axis_rx_tvalid <= 1'b0;
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m_axis_rx_tlast <= 1'b0;
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end else begin
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case (rx_state)
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RX_IDLE: begin
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m_axis_rx_tvalid <= 1'b0;
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m_axis_rx_tlast <= 1'b0;
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rx_index <= 16'd0;
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udp_rec_ram_read_addr <= 11'd0;
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if (udp_pkt_done) begin
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// protect against pathological short values
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if (udp_rec_data_length > 16'd8) begin
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rx_payload_len <= udp_rec_data_length - 16'd8;
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udp_rec_ram_read_addr <= 11'd0; // issue read for byte 0
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rx_state <= RX_ADDR;
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end else begin
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rx_payload_len <= 16'd0;
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rx_state <= RX_IDLE;
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end
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end
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end
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// one cycle for synchronous BRAM read latency
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RX_ADDR: begin
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m_axis_rx_tvalid <= 1'b0;
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m_axis_rx_tlast <= 1'b0;
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rx_state <= RX_DATA;
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end
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RX_DATA: begin
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// hold valid until accepted
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if (m_axis_rx_tvalid && !m_axis_rx_tready) begin
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m_axis_rx_tvalid <= m_axis_rx_tvalid;
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m_axis_rx_tlast <= m_axis_rx_tlast;
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end else begin
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// present current byte from RAM
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m_axis_rx_tdata <= udp_rec_ram_rdata;
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m_axis_rx_tvalid <= 1'b1;
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m_axis_rx_tlast <= (rx_index == rx_payload_len - 1);
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if (rx_index == rx_payload_len - 1) begin
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// last byte accepted immediately if ready=1,
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// otherwise valid/last remain asserted until ready
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if (m_axis_rx_tready) begin
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m_axis_rx_tvalid <= 1'b0;
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m_axis_rx_tlast <= 1'b0;
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rx_state <= RX_IDLE;
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end
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end else begin
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if (m_axis_rx_tready) begin
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rx_index <= rx_index + 1'b1;
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udp_rec_ram_read_addr <= rx_index + 1'b1; // next byte
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rx_state <= RX_ADDR;
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m_axis_rx_tvalid <= 1'b0;
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m_axis_rx_tlast <= 1'b0;
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end
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end
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end
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end
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default: begin
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rx_state <= RX_IDLE;
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m_axis_rx_tvalid <= 1'b0;
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m_axis_rx_tlast <= 1'b0;
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end
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endcase
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end
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end
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endmodule
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