baulin.fa/reflectometer_fpga_project
2
0
Fork 0
Code Issues 4 Pull Requests Actions Packages Projects Releases Wiki Activity

rtl: update controller to support different smp_num for adc/dac sides

Browse Source
This commit is contained in:
Phil
2026-05-08 15:59:20 +03:00
parent 2a928c2407
commit ecb2ed3b7f
2 changed files with 25 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
rtl/controller/src/controller.sv
View File

@ -109,9 +109,11 @@ module control #(
// [63:32] pulse_period
// [79:64] pulse_num
// [95:80] pulse_height_raw[15:0]
// [127:96] pulse_period_ADC
//
// -------------------------------------------------------------------------
(* MARK_DEBUG="true" *) logic [95:0] cfg_bus_eth;
logic [95:0] cfg_shift_eth;
(* MARK_DEBUG="true" *) logic [127:0] cfg_bus_eth;
logic [127:0] cfg_shift_eth;
// ETH-domain parser and control
typedef enum logic [2:0] {
@ -278,10 +280,10 @@ module control #(
// little endian packing
cfg_shift_eth[cfg_byte_cnt*8 +: 8] <= s_axis_tdata;
if (cfg_byte_cnt == 4'd11) begin
if (cfg_byte_cnt == 4'd15) begin
// this must be the final payload byte
if (s_axis_tlast) begin
cfg_bus_eth <= {s_axis_tdata, cfg_shift_eth[87:0]};
cfg_bus_eth <= {s_axis_tdata, cfg_shift_eth[119:0]};
cfg_req_toggle_dac_eth <= ~cfg_req_toggle_dac_eth;
cfg_req_toggle_adc_eth <= ~cfg_req_toggle_adc_eth;
cfg_wait_dac_ack <= 1'b1;
@ -451,7 +453,7 @@ module control #(
cfg_req_sync_adc_d <= cfg_req_sync_adc;
if (cfg_req_pulse_adc) begin
adc_pulse_period <= cfg_bus_eth[63:32];
adc_pulse_period <= cfg_bus_eth[127:96];
adc_pulse_num <= cfg_bus_eth[79:64];
cfg_ack_toggle_adc <= ~cfg_ack_toggle_adc;

28
rtl/controller/tests/controller_tb.sv
View File

@ -139,9 +139,10 @@ module tb_control;
input logic [31:0] pulse_width,
input logic [31:0] pulse_period,
input logic [15:0] pulse_num,
input logic [15:0] pulse_height_raw
input logic [15:0] pulse_height_raw,
input logic [31:0] pulse_period_adc
);
logic [95:0] payload;
logic [127:0] payload;
int i;
begin
// little-endian payload layout:
@ -149,12 +150,14 @@ module tb_control;
// [63:32] pulse_period
// [79:64] pulse_num
// [95:80] pulse_height_raw
payload = {pulse_height_raw, pulse_num, pulse_period, pulse_width};
// [127:96] pulse_period_ADC
payload = {pulse_period_adc, pulse_height_raw, pulse_num, pulse_period, pulse_width};
axis_send_byte(8'h88, 1'b0); // CMD_SET_DATA
for (i = 0; i < 12; i++) begin
axis_send_byte(payload[i*8 +: 8], (i == 11));
for (i = 0; i < 16; i++) begin
axis_send_byte(payload[i*8 +: 8], (i == 15));
end
end
endtask
@ -219,6 +222,7 @@ module tb_control;
input logic [31:0] exp_pulse_period,
input logic [15:0] exp_pulse_num,
input logic [15:0] exp_pulse_height_raw,
input logic [31:0] exp_pulse_period_adc,
input int max_cycles = 200
);
logic [DAC_DATA_WIDTH-1:0] exp_dac_height;
@ -232,7 +236,7 @@ module tb_control;
(dac_pulse_period === exp_pulse_period) &&
(dac_pulse_num === exp_pulse_num ) &&
(dac_pulse_height === exp_dac_height ) &&
(adc_pulse_period === exp_pulse_period) &&
(adc_pulse_period === exp_pulse_period_adc) &&
(adc_pulse_num === exp_pulse_num )) begin
return;
end
@ -252,6 +256,7 @@ module tb_control;
logic [31:0] test_pulse_period;
logic [15:0] test_pulse_num;
logic [15:0] test_pulse_height_raw;
logic [31:0] test_pulse_period_adc;
initial begin
// defaults
@ -265,6 +270,7 @@ module tb_control;
test_pulse_period = 32'h55667788;
test_pulse_num = 16'hA1B2;
test_pulse_height_raw = 16'h0CDE; // for DAC_DATA_WIDTH=12 => 12'hCDE
test_pulse_period_adc = 32'h50607080;
repeat (10) @(posedge eth_clk_in);
rst_n = 1'b1;
@ -291,14 +297,16 @@ module tb_control;
test_pulse_width,
test_pulse_period,
test_pulse_num,
test_pulse_height_raw
test_pulse_height_raw,
test_pulse_period_adc
);
wait_cfg_applied(
test_pulse_width,
test_pulse_period,
test_pulse_num,
test_pulse_height_raw
test_pulse_height_raw,
test_pulse_period_adc
);
if (dac_pulse_width !== 32'h11223344) begin
@ -313,8 +321,8 @@ module tb_control;
if (dac_pulse_height !== 12'hCDE) begin
$fatal(1, "dac_pulse_height mismatch: got %h expected %h", dac_pulse_height, 12'hCDE);
end
if (adc_pulse_period !== 32'h55667788) begin
$fatal(1, "adc_pulse_period mismatch: got %h expected %h", adc_pulse_period, 32'h55667788);
if (adc_pulse_period !== 32'h50607080) begin
$fatal(1, "adc_pulse_period mismatch: got %h expected %h", adc_pulse_period, 32'h50607080);
end
if (adc_pulse_num !== 16'hA1B2) begin
$fatal(1, "adc_pulse_num mismatch: got %h expected %h", adc_pulse_num, 16'hA1B2);