fix: generator wrt signal incorrect clocking

This commit is contained in:
Phil
2026-04-17 14:42:20 +03:00
parent f863d09fb8
commit b9c75b823f

View File

@ -92,8 +92,12 @@ module generator
end
end
end
OBUF OBUF_pulse_clk (
.I(clk_in),
.O(pulse)
);
assign pulse_height_out = pulse_height_out_reg;
assign pulse = pulse_reg;
endmodule