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chore: update eth_test_minimal to a100

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This commit is contained in:
Phil
2026-05-08 18:43:26 +03:00
parent 7f6a3e03a1
commit 429cf3d085
3 changed files with 64 additions and 118 deletions
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2
rtl/ethernet-udp/src/eth/mac/mac_test.v
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@ -4,7 +4,7 @@
//Description :
//
//////////////////////////////////////////////////////////////////////////////////////
`define TEST_SPEED
//`define TEST_SPEED
`timescale 1 ns/1 ns
module mac_test
(

4
rtl/ethernet-udp/tests/eth_minimal/Makefile
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@ -7,7 +7,7 @@
#
# FPGA settings
FPGA_PART = xc7a35tfgg484-1
FPGA_PART = xc7a100tfgg484-2
FPGA_TOP = ethernet_test_minimal
FPGA_ARCH = artix7
@ -23,7 +23,7 @@ SYN_FILES += $(sort $(shell find ../../src -type f \( -name '*.v' -o -name '*.sv
XCI_FILES = $(sort $(shell find ../../src -type f -name '*.xci'))
XDC_FILES += debug.xdc
XDC_FILES += ../../../../constraints/ax7a035b.xdc
XDC_FILES += ../../../../constraints/ax7102.xdc
program: $(PROJECT).bit
echo "open_hw_manager" > program.tcl

176
rtl/ethernet-udp/tests/eth_minimal/ethernet_test_minimal.v
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@ -1,134 +1,80 @@
module ethernet_test_minimal
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: ethernet_test
//////////////////////////////////////////////////////////////////////////////////
module ethernet_test
(
input sys_clk_p, //system clock positive
input sys_clk_n, //system clock negative
input rst_n, //reset ,low active
output [3:0] led, //display network rate status
output e_reset, //phy reset
output e_mdc, //phy emdio clock
inout e_mdio, //phy emdio data
output[3:0] rgmii_txd, //phy data send
output rgmii_txctl, //phy data send control
output rgmii_txc, //Clock for sending data
input[3:0] rgmii_rxd, //recieve data
input rgmii_rxctl, //Control signal for receiving data
input rgmii_rxc //Clock for recieving data
input sys_clk_p, //system clock positive
input sys_clk_n, //system clock negative
input rst_n, //reset ,low active
output [3:0] led, //display network rate status
output e_reset, //phy reset
output e_mdc, //phy emdio clock
inout e_mdio, //phy emdio data
input e_rxc, //125Mhz ethernet gmii rx clock
input e_rxdv, //GMII recieving data valid
input e_rxer, //GMII recieving data error
input [7:0] e_rxd, //GMII recieving data
input e_txc, //25Mhz ethernet mii tx clock
output e_gtxc, //125Mhz ethernet gmii tx clock
output e_txen, //GMII sending data valid
output e_txer, //GMII sending data error
output[7:0] e_txd //GMII sending data
);
wire [ 7:0] gmii_txd; //gmii data
wire gmii_tx_en; //gmii send enable
wire gmii_tx_er;
wire gmii_tx_clk; //gmii send clock
wire gmii_crs;
wire gmii_col;
wire [ 7:0] gmii_rxd; //gmii recieving data
wire gmii_rx_dv; //gmii recieving data valid
wire gmii_rx_er;
wire gmii_rx_clk; //gmii recieve clock
wire [ 1:0] speed_selection; // 1x gigabit, 01 100Mbps, 00 10mbps
wire duplex_mode; // 1 full, 0 half
wire rgmii_rxcpll;
wire [31:0] pack_total_len ; //package length
wire [1:0] speed ; //net speed select
wire link ; //link status
wire e_rx_dv ;
wire [7:0] e_rxd ;
wire e_tx_en ;
wire [7:0] e_txd ;
wire e_rst_n ;
wire sys_clk ;
assign duplex_mode = 1'b1;
wire sys_clk; //single end clock
wire [31:0] pack_total_len ; //package length
wire [1:0] speed ; //net speed select
wire link ; //link status
wire erxdv ;
wire [7:0] erxd ;
wire e_tx_en ;
wire [7:0] etxd ;
wire e_rst_n ;
assign e_gtxc =e_rxc;
assign e_reset = 1'b1;
/*************************************************************************
generate single end clock
**************************************************************************/
IBUFDS sys_clk_ibufgds
(
.O (sys_clk ),
.I (sys_clk_p ),
.IB (sys_clk_n )
);
(* IODELAY_GROUP = "rgmii_idelay_group" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYCTRL IDELAYCTRL_inst (
.RDY(), // 1-bit output: Ready output
.REFCLK(sys_clk), // 1-bit input: Reference clock input
.RST(1'b0) // 1-bit input: Active high reset input
.O (sys_clk ),
.I (sys_clk_p ),
.IB (sys_clk_n )
);
/*************************************************************************
GMII and RGMII data conversion
****************************************************************************/
util_gmii_to_rgmii util_gmii_to_rgmii_m0
(
.reset (1'b0 ),
.rgmii_td (rgmii_txd ),
.rgmii_tx_ctl (rgmii_txctl ),
.rgmii_txc (rgmii_txc ),
.rgmii_rd (rgmii_rxd ),
.rgmii_rx_ctl (rgmii_rxctl ),
.gmii_rx_clk (gmii_rx_clk ),
.gmii_txd (e_txd ),
.gmii_tx_en (e_tx_en ),
.gmii_tx_er (1'b0 ),
.gmii_tx_clk (gmii_tx_clk ),
.gmii_crs (gmii_crs ),
.gmii_col (gmii_col ),
.gmii_rxd (gmii_rxd ),
.rgmii_rxc (rgmii_rxc ),//add
.gmii_rx_dv (gmii_rx_dv ),
.gmii_rx_er (gmii_rx_er ),
.speed_selection (2'b10 ),
.duplex_mode (duplex_mode )
);
/*************************************************************************
Different conversion of GMII data according to different network speeds
****************************************************************************/
gmii_arbi arbi_inst
(
.clk (gmii_tx_clk ),
.rst_n (rst_n ),
.speed (2'b10 ),
.link (1'b1 ),
.pack_total_len (pack_total_len ),
.e_rst_n (e_rst_n ),
.gmii_rx_dv (gmii_rx_dv ),
.gmii_rxd (gmii_rxd ),
.gmii_tx_en (gmii_tx_en ),
.gmii_txd (gmii_txd ),
.e_rx_dv (e_rx_dv ),
.e_rxd (e_rxd ),
.e_tx_en (e_tx_en ),
.e_txd (e_txd )
);
/*************************************************************************
Mac layer protocol test
****************************************************************************/
mac_test mac_test0
(
.gmii_tx_clk (gmii_tx_clk ),
.gmii_rx_clk (gmii_rx_clk ) ,
.rst_n (e_rst_n ),
.pack_total_len (pack_total_len ),
.gmii_rx_dv (e_rx_dv ),
.gmii_rxd (e_rxd ),
.gmii_tx_en (gmii_tx_en ),
.gmii_txd (gmii_txd )
.gmii_tx_clk (e_gtxc ),
.gmii_rx_clk (e_rxc ) ,
.rst_n (e_rst_n ),
.pack_total_len (pack_total_len ),
.gmii_rx_dv (erxdv ),
.gmii_rxd (erxd ),
.gmii_tx_en (e_tx_en ),
.gmii_txd (etxd )
);
/*************************************************************************
Generate PHY reset signal
Different conversion of GMII data according to different network speeds
****************************************************************************/
reset reset_m0
gmii_arbi arbi_inst
(
.clk (sys_clk ),
.key1 (rst_n ),
.rst_n (e_reset )
.clk (e_gtxc ),
.rst_n (rst_n ),
.speed (2'b10 ),
.link (1'b1 ),
.pack_total_len (pack_total_len ),
.e_rst_n (e_rst_n ),
.gmii_rx_dv (e_rxdv ),
.gmii_rxd (e_rxd ),
.gmii_tx_en (e_tx_en ),
.gmii_txd (etxd ),
.e_rx_dv (erxdv ),
.e_rxd (erxd ),
.e_tx_en (e_txen ),
.e_txd (e_txd )
);
endmodule