DMA control module
This commit is contained in:
otroubi
@ -1,72 +1,117 @@
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module dma_controller
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#(
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parameter AXI_ADDR_WIDTH = 16,
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parameter LEN_WIDTH = 20,
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parameter TAG_WIDTH = 8,
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parameter AXIS_ID_WIDTH = 8,
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parameter AXIS_DEST_WIDTH = 8,
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parameter AXIS_USER_WIDTH = 1
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parameter int unsigned READ_DESC_WIDTH = 128,
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parameter int unsigned WRITE_DESC_WIDTH = 128,
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parameter int unsigned READ_STATUS_WIDTH = 128,
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parameter int unsigned WRITE_STATUS_WIDTH = 128
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)
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(
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input dma_clk,
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input rst,
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input send,
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input [127:0] desc_read,
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input [127:0] desc_write,
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input [127:0] status_read,
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input [127:0] status_write,
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//descriptor read
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output wire [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_addr,
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output wire [LEN_WIDTH-1:0] s_axis_read_desc_len,
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output wire [TAG_WIDTH-1:0] s_axis_read_desc_tag,
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output wire [AXIS_ID_WIDTH-1:0] s_axis_read_desc_id,
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output wire [AXIS_DEST_WIDTH-1:0] s_axis_read_desc_dest,
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output wire [AXIS_USER_WIDTH-1:0] s_axis_read_desc_user,
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output wire s_axis_read_desc_valid,
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input wire s_axis_read_desc_ready,
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input rst_n,
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input logic send_desc_read,
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input logic send_desc_write,
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input logic take_status_read,
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input logic take_status_write,
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// descriptor write
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output wire [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_addr,
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output wire [LEN_WIDTH-1:0] s_axis_write_desc_len,
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output wire [TAG_WIDTH-1:0] s_axis_write_desc_tag,
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output wire s_axis_write_desc_valid,
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input wire s_axis_write_desc_ready,
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input logic ready_desc_read,
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input logic ready_desc_write,
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// status read
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input wire [TAG_WIDTH-1:0] m_axis_read_desc_status_tag,
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input wire [3:0] m_axis_read_desc_status_error,
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input wire m_axis_read_desc_status_valid,
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output logic ready_status_read,
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output logic ready_status_write,
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input logic [READ_DESC_WIDTH-1:0] desc_read_cmd,
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input logic [WRITE_DESC_WIDTH-1:0] desc_write_cmd,
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output logic [READ_STATUS_WIDTH-1:0] status_read_cmd,
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output logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd,
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input logic [READ_STATUS_WIDTH-1:0] status_read_cmd_in,
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input logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd_in,
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output logic desc_read_dma_busy,
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output logic desc_write_dma_busy,
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output logic status_read_dma_busy,
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output logic status_write_dma_busy,
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output logic desc_read_dma_hs,
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output logic desc_write_dma_hs,
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output logic status_read_dma_hs,
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output logic status_write_dma_hs,
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output logic valid_desc_read,
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output logic valid_desc_write,
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input logic valid_status_read,
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input logic valid_status_write,
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output logic [READ_DESC_WIDTH-1:0] desc_read_cmd_out,
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output logic [WRITE_DESC_WIDTH-1:0] desc_write_cmd_out
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// status write
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input wire [LEN_WIDTH-1:0] m_axis_write_desc_status_len,
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input wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag,
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input wire [AXIS_ID_WIDTH-1:0] m_axis_write_desc_status_id,
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input wire [AXIS_DEST_WIDTH-1:0] m_axis_write_desc_status_dest,
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input wire [AXIS_USER_WIDTH-1:0] m_axis_write_desc_status_user,
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input wire [3:0] m_axis_write_desc_status_error,
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input wire m_axis_write_desc_status_valid
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);
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typedef enum logic [0:0] {
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IDLE,
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WAIT_READY
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} wr_state;
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shaper_axis_desc
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#(
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.DATA_WIDTH(READ_DESC_WIDTH)
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) shaper_axis_desc_read
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(
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.clk(dma_clk),
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.rst_n(rst_n),
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.data_in(desc_read_cmd),
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.send(send_desc_read),
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.ready(ready_desc_read),
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.busy(desc_read_dma_busy),
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.handshake(desc_read_dma_hs),
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.data_out(desc_read_cmd_out),
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.valid(valid_desc_read)
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);
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wr_state state;
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shaper_axis_desc
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#(
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.DATA_WIDTH(WRITE_DESC_WIDTH)
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) shaper_axis_desc_write
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(
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.clk(dma_clk),
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.rst_n(rst_n),
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.data_in(desc_write_cmd),
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.send(send_desc_write),
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.ready(ready_desc_write),
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.busy(desc_write_dma_busy),
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.handshake(desc_write_dma_hs),
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.data_out(desc_write_cmd_out),
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.valid(valid_desc_write)
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);
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always @(posedge clk) begin
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if (rst) begin
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shaper_axis_status
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#(
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.DATA_WIDTH(READ_STATUS_WIDTH)
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) shaper_axis_status_read
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(
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.clk(dma_clk),
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.rst_n(rst_n),
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.data_in(status_read_cmd_in),
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.take(take_status_read),
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.valid(valid_status_read),
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.ready(ready_status_read),
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.busy(status_read_dma_busy),
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.handshake(status_read_dma_hs),
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.data_out(status_read_cmd)
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);
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end else begin
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case (state)
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IDLE: begin
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if (send) begin
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end
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WAIT_READY: begin
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end
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endcase
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end
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shaper_axis_status
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#(
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.DATA_WIDTH(READ_STATUS_WIDTH)
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) shaper_axis_status_write
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(
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.clk(dma_clk),
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.rst_n(rst_n),
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.data_in(status_write_cmd_in),
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.take(take_status_write),
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.valid(valid_status_write),
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.ready(ready_status_write),
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.busy(status_write_dma_busy),
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.handshake(status_write_dma_hs),
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.data_out(status_write_cmd)
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);
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endmodule
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54
rtl/controller/src/shaper_axis_desc.sv
Normal file
54
rtl/controller/src/shaper_axis_desc.sv
Normal file
@ -0,0 +1,54 @@
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module shaper_axis_desc #(
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parameters DATA_WIDTH = 128;
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) (
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input clk;
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input rst_n;
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input logic [DATA_WIDTH-1:0] data_in;
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input logic send;
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input logic ready;
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output logic busy;
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output logic handshake;
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output logic [DATA_WIDTH-1:0] data_out;
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output logic valid;
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);
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typedef enum logic [0:0] {
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IDLE,
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WAIT_READY
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} wr_state;
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wr_state state;
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always @(posedge clk) begin
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if (!rst_n) begin
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state <= IDLE;
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busy <= 1'b0;
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handshake <= 1'b0;
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data_out <= 1'b0;
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valid <= 1'b0;
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end else begin
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case (state)
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IDLE: begin
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handshake <= 1'b0;
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if (send) begin
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valid <= 1'b1;
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data_out <= data_in;
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busy <= 1'b1;
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state <= WAIT_READY;
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end
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end
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WAIT_READY: begin
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if (ready) begin
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valid <= 1'b0;
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handshake <= 1'b1;
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busy <= 1'b0;
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state <= IDLE;
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end
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end
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default: state <= IDLE;
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endcase
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end
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end
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endmodule
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55
rtl/controller/src/shaper_axis_status.sv
Normal file
55
rtl/controller/src/shaper_axis_status.sv
Normal file
@ -0,0 +1,55 @@
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module shaper_axis_status #(
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parameter int unsigned DATA_WIDTH = 128
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)(
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input logic clk,
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input logic rst_n,
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input logic [DATA_WIDTH-1:0] data_in,
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input logic take,
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input logic valid,
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output logic ready,
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output logic busy,
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output logic handshake,
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output logic [DATA_WIDTH-1:0] data_out
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);
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typedef enum logic [0:0] {
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IDLE,
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WAIT_VALID
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} wr_state;
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wr_state state;
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always @(posedge clk) begin
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if (!rst_n) begin
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state <= IDLE;
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ready <= 1'b0;
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busy <= 1'b0;
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handshake <= 1'b0;
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data_out <= '0;
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end else begin
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case (state)
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IDLE: begin
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handshake <= 1'b0;
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if (take) begin
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ready <= 1'b1;
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busy <= 1'b1;
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state <= WAIT_VALID;
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end
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end
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WAIT_VALID: begin
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if (valid) begin
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data_out <= data_in;
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ready <= 1'b0;
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handshake <= 1'b1;
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busy <= 1'b0;
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state <= IDLE;
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end
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end
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endcase
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end
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end
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endmodule
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