baulin.fa/reflectometer_fpga_project
2
0
Fork 0
Code Issues 4 Pull Requests Actions Packages Projects Releases Wiki Activity
52 Commits 12 Branches 0 Tags
8e46f965df9362e40325e9339402579357d83c0b
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Phil 8e46f965df fix: incorrect fifo threshold value
2026-04-17 21:58:20 +03:00
constraints
fix: constraint re-pin DAC to J11 header
2026-04-17 14:43:31 +03:00
designs
rtl: add project with eth and generator
2026-04-17 14:53:14 +03:00
docs
infra: init project structure
2026-03-25 16:17:55 +03:00
rtl
fix: incorrect fifo threshold value
2026-04-17 21:58:20 +03:00
scripts
fix: broken (stuck) sim
2026-04-15 18:53:49 +03:00
software
sw: update console, now can send actual data
2026-04-17 14:44:27 +03:00
.gitignore
chore: exclude bitstreams from git
2026-04-17 14:50:23 +03:00
README.md
chore: update readme
2026-03-25 15:57:00 +03:00

README.md

reflectometer_fpga_project

Проект по разработке аппаратной вычислительной части для отпического рефлектометра для обнаружения утечек.

Description
No description provided
Readme 917 KiB
Languages
Verilog 36%
Tcl 30.5%
SystemVerilog 24.6%
Python 5.1%
Makefile 3.8%