baulin.fa/reflectometer_fpga_project
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Phil a8a3aff498 rtl: first impl of adder+accum
2026-04-22 16:38:22 +03:00
constraints
fix: constraint re-pin DAC to J11 header
2026-04-17 14:43:31 +03:00
designs
rtl: add project with eth and generator
2026-04-17 14:53:14 +03:00
docs
infra: init project structure
2026-03-25 16:17:55 +03:00
rtl
rtl: first impl of adder+accum
2026-04-22 16:38:22 +03:00
scripts
infra: make default sim longer
2026-04-21 19:46:51 +03:00
software
sw: update console, now can send actual data
2026-04-17 14:44:27 +03:00
.gitignore
chore: exclude bitstreams from git
2026-04-17 14:50:23 +03:00
README.md
chore: update readme
2026-03-25 15:57:00 +03:00

README.md

reflectometer_fpga_project

Проект по разработке аппаратной вычислительной части для отпического рефлектометра для обнаружения утечек.

Description
No description provided
Readme 340 KiB
Languages
Verilog 40.3%
Tcl 29.4%
SystemVerilog 25.8%
Makefile 3.7%
Python 0.8%