|
|
7f9ad95e68
|
tests: add simple tb for accum output fifo
|
2026-04-17 21:51:00 +03:00 |
|
|
|
4786d2d7f6
|
rtl: wip accum output module, currently only with write part
|
2026-04-17 21:50:30 +03:00 |
|
|
|
b9c75b823f
|
fix: generator wrt signal incorrect clocking
|
2026-04-17 14:42:20 +03:00 |
|
|
|
f863d09fb8
|
Merge pull request 'dev/controller' (#5) from dev/controller into master
Reviewed-on: #5
|
2026-04-15 18:58:23 +03:00 |
|
|
|
597be48407
|
docs: fix typos
|
2026-04-15 18:56:46 +03:00 |
|
|
|
f98051bc53
|
docs: add controller READMEs
|
2026-04-15 18:54:07 +03:00 |
|
|
|
c41b08f539
|
fix: tricky packet check in ctrl
|
2026-04-15 17:56:22 +03:00 |
|
|
|
dcf93fb307
|
infra: add build Makefile for controller test project
|
2026-04-15 13:31:28 +03:00 |
|
|
|
23f82b9445
|
tests: add controller tb
|
2026-04-15 13:30:56 +03:00 |
|
|
|
003750d972
|
rtl: add controller first version
|
2026-04-15 12:47:10 +03:00 |
|
|
|
966d0379b7
|
Merge pull request 'dev/ethernet' (#4) from dev/ethernet into master
Reviewed-on: #4
|
2026-04-14 15:42:08 +03:00 |
|
|
|
7d1bfe25b4
|
infra: update constraints to use unified ones for board and additional for debug nodes
|
2026-04-14 15:39:21 +03:00 |
|
|
|
df6c204cbd
|
docs: add readme to ethernet-udp
|
2026-04-14 12:36:05 +03:00 |
|
|
|
8907fea8a4
|
fix: signal in axis_mac
|
2026-04-14 12:32:10 +03:00 |
|
|
|
1c654f4e8e
|
tests: add tb to axis_mac project
|
2026-04-14 12:31:21 +03:00 |
|
|
|
a3ed4919bc
|
chore: add debug for base ethernet test
|
2026-04-10 15:40:29 +03:00 |
|
|
|
d813855224
|
tests: add test project for ethernet echo & axis_mac tests
|
2026-04-10 15:39:59 +03:00 |
|
|
|
0480642167
|
chore: little refactor in eth stack
|
2026-04-10 15:38:09 +03:00 |
|
|
|
c33afac783
|
rtl: implement axis UDP TX logic
|
2026-04-10 15:37:19 +03:00 |
|
|
|
26c627c988
|
rtl: add udp ram data count signal logic
|
2026-04-10 15:35:26 +03:00 |
|
|
|
3544e3e2dc
|
test: add sample top for axis loopback test
|
2026-04-08 19:58:34 +03:00 |
|
|
|
88db70ede8
|
Merge pull request 'rtl: generator added' (#1) from dev/generator into master
Reviewed-on: #1
|
2026-04-08 15:25:25 +03:00 |
|
|
|
7a1c838de3
|
rtl: generator added
|
2026-04-08 15:13:57 +03:00 |
|
|
|
100feb0ea1
|
rtl: add constrains for axis eth fpga project
|
2026-04-01 18:10:17 +03:00 |
|
|
|
1310555b55
|
chore: remove old file
|
2026-04-01 18:08:50 +03:00 |
|
|
|
c75443d170
|
test: udp axis rx
|
2026-04-01 18:04:01 +03:00 |
|
|
|
3a58119960
|
rtl: eth udp rx -> axis
|
2026-04-01 18:03:47 +03:00 |
|
|
|
221cb055f1
|
rtl: sampler ready
|
2026-04-01 11:46:59 +03:00 |
|
|
|
0b9fb64193
|
rtl: add axis eth rx prototype
|
2026-04-01 11:44:46 +03:00 |
|
|
|
7fedc36562
|
tests: add sample project for minimal eth udp echo
|
2026-03-31 15:08:12 +03:00 |
|
|
|
ded2afc0db
|
rtl: add sources for ethernet udp stack
|
2026-03-31 12:53:16 +03:00 |
|
|
|
aa1d45fe15
|
infra: init project structure
|
2026-03-25 16:17:55 +03:00 |
|
