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b54e69dec0
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chore: add clocks for accum_fifo impl test
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2026-04-21 19:48:20 +03:00 |
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7be26d9d1a
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chore: update tb files
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2026-04-21 19:47:56 +03:00 |
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3dcaaf8ea5
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fix: better sync for accum fifo
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2026-04-21 19:47:46 +03:00 |
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dfccc01225
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tests: auto tb for out_axis_fifo
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2026-04-21 19:47:27 +03:00 |
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4eb937e13f
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infra: make default sim longer
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2026-04-21 19:46:51 +03:00 |
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21785aaac7
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rtl: send part of out_axis_fifo
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2026-04-21 17:26:02 +03:00 |
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8e46f965df
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fix: incorrect fifo threshold value
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2026-04-17 21:58:20 +03:00 |
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7f9ad95e68
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tests: add simple tb for accum output fifo
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2026-04-17 21:51:00 +03:00 |
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4786d2d7f6
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rtl: wip accum output module, currently only with write part
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2026-04-17 21:50:30 +03:00 |
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58500b7549
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Merge pull request 'dev/debug' (#6) from dev/debug into master
Reviewed-on: #6
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2026-04-17 15:30:07 +03:00 |
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8b1e209da6
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rtl: add project with eth and generator
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2026-04-17 14:53:14 +03:00 |
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924f94986c
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chore: exclude bitstreams from git
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2026-04-17 14:50:23 +03:00 |
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83c714cd6f
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sw: update console, now can send actual data
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2026-04-17 14:44:27 +03:00 |
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f54883a9e7
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fix: constraint re-pin DAC to J11 header
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2026-04-17 14:43:31 +03:00 |
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b9c75b823f
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fix: generator wrt signal incorrect clocking
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2026-04-17 14:42:20 +03:00 |
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f863d09fb8
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Merge pull request 'dev/controller' (#5) from dev/controller into master
Reviewed-on: #5
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2026-04-15 18:58:23 +03:00 |
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597be48407
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docs: fix typos
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2026-04-15 18:56:46 +03:00 |
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f98051bc53
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docs: add controller READMEs
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2026-04-15 18:54:07 +03:00 |
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eea031c6c1
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fix: broken (stuck) sim
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2026-04-15 18:53:49 +03:00 |
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500b10b327
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sw: add console script prototype
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2026-04-15 18:28:03 +03:00 |
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851851828e
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fix: add missing constrain to Makefile
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2026-04-15 18:23:52 +03:00 |
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35e9feb87b
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tests: add sample project for eth+ctrl
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2026-04-15 17:57:16 +03:00 |
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c41b08f539
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fix: tricky packet check in ctrl
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2026-04-15 17:56:22 +03:00 |
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ea7af4ed62
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infra: init designs folder
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2026-04-15 13:40:19 +03:00 |
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6bb4f1efd8
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infra: sim_top auto pick if exists in sim fileset
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2026-04-15 13:31:47 +03:00 |
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dcf93fb307
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infra: add build Makefile for controller test project
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2026-04-15 13:31:28 +03:00 |
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23f82b9445
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tests: add controller tb
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2026-04-15 13:30:56 +03:00 |
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bdb75fa298
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infra: exclude temp scripts from git
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2026-04-15 13:19:08 +03:00 |
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003750d972
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rtl: add controller first version
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2026-04-15 12:47:10 +03:00 |
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966d0379b7
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Merge pull request 'dev/ethernet' (#4) from dev/ethernet into master
Reviewed-on: #4
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2026-04-14 15:42:08 +03:00 |
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7d1bfe25b4
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infra: update constraints to use unified ones for board and additional for debug nodes
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2026-04-14 15:39:21 +03:00 |
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df6c204cbd
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docs: add readme to ethernet-udp
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2026-04-14 12:36:05 +03:00 |
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8907fea8a4
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fix: signal in axis_mac
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2026-04-14 12:32:10 +03:00 |
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1c654f4e8e
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tests: add tb to axis_mac project
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2026-04-14 12:31:21 +03:00 |
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c372dcd942
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infra: add sim support to vivado.mk targets
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2026-04-14 12:30:30 +03:00 |
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a3ed4919bc
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chore: add debug for base ethernet test
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2026-04-10 15:40:29 +03:00 |
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d813855224
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tests: add test project for ethernet echo & axis_mac tests
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2026-04-10 15:39:59 +03:00 |
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0480642167
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chore: little refactor in eth stack
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2026-04-10 15:38:09 +03:00 |
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c33afac783
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rtl: implement axis UDP TX logic
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2026-04-10 15:37:19 +03:00 |
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26c627c988
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rtl: add udp ram data count signal logic
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2026-04-10 15:35:26 +03:00 |
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879c4d49b2
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infra: add vivado builds to gitignore
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2026-04-10 15:19:43 +03:00 |
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3544e3e2dc
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test: add sample top for axis loopback test
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2026-04-08 19:58:34 +03:00 |
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88db70ede8
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Merge pull request 'rtl: generator added' (#1) from dev/generator into master
Reviewed-on: #1
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2026-04-08 15:25:25 +03:00 |
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ad6d6a4e2b
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Merge pull request 'rtl: sampler ready' (#2) from dev/sampler into master
Reviewed-on: #2
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2026-04-08 15:25:03 +03:00 |
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7a1c838de3
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rtl: generator added
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2026-04-08 15:13:57 +03:00 |
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100feb0ea1
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rtl: add constrains for axis eth fpga project
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2026-04-01 18:10:17 +03:00 |
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1310555b55
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chore: remove old file
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2026-04-01 18:08:50 +03:00 |
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c75443d170
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test: udp axis rx
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2026-04-01 18:04:01 +03:00 |
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3a58119960
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rtl: eth udp rx -> axis
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2026-04-01 18:03:47 +03:00 |
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221cb055f1
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rtl: sampler ready
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2026-04-01 11:46:59 +03:00 |
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