chore: add clocks for accum_fifo impl test

Reviewed-on: #6

.gitignore

@@ -23,3 +23,7 @@ create_project.tcl
 gen_ip.tcl
 defines.v
 run_sim.tcl
+*.bit
+*.xsa
+*.ltx
+*.bin

constraints/ax7a035b.xdc

@@ -58,67 +58,40 @@ set_property SLEW FAST [get_ports rgmii_txctl]
 set_property SLEW FAST [get_ports {rgmii_txd[*]}]
 create_clock -period 8.000 [get_ports rgmii_rxc]
 
-# === ADC an9238 (J11 header) ===
+# === DAC (J11 header) ===
-set_property PACKAGE_PIN G21 [get_ports ch2_clk]
-set_property PACKAGE_PIN G22 [get_ports ch2_data[0]]
-set_property PACKAGE_PIN C22 [get_ports ch2_data[1]]
-set_property PACKAGE_PIN B22 [get_ports ch2_data[2]]
-set_property PACKAGE_PIN F19 [get_ports ch2_data[3]]
-set_property PACKAGE_PIN F20 [get_ports ch2_data[4]]
-set_property PACKAGE_PIN D20 [get_ports ch2_data[5]]
-set_property PACKAGE_PIN C20 [get_ports ch2_data[6]]
-set_property PACKAGE_PIN A18 [get_ports ch2_data[7]]
-set_property PACKAGE_PIN A19 [get_ports ch2_data[8]]
-set_property PACKAGE_PIN B20 [get_ports ch2_data[9]]
-set_property PACKAGE_PIN A20 [get_ports ch2_data[10]]
-set_property PACKAGE_PIN F18 [get_ports ch2_data[11]]
-set_property PACKAGE_PIN E18 [get_ports ch2_otr]
-set_property PACKAGE_PIN C18 [get_ports ch1_data[1]]
-set_property PACKAGE_PIN C19 [get_ports ch1_data[0]]
-set_property PACKAGE_PIN B17 [get_ports ch1_data[3]]
-set_property PACKAGE_PIN B18 [get_ports ch1_data[2]]
-set_property PACKAGE_PIN D17 [get_ports ch1_data[5]]
-set_property PACKAGE_PIN C17 [get_ports ch1_data[4]]
-set_property PACKAGE_PIN A15 [get_ports ch1_data[7]]
-set_property PACKAGE_PIN A16 [get_ports ch1_data[6]]
-set_property PACKAGE_PIN B15 [get_ports ch1_data[9]]
-set_property PACKAGE_PIN B16 [get_ports ch1_data[8]]
-set_property PACKAGE_PIN A13 [get_ports ch1_data[11]]
-set_property PACKAGE_PIN A14 [get_ports ch1_data[10]]
-set_property PACKAGE_PIN E16 [get_ports ch1_clk]
-set_property PACKAGE_PIN D16 [get_ports ch1_otr]
-
-set_property IOSTANDARD LVCMOS33 [get_ports ch2_clk]
-set_property IOSTANDARD LVCMOS33 [get_ports {ch2_data[*]}]
-set_property IOSTANDARD LVCMOS33 [get_ports ch2_otr]
-set_property IOSTANDARD LVCMOS33 [get_ports {ch1_data[*]}]
-set_property IOSTANDARD LVCMOS33 [get_ports ch1_clk]
-set_property IOSTANDARD LVCMOS33 [get_ports ch1_otr]
-
-set_property SLEW FAST [get_ports {ch2_clk ch1_clk}]
-
-# === DAC an9767 (J13 header) ===
-set_property PACKAGE_PIN AA9 [get_ports p2_clk]
-set_property PACKAGE_PIN AB10 [get_ports p2_wrt]
-set_property PACKAGE_PIN U16 [get_ports p2_data[13]]
-set_property PACKAGE_PIN T16 [get_ports p2_data[12]]
-set_property PACKAGE_PIN AA13 [get_ports p2_data[11]]
-set_property PACKAGE_PIN AB13 [get_ports p2_data[10]]
-set_property PACKAGE_PIN AB11 [get_ports p2_data[9]]
-set_property PACKAGE_PIN AB12 [get_ports p2_data[8]]
-set_property PACKAGE_PIN Y13 [get_ports p2_data[7]]
-set_property PACKAGE_PIN AA14 [get_ports p2_data[6]]
-set_property PACKAGE_PIN W14 [get_ports p2_data[5]]
-set_property PACKAGE_PIN Y14 [get_ports p2_data[4]]
-set_property PACKAGE_PIN Y16 [get_ports p2_data[3]]
-set_property PACKAGE_PIN AA16 [get_ports p2_data[2]]
-set_property PACKAGE_PIN AB16 [get_ports p2_data[1]]
-set_property PACKAGE_PIN AB17 [get_ports p2_data[0]]
-
 set_property IOSTANDARD LVCMOS33 [get_ports p2_clk]
 set_property IOSTANDARD LVCMOS33 [get_ports p2_wrt]
-set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[0]}]
 
-set_property SLEW FAST [get_ports {p2_clk}]
+set_property SLEW FAST [get_ports p2_clk]
 
+set_property PACKAGE_PIN C18 [get_ports p2_clk]
+set_property PACKAGE_PIN C19 [get_ports p2_wrt]
+set_property PACKAGE_PIN B17 [get_ports {p2_data[13]}]
+set_property PACKAGE_PIN B18 [get_ports {p2_data[12]}]
+set_property PACKAGE_PIN D17 [get_ports {p2_data[11]}]
+set_property PACKAGE_PIN C17 [get_ports {p2_data[10]}]
+set_property PACKAGE_PIN A15 [get_ports {p2_data[9]}]
+set_property PACKAGE_PIN A16 [get_ports {p2_data[8]}]
+set_property PACKAGE_PIN B15 [get_ports {p2_data[7]}]
+set_property PACKAGE_PIN B16 [get_ports {p2_data[6]}]
+set_property PACKAGE_PIN A13 [get_ports {p2_data[5]}]
+set_property PACKAGE_PIN A14 [get_ports {p2_data[4]}]
+set_property PACKAGE_PIN E16 [get_ports {p2_data[3]}]
+set_property PACKAGE_PIN D16 [get_ports {p2_data[2]}]
+set_property PACKAGE_PIN C14 [get_ports {p2_data[1]}]
+set_property PACKAGE_PIN C15 [get_ports {p2_data[0]}]
 

designs/README.md

@@ -1,3 +1,5 @@
 # Директория с тестовыми проектами под ПЛИСу
 
 - eth_ctrl_debug: проект с ethernet и контроллером. Позволяет через ILA проверить, что пакет правильно принимается и что значения правильно выставляются.
+
+- eth_generator: проект на базе eth_ctrl_debug, в который включен генератор импульсов. В паре с ЦАП можно через консольку по Ethernet запускать генерацию разных импульсов.

designs/eth_ctrl_debug/README.md

@@ -0,0 +1,7 @@
+# Тестовый проект Eth + CTRL
+Проект состоит из AXIS Ethernet и контроллера. Для тестирования сделано три разных частотных домена: ethernet 125MHz, DAC 130MHz, ADC 65MHz для тестирования сихронизации. Есть ILA на все выходы контроллера и на шину AXIS eth -> ctrl. Для отправки пакетов используйте скрипт ```console.py --debug```.
+
+## Сборка
+```make all``` - собрать все до битстрима
+
+```make vivado``` - открыть проект в Vivado

designs/eth_generator/Makefile

@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xc7a35tfgg484-1
+FPGA_TOP = eth_generator_top
+FPGA_ARCH = artix7
+
+RTL_DIR = ../../rtl
+
+
+include ../../scripts/vivado.mk
+
+SYN_FILES += eth_generator.sv
+SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
+
+XCI_FILES = $(sort $(shell find ../../rtl/ethernet-udp/src -type f -name '*.xci'))
+XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
+
+XDC_FILES += ../../constraints/ax7a035b.xdc
+XDC_FILES += debug.xdc
+
+
+
+program: $(PROJECT).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
+	echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;

designs/eth_generator/README.md

@@ -0,0 +1,11 @@
+# Тестовый проект Generator + ETH + CTRL
+Проект состоит из AXIS Ethernet, контроллера и генератора. Позволяет генерировать сигналы, задав параметры через Ethernet.
+## Сборка
+```make all``` - собрать все до битстрима
+
+```make vivado``` - открыть проект в Vivado
+
+## Управление
+Используйте software/console.py. Пример:
+
+```python3 console.py --pulse_width 3_500_000 --pulse_period 20_000_000 --pulse_height 10000 --pulse_num 5500 --dac-bits 14```

designs/eth_generator/debug.xdc

@@ -0,0 +1,117 @@
+set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst]
+
+
+
+
+connect_debug_port u_ila_2/probe0 [get_nets [list {dac_pulse_height_dbg[0]} {dac_pulse_height_dbg[1]} {dac_pulse_height_dbg[2]} {dac_pulse_height_dbg[3]} {dac_pulse_height_dbg[4]} {dac_pulse_height_dbg[5]} {dac_pulse_height_dbg[6]} {dac_pulse_height_dbg[7]} {dac_pulse_height_dbg[8]} {dac_pulse_height_dbg[9]} {dac_pulse_height_dbg[10]} {dac_pulse_height_dbg[11]}]]
+connect_debug_port u_ila_2/probe1 [get_nets [list {dac_pulse_num_dbg[0]} {dac_pulse_num_dbg[1]} {dac_pulse_num_dbg[2]} {dac_pulse_num_dbg[3]} {dac_pulse_num_dbg[4]} {dac_pulse_num_dbg[5]} {dac_pulse_num_dbg[6]} {dac_pulse_num_dbg[7]} {dac_pulse_num_dbg[8]} {dac_pulse_num_dbg[9]} {dac_pulse_num_dbg[10]} {dac_pulse_num_dbg[11]} {dac_pulse_num_dbg[12]} {dac_pulse_num_dbg[13]} {dac_pulse_num_dbg[14]} {dac_pulse_num_dbg[15]}]]
+connect_debug_port u_ila_2/probe2 [get_nets [list {dac_pulse_period_dbg[0]} {dac_pulse_period_dbg[1]} {dac_pulse_period_dbg[2]} {dac_pulse_period_dbg[3]} {dac_pulse_period_dbg[4]} {dac_pulse_period_dbg[5]} {dac_pulse_period_dbg[6]} {dac_pulse_period_dbg[7]} {dac_pulse_period_dbg[8]} {dac_pulse_period_dbg[9]} {dac_pulse_period_dbg[10]} {dac_pulse_period_dbg[11]} {dac_pulse_period_dbg[12]} {dac_pulse_period_dbg[13]} {dac_pulse_period_dbg[14]} {dac_pulse_period_dbg[15]} {dac_pulse_period_dbg[16]} {dac_pulse_period_dbg[17]} {dac_pulse_period_dbg[18]} {dac_pulse_period_dbg[19]} {dac_pulse_period_dbg[20]} {dac_pulse_period_dbg[21]} {dac_pulse_period_dbg[22]} {dac_pulse_period_dbg[23]} {dac_pulse_period_dbg[24]} {dac_pulse_period_dbg[25]} {dac_pulse_period_dbg[26]} {dac_pulse_period_dbg[27]} {dac_pulse_period_dbg[28]} {dac_pulse_period_dbg[29]} {dac_pulse_period_dbg[30]} {dac_pulse_period_dbg[31]}]]
+connect_debug_port u_ila_2/probe3 [get_nets [list {dac_pulse_width_dbg[0]} {dac_pulse_width_dbg[1]} {dac_pulse_width_dbg[2]} {dac_pulse_width_dbg[3]} {dac_pulse_width_dbg[4]} {dac_pulse_width_dbg[5]} {dac_pulse_width_dbg[6]} {dac_pulse_width_dbg[7]} {dac_pulse_width_dbg[8]} {dac_pulse_width_dbg[9]} {dac_pulse_width_dbg[10]} {dac_pulse_width_dbg[11]} {dac_pulse_width_dbg[12]} {dac_pulse_width_dbg[13]} {dac_pulse_width_dbg[14]} {dac_pulse_width_dbg[15]} {dac_pulse_width_dbg[16]} {dac_pulse_width_dbg[17]} {dac_pulse_width_dbg[18]} {dac_pulse_width_dbg[19]} {dac_pulse_width_dbg[20]} {dac_pulse_width_dbg[21]} {dac_pulse_width_dbg[22]} {dac_pulse_width_dbg[23]} {dac_pulse_width_dbg[24]} {dac_pulse_width_dbg[25]} {dac_pulse_width_dbg[26]} {dac_pulse_width_dbg[27]} {dac_pulse_width_dbg[28]} {dac_pulse_width_dbg[29]} {dac_pulse_width_dbg[30]} {dac_pulse_width_dbg[31]}]]
+connect_debug_port u_ila_2/probe4 [get_nets [list dac_rst_dbg]]
+connect_debug_port u_ila_2/probe5 [get_nets [list dac_start_dbg]]
+
+
+connect_debug_port u_ila_1/probe7 [get_nets [list p2_wrt_OBUF]]
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 3 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {udp_ctrl_inst/eth_state[0]} {udp_ctrl_inst/eth_state[1]} {udp_ctrl_inst/eth_state[2]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 96 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {udp_ctrl_inst/cfg_bus_eth[0]} {udp_ctrl_inst/cfg_bus_eth[1]} {udp_ctrl_inst/cfg_bus_eth[2]} {udp_ctrl_inst/cfg_bus_eth[3]} {udp_ctrl_inst/cfg_bus_eth[4]} {udp_ctrl_inst/cfg_bus_eth[5]} {udp_ctrl_inst/cfg_bus_eth[6]} {udp_ctrl_inst/cfg_bus_eth[7]} {udp_ctrl_inst/cfg_bus_eth[8]} {udp_ctrl_inst/cfg_bus_eth[9]} {udp_ctrl_inst/cfg_bus_eth[10]} {udp_ctrl_inst/cfg_bus_eth[11]} {udp_ctrl_inst/cfg_bus_eth[12]} {udp_ctrl_inst/cfg_bus_eth[13]} {udp_ctrl_inst/cfg_bus_eth[14]} {udp_ctrl_inst/cfg_bus_eth[15]} {udp_ctrl_inst/cfg_bus_eth[16]} {udp_ctrl_inst/cfg_bus_eth[17]} {udp_ctrl_inst/cfg_bus_eth[18]} {udp_ctrl_inst/cfg_bus_eth[19]} {udp_ctrl_inst/cfg_bus_eth[20]} {udp_ctrl_inst/cfg_bus_eth[21]} {udp_ctrl_inst/cfg_bus_eth[22]} {udp_ctrl_inst/cfg_bus_eth[23]} {udp_ctrl_inst/cfg_bus_eth[24]} {udp_ctrl_inst/cfg_bus_eth[25]} {udp_ctrl_inst/cfg_bus_eth[26]} {udp_ctrl_inst/cfg_bus_eth[27]} {udp_ctrl_inst/cfg_bus_eth[28]} {udp_ctrl_inst/cfg_bus_eth[29]} {udp_ctrl_inst/cfg_bus_eth[30]} {udp_ctrl_inst/cfg_bus_eth[31]} {udp_ctrl_inst/cfg_bus_eth[32]} {udp_ctrl_inst/cfg_bus_eth[33]} {udp_ctrl_inst/cfg_bus_eth[34]} {udp_ctrl_inst/cfg_bus_eth[35]} {udp_ctrl_inst/cfg_bus_eth[36]} {udp_ctrl_inst/cfg_bus_eth[37]} {udp_ctrl_inst/cfg_bus_eth[38]} {udp_ctrl_inst/cfg_bus_eth[39]} {udp_ctrl_inst/cfg_bus_eth[40]} {udp_ctrl_inst/cfg_bus_eth[41]} {udp_ctrl_inst/cfg_bus_eth[42]} {udp_ctrl_inst/cfg_bus_eth[43]} {udp_ctrl_inst/cfg_bus_eth[44]} {udp_ctrl_inst/cfg_bus_eth[45]} {udp_ctrl_inst/cfg_bus_eth[46]} {udp_ctrl_inst/cfg_bus_eth[47]} {udp_ctrl_inst/cfg_bus_eth[48]} {udp_ctrl_inst/cfg_bus_eth[49]} {udp_ctrl_inst/cfg_bus_eth[50]} {udp_ctrl_inst/cfg_bus_eth[51]} {udp_ctrl_inst/cfg_bus_eth[52]} {udp_ctrl_inst/cfg_bus_eth[53]} {udp_ctrl_inst/cfg_bus_eth[54]} {udp_ctrl_inst/cfg_bus_eth[55]} {udp_ctrl_inst/cfg_bus_eth[56]} {udp_ctrl_inst/cfg_bus_eth[57]} {udp_ctrl_inst/cfg_bus_eth[58]} {udp_ctrl_inst/cfg_bus_eth[59]} {udp_ctrl_inst/cfg_bus_eth[60]} {udp_ctrl_inst/cfg_bus_eth[61]} {udp_ctrl_inst/cfg_bus_eth[62]} {udp_ctrl_inst/cfg_bus_eth[63]} {udp_ctrl_inst/cfg_bus_eth[64]} {udp_ctrl_inst/cfg_bus_eth[65]} {udp_ctrl_inst/cfg_bus_eth[66]} {udp_ctrl_inst/cfg_bus_eth[67]} {udp_ctrl_inst/cfg_bus_eth[68]} {udp_ctrl_inst/cfg_bus_eth[69]} {udp_ctrl_inst/cfg_bus_eth[70]} {udp_ctrl_inst/cfg_bus_eth[71]} {udp_ctrl_inst/cfg_bus_eth[72]} {udp_ctrl_inst/cfg_bus_eth[73]} {udp_ctrl_inst/cfg_bus_eth[74]} {udp_ctrl_inst/cfg_bus_eth[75]} {udp_ctrl_inst/cfg_bus_eth[76]} {udp_ctrl_inst/cfg_bus_eth[77]} {udp_ctrl_inst/cfg_bus_eth[78]} {udp_ctrl_inst/cfg_bus_eth[79]} {udp_ctrl_inst/cfg_bus_eth[80]} {udp_ctrl_inst/cfg_bus_eth[81]} {udp_ctrl_inst/cfg_bus_eth[82]} {udp_ctrl_inst/cfg_bus_eth[83]} {udp_ctrl_inst/cfg_bus_eth[84]} {udp_ctrl_inst/cfg_bus_eth[85]} {udp_ctrl_inst/cfg_bus_eth[86]} {udp_ctrl_inst/cfg_bus_eth[87]} {udp_ctrl_inst/cfg_bus_eth[88]} {udp_ctrl_inst/cfg_bus_eth[89]} {udp_ctrl_inst/cfg_bus_eth[90]} {udp_ctrl_inst/cfg_bus_eth[91]} {udp_ctrl_inst/cfg_bus_eth[92]} {udp_ctrl_inst/cfg_bus_eth[93]} {udp_ctrl_inst/cfg_bus_eth[94]} {udp_ctrl_inst/cfg_bus_eth[95]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 8 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 1 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list udp_ctrl_inst/axis_hs]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 1 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list udp_ctrl_inst/busy_flag_eth]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list m_axis_rx_tlast]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 1 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list m_axis_rx_tready]]
+create_debug_core u_ila_1 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
+set_property port_width 1 [get_debug_ports u_ila_1/clk]
+connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out1]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
+set_property port_width 14 [get_debug_ports u_ila_1/probe0]
+connect_debug_port u_ila_1/probe0 [get_nets [list {p2_data_OBUF[0]} {p2_data_OBUF[1]} {p2_data_OBUF[2]} {p2_data_OBUF[3]} {p2_data_OBUF[4]} {p2_data_OBUF[5]} {p2_data_OBUF[6]} {p2_data_OBUF[7]} {p2_data_OBUF[8]} {p2_data_OBUF[9]} {p2_data_OBUF[10]} {p2_data_OBUF[11]} {p2_data_OBUF[12]} {p2_data_OBUF[13]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
+set_property port_width 16 [get_debug_ports u_ila_1/probe1]
+connect_debug_port u_ila_1/probe1 [get_nets [list {dac_pulse_num[0]} {dac_pulse_num[1]} {dac_pulse_num[2]} {dac_pulse_num[3]} {dac_pulse_num[4]} {dac_pulse_num[5]} {dac_pulse_num[6]} {dac_pulse_num[7]} {dac_pulse_num[8]} {dac_pulse_num[9]} {dac_pulse_num[10]} {dac_pulse_num[11]} {dac_pulse_num[12]} {dac_pulse_num[13]} {dac_pulse_num[14]} {dac_pulse_num[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
+set_property port_width 14 [get_debug_ports u_ila_1/probe2]
+connect_debug_port u_ila_1/probe2 [get_nets [list {dac_pulse_height[0]} {dac_pulse_height[1]} {dac_pulse_height[2]} {dac_pulse_height[3]} {dac_pulse_height[4]} {dac_pulse_height[5]} {dac_pulse_height[6]} {dac_pulse_height[7]} {dac_pulse_height[8]} {dac_pulse_height[9]} {dac_pulse_height[10]} {dac_pulse_height[11]} {dac_pulse_height[12]} {dac_pulse_height[13]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
+set_property port_width 32 [get_debug_ports u_ila_1/probe3]
+connect_debug_port u_ila_1/probe3 [get_nets [list {dac_pulse_period[0]} {dac_pulse_period[1]} {dac_pulse_period[2]} {dac_pulse_period[3]} {dac_pulse_period[4]} {dac_pulse_period[5]} {dac_pulse_period[6]} {dac_pulse_period[7]} {dac_pulse_period[8]} {dac_pulse_period[9]} {dac_pulse_period[10]} {dac_pulse_period[11]} {dac_pulse_period[12]} {dac_pulse_period[13]} {dac_pulse_period[14]} {dac_pulse_period[15]} {dac_pulse_period[16]} {dac_pulse_period[17]} {dac_pulse_period[18]} {dac_pulse_period[19]} {dac_pulse_period[20]} {dac_pulse_period[21]} {dac_pulse_period[22]} {dac_pulse_period[23]} {dac_pulse_period[24]} {dac_pulse_period[25]} {dac_pulse_period[26]} {dac_pulse_period[27]} {dac_pulse_period[28]} {dac_pulse_period[29]} {dac_pulse_period[30]} {dac_pulse_period[31]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
+set_property port_width 32 [get_debug_ports u_ila_1/probe4]
+connect_debug_port u_ila_1/probe4 [get_nets [list {dac_pulse_width[0]} {dac_pulse_width[1]} {dac_pulse_width[2]} {dac_pulse_width[3]} {dac_pulse_width[4]} {dac_pulse_width[5]} {dac_pulse_width[6]} {dac_pulse_width[7]} {dac_pulse_width[8]} {dac_pulse_width[9]} {dac_pulse_width[10]} {dac_pulse_width[11]} {dac_pulse_width[12]} {dac_pulse_width[13]} {dac_pulse_width[14]} {dac_pulse_width[15]} {dac_pulse_width[16]} {dac_pulse_width[17]} {dac_pulse_width[18]} {dac_pulse_width[19]} {dac_pulse_width[20]} {dac_pulse_width[21]} {dac_pulse_width[22]} {dac_pulse_width[23]} {dac_pulse_width[24]} {dac_pulse_width[25]} {dac_pulse_width[26]} {dac_pulse_width[27]} {dac_pulse_width[28]} {dac_pulse_width[29]} {dac_pulse_width[30]} {dac_pulse_width[31]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
+set_property port_width 1 [get_debug_ports u_ila_1/probe5]
+connect_debug_port u_ila_1/probe5 [get_nets [list dac_rst]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
+set_property port_width 1 [get_debug_ports u_ila_1/probe6]
+connect_debug_port u_ila_1/probe6 [get_nets [list dac_start]]
+create_debug_core u_ila_2 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
+set_property port_width 1 [get_debug_ports u_ila_2/clk]
+connect_debug_port u_ila_2/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out2]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
+set_property port_width 8 [get_debug_ports u_ila_2/probe0]
+connect_debug_port u_ila_2/probe0 [get_nets [list {finish_cnt[0]} {finish_cnt[1]} {finish_cnt[2]} {finish_cnt[3]} {finish_cnt[4]} {finish_cnt[5]} {finish_cnt[6]} {finish_cnt[7]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
+set_property port_width 1 [get_debug_ports u_ila_2/probe1]
+connect_debug_port u_ila_2/probe1 [get_nets [list finish_dbg]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2]
+set_property port_width 1 [get_debug_ports u_ila_2/probe2]
+connect_debug_port u_ila_2/probe2 [get_nets [list finish_pending]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets adc_clk]

designs/eth_generator/eth_generator.sv

@@ -0,0 +1,345 @@
+`timescale 1 ns / 1 ns
+
+module eth_generator_top #(
+    parameter int unsigned DAC_DATA_WIDTH = 14
+)(
+    input               sys_clk_p,
+    input               sys_clk_n,
+    input               rst_n,
+
+    output [3:0]        led,
+
+    output              e_reset,
+    output              e_mdc,
+    inout               e_mdio,
+
+    output [3:0]        rgmii_txd,
+    output              rgmii_txctl,
+    output              rgmii_txc,
+    input  [3:0]        rgmii_rxd,
+    input               rgmii_rxctl,
+    input               rgmii_rxc,
+
+    // DAC
+    output              p2_clk,
+    output              p2_wrt,
+    (* MARK_DEBUG="true" *) output [13:0]       p2_data
+);
+
+    // -------------------------------------------------------------------------
+    // Internal GMII-side signals
+    // -------------------------------------------------------------------------
+    wire  [7:0] gmii_txd;
+    wire        gmii_tx_en;
+    wire        gmii_tx_er;
+    wire        gmii_tx_clk;
+    wire        gmii_crs;
+    wire        gmii_col;
+    wire  [7:0] gmii_rxd_i;
+    wire        gmii_rx_dv;
+    wire        gmii_rx_er;
+    wire        gmii_rx_clk;
+
+    wire [31:0] pack_total_len;
+
+    wire        e_rx_dv;
+    wire [7:0]  e_rxd;
+    wire        e_tx_en;
+    wire [7:0]  e_txd;
+    wire        e_rst_n;
+    wire        sys_clk;
+
+    wire        duplex_mode;
+    
+
+    assign duplex_mode = 1'b1;
+
+    // -------------------------------------------------------------------------
+    // System clock buffer (200 MHz differential input)
+    // -------------------------------------------------------------------------
+    IBUFDS sys_clk_ibufgds (
+        .O  (sys_clk),
+        .I  (sys_clk_p),
+        .IB (sys_clk_n)
+    );
+
+    // -------------------------------------------------------------------------
+    // IDELAYCTRL
+    // -------------------------------------------------------------------------
+    (* IODELAY_GROUP = "rgmii_idelay_group" *)
+    IDELAYCTRL IDELAYCTRL_inst (
+        .RDY    (),
+        .REFCLK (sys_clk),
+        .RST    (1'b0)
+    );
+
+    // -------------------------------------------------------------------------
+    // Generated clocks for controller
+    // Need to create this IP in Vivado:
+    //  input : 200 MHz
+    //  output0: 130 MHz
+    //  output1: 65 MHz
+    // -------------------------------------------------------------------------
+    wire dac_clk;
+    wire adc_clk;
+    wire clk_wiz_locked;
+
+    clk_wiz_ctrl_inst clk_wiz_ctrl_inst (
+        .clk_in1   (sys_clk),
+        .reset    (~rst_n),
+        .clk_out1  (dac_clk),   // 130 MHz
+        .clk_out2  (adc_clk),   // 65 MHz
+        .locked    (clk_wiz_locked)
+    );
+
+    // -------------------------------------------------------------------------
+    // GMII <-> RGMII conversion
+    // -------------------------------------------------------------------------
+    util_gmii_to_rgmii util_gmii_to_rgmii_m0 (
+        .reset           (1'b0),
+        .rgmii_td        (rgmii_txd),
+        .rgmii_tx_ctl    (rgmii_txctl),
+        .rgmii_txc       (rgmii_txc),
+        .rgmii_rd        (rgmii_rxd),
+        .rgmii_rx_ctl    (rgmii_rxctl),
+        .gmii_rx_clk     (gmii_rx_clk),
+        .gmii_txd        (e_txd),
+        .gmii_tx_en      (e_tx_en),
+        .gmii_tx_er      (1'b0),
+        .gmii_tx_clk     (gmii_tx_clk),
+        .gmii_crs        (gmii_crs),
+        .gmii_col        (gmii_col),
+        .gmii_rxd        (gmii_rxd_i),
+        .rgmii_rxc       (rgmii_rxc),
+        .gmii_rx_dv      (gmii_rx_dv),
+        .gmii_rx_er      (gmii_rx_er),
+        .speed_selection (2'b10),
+        .duplex_mode     (duplex_mode)
+    );
+
+    // -------------------------------------------------------------------------
+    // GMII arbitration / adaptation
+    // -------------------------------------------------------------------------
+    gmii_arbi arbi_inst (
+        .clk            (gmii_tx_clk),
+        .rst_n          (rst_n),
+        .speed          (2'b10),
+        .link           (1'b1),
+        .pack_total_len (pack_total_len),
+        .e_rst_n        (e_rst_n),
+        .gmii_rx_dv     (gmii_rx_dv),
+        .gmii_rxd       (gmii_rxd_i),
+        .gmii_tx_en     (gmii_tx_en),
+        .gmii_txd       (gmii_txd),
+        .e_rx_dv        (e_rx_dv),
+        .e_rxd          (e_rxd),
+        .e_tx_en        (e_tx_en),
+        .e_txd          (e_txd)
+    );
+
+    // -------------------------------------------------------------------------
+    // axis_mac interface
+    // RX stream from Ethernet goes into controller
+    // TX stream is unused for now
+    // -------------------------------------------------------------------------
+    wire        req_ready;
+
+    reg         send_req;
+    reg  [15:0] data_length;
+
+    reg  [7:0]  s_axis_tx_tdata;
+    reg         s_axis_tx_tvalid;
+    wire        s_axis_tx_tready;
+    reg         s_axis_tx_tlast;
+
+    (* MARK_DEBUG="true" *) wire [7:0]  m_axis_rx_tdata;
+    (* MARK_DEBUG="true" *) wire        m_axis_rx_tvalid;
+    (* MARK_DEBUG="true" *) wire        m_axis_rx_tlast;
+    (* MARK_DEBUG="true" *) wire        m_axis_rx_tready;
+
+    // Always ready to accept RX payload bytes
+    assign m_axis_rx_tready = 1'b1;
+
+    // TX disabled
+    always @(*) begin
+        send_req        = 1'b0;
+        data_length     = 16'd0;
+        s_axis_tx_tdata = 8'd0;
+        s_axis_tx_tvalid= 1'b0;
+        s_axis_tx_tlast = 1'b0;
+    end
+
+    axis_mac axis_mac0 (
+        .gmii_tx_clk       (gmii_tx_clk),
+        .gmii_rx_clk       (gmii_rx_clk),
+        .rst_n             (e_rst_n),
+
+        .gmii_rx_dv        (e_rx_dv),
+        .gmii_rxd          (e_rxd),
+        .gmii_tx_en        (gmii_tx_en),
+        .gmii_txd          (gmii_txd),
+
+        .send_req          (send_req),
+        .data_length       (data_length),
+        .req_ready         (req_ready),
+
+        .s_axis_tx_tdata   (s_axis_tx_tdata),
+        .s_axis_tx_tvalid  (s_axis_tx_tvalid),
+        .s_axis_tx_tready  (s_axis_tx_tready),
+        .s_axis_tx_tlast   (s_axis_tx_tlast),
+
+        .m_axis_rx_tdata   (m_axis_rx_tdata),
+        .m_axis_rx_tvalid  (m_axis_rx_tvalid),
+        .m_axis_rx_tready  (m_axis_rx_tready),
+        .m_axis_rx_tlast   (m_axis_rx_tlast)
+    );
+
+    // PHY reset helper from your original example
+    reset reset_m0 (
+        .clk   (sys_clk),
+        .key1  (rst_n),
+        .rst_n (e_reset)
+    );
+
+    // MDIO lines are not driven here yet
+    assign e_mdc  = 1'b0;
+    assign e_mdio = 1'bz;
+
+    // -------------------------------------------------------------------------
+    // Controller reset
+    // Use both external reset and clk_wiz lock
+    // -------------------------------------------------------------------------
+    wire ctrl_rst_n = rst_n & clk_wiz_locked;
+
+    // -------------------------------------------------------------------------
+    // Debug finish generator (still used here, since generator doesn't have finish signal)
+    //
+    // After each adc_start pulse generates one finish pulse after some delay.
+    // This is just for first bring-up so the controller can leave busy state
+    // If you don't want this, replace with:
+    // wire finish_dbg = 1'b0;
+    // -------------------------------------------------------------------------
+    (* MARK_DEBUG="true" *) logic        finish_dbg;
+    (* MARK_DEBUG="true" *) logic [7:0]  finish_cnt;
+    (* MARK_DEBUG="true" *) logic        finish_pending;
+
+    // Controller outputs to debug
+    (* MARK_DEBUG="true" *) wire [31:0]               dac_pulse_width;
+    (* MARK_DEBUG="true" *) wire [31:0]               dac_pulse_period;
+    (* MARK_DEBUG="true" *) wire [DAC_DATA_WIDTH-1:0] dac_pulse_height;
+    (* MARK_DEBUG="true" *) wire [15:0]               dac_pulse_num;
+
+    (* MARK_DEBUG="true" *) wire [31:0]               adc_pulse_period_dbg;
+    (* MARK_DEBUG="true" *) wire [15:0]               adc_pulse_num_dbg;
+
+    (* MARK_DEBUG="true" *) wire                      dac_start;
+    (* MARK_DEBUG="true" *) wire                      adc_start_dbg;
+    (* MARK_DEBUG="true" *) wire                      dac_rst;
+    (* MARK_DEBUG="true" *) wire                      adc_rst_dbg;
+
+    always_ff @(posedge adc_clk or negedge ctrl_rst_n) begin
+        if (!ctrl_rst_n) begin
+            finish_dbg     <= 1'b0;
+            finish_cnt     <= 8'd0;
+            finish_pending <= 1'b0;
+        end else begin
+            finish_dbg <= 1'b0;
+
+            if (adc_start_dbg) begin
+                finish_pending <= 1'b1;
+                finish_cnt     <= 8'd80;
+            end else if (finish_pending) begin
+                if (finish_cnt == 8'd0) begin
+                    finish_dbg     <= 1'b1;
+                    finish_pending <= 1'b0;
+                end else begin
+                    finish_cnt <= finish_cnt - 8'd1;
+                end
+            end
+        end
+    end
+
+    // -------------------------------------------------------------------------
+    // Controller
+    // ETH domain = gmii_rx_clk, because RX AXI master comes from axis_mac RX side
+    // -------------------------------------------------------------------------
+    control #(
+        .DAC_DATA_WIDTH(DAC_DATA_WIDTH)
+    ) udp_ctrl_inst (
+        .eth_clk_in        (gmii_rx_clk),
+        .dac_clk_in        (dac_clk),
+        .adc_clk_in        (adc_clk),
+        .rst_n             (ctrl_rst_n),
+
+        .s_axis_tdata      (m_axis_rx_tdata),
+        .s_axis_tvalid     (m_axis_rx_tvalid),
+        .s_axis_tready     (), // controller internally always ready in current version
+        .s_axis_tlast      (m_axis_rx_tlast),
+
+        .finish            (finish_dbg),
+
+        .dac_pulse_width   (dac_pulse_width),
+        .dac_pulse_period  (dac_pulse_period),
+        .dac_pulse_height  (dac_pulse_height),
+        .dac_pulse_num     (dac_pulse_num),
+
+        .adc_pulse_period  (adc_pulse_period_dbg),
+        .adc_pulse_num     (adc_pulse_num_dbg),
+
+        .dac_start         (dac_start),
+        .adc_start         (adc_start_dbg),
+
+        .dac_rst           (dac_rst),
+        .adc_rst           (adc_rst_dbg)
+    );
+
+    // -------------------------------------------------------------------------
+    // DAC
+    // -------------------------------------------------------------------------
+    generator #(
+        .DATA_WIDTH(DAC_DATA_WIDTH)
+    ) generator_inst (
+        .clk_in(dac_clk),
+        .rst(dac_rst),
+        .start(dac_start),
+        .pulse_width(dac_pulse_width),
+        .pulse_period(dac_pulse_period),
+        .pulse_height(dac_pulse_height),
+        .pulse_num(dac_pulse_num),
+        .pulse(p2_wrt ),
+        .pulse_height_out(p2_data)
+    );
+
+    // dac clk mgt
+    wire p2_clk_oddr;
+
+    ODDR #(
+        .DDR_CLK_EDGE("SAME_EDGE"),
+        .INIT(1'b0),
+        .SRTYPE("SYNC")
+    ) ODDR_p2_clk (
+        .Q (p2_clk_oddr),
+        .C (dac_clk),
+        .CE(1'b1),
+        .D1(1'b1),
+        .D2(1'b0),
+        .R (1'b0),
+        .S (1'b0)
+    );
+
+    OBUF OBUF_p2_clk (
+        .I(p2_clk_oddr),
+        .O(p2_clk)
+    );
+    
+    //assign p2_wrt = p2_clk;
+
+    // -------------------------------------------------------------------------
+    // Simple LED status
+    // -------------------------------------------------------------------------
+    assign led[0] = clk_wiz_locked;
+    assign led[1] = m_axis_rx_tvalid;
+    assign led[2] = dac_start;
+    assign led[3] = adc_rst_dbg;
+
+endmodule

designs/eth_generator/ip/clk_wiz_ctrl_inst.xci

@@ -0,0 +1,689 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "clk_wiz_ctrl_inst",
+    "component_reference": "xilinx.com:ip:clk_wiz:6.0",
+    "ip_revision": "16",
+    "gen_directory": "../../../../eth_generator_top.gen/sources_1/ip/clk_wiz_ctrl_inst",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "user", "usage": "all" } ],
+        "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
+        "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
+        "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_IN_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
+        "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
+        "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
+        "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
+        "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
+        "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+        "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
+        "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN1_JITTER_PS": [ { "value": "50.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "NUM_OUT_CLKS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
+        "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
+        "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
+        "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
+        "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
+        "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
+        "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
+        "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
+        "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
+        "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
+        "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
+        "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
+        "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
+        "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
+        "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
+        "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
+        "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
+        "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
+        "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
+        "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_DIVCLK_DIVIDE": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_CLKFBOUT_MULT_F": [ { "value": "16.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "6.750", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT1_DIVIDE": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
+        "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
+        "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
+        "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_JITTER": [ { "value": "162.582", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_PHASE_ERROR": [ { "value": "137.238", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_JITTER": [ { "value": "185.296", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_PHASE_ERROR": [ { "value": "137.238", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
+        "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
+        "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "c_component_name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_OUT_CLKS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW0": [ { "value": "Input Clock   Freq (MHz)    Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW1": [ { "value": "__primary_________200.000____________0.010", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0A": [ { "value": " Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0B": [ { "value": "  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__125.00000______0.000______50.0______162.582____137.238", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__64.90385______0.000______50.0______185.296____137.238", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_OUT_FREQ": [ { "value": "125.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_OUT_FREQ": [ { "value": "64.90385", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "16.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_DIVCLK_DIVIDE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "6.750", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
+        "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
+        "C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
+        "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
+        "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
+        "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
+        "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
+        "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
+        "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
+        "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKIN1_JITTER_PS": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
+        "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE2_AUTO": [ { "value": "1.9259259259259258", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE3_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE4_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE5_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE6_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE7_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "125.00000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "64.90385", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_D_MAX": [ { "value": "80.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MAX": [ { "value": "1200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "artix7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7a35t" } ],
+        "PACKAGE": [ { "value": "fgg484" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-1" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "16" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../eth_generator_top.gen/sources_1/ip/clk_wiz_ctrl_inst" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2025.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "reset": [ { "direction": "in", "driver_value": "0" } ],
+        "clk_in1": [ { "direction": "in" } ],
+        "clk_out1": [ { "direction": "out" } ],
+        "clk_out2": [ { "direction": "out" } ],
+        "locked": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "reset" } ]
+          }
+        },
+        "clock_CLK_IN1": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_IN1": [ { "physical_name": "clk_in1" } ]
+          }
+        },
+        "clock_CLK_OUT1": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_OUT1": [ { "physical_name": "clk_out1" } ]
+          }
+        },
+        "clock_CLK_OUT2": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_OUT2": [ { "physical_name": "clk_out2" } ]
+          }
+        }
+      }
+    }
+  }
+}

rtl/accum/src/out_axis_fifo.sv

@@ -0,0 +1,322 @@
+module out_axis_fifo #(
+    parameter ACCUM_WIDTH = 32,
+    parameter WINDOW_SIZE = 65,
+    parameter PACKET_SIZE = 1024
+) (
+    input  logic                eth_clk_in,
+    input  logic                acc_clk_in,
+    input  logic                rst,
+    input  logic [31:0]         smp_num,
+
+    // AXI stream master for output, eth_clk_in domain
+    output logic [7:0]          s_axis_tdata,
+    output logic                s_axis_tvalid,
+    input  logic                s_axis_tready,
+    output logic                s_axis_tlast,
+    // eth handshake
+    input  logic                req_ready,
+    output logic                send_req,
+    output logic [15:0]         udp_data_length,
+
+    // data from acc
+    input  logic [ACCUM_WIDTH-1:0]   acc_din,
+    input  logic                     din_valid,
+    
+    // input pulse
+    input  logic                readout_begin,
+
+    // output pulses
+    output logic batch_req,
+    output logic finish      
+);
+    // sync reset
+    reg [1:0] rst_sync_ff;
+    reg rst_eth;
+
+    always @(posedge acc_clk_in or posedge rst) begin
+        if (rst) begin
+            rst_sync_ff <= 2'b11;
+        end else begin
+            rst_sync_ff <= {rst_sync_ff[0], 1'b0};
+        end
+    end
+
+    assign rst_eth = rst_sync_ff[1];
+
+    logic [1:0] rst_acc_ff;
+    logic rst_acc;
+
+    always_ff @(posedge acc_clk_in or posedge rst) begin
+        if (rst)
+            rst_acc_ff <= 2'b11;
+        else
+            rst_acc_ff <= {rst_acc_ff[0], 1'b0};
+    end
+
+    assign rst_acc = rst_acc_ff[1];
+
+
+    // fifo params calc
+    // round up to be enough for 2xPACKET_SIZE storage
+    localparam int MIN_BYTES      = 2 * PACKET_SIZE;
+    localparam int MIN_BITS       = MIN_BYTES * 8;
+    localparam int MIN_WR_WORDS   = (MIN_BITS + ACCUM_WIDTH - 1) / ACCUM_WIDTH; // ceil div
+    localparam int WDEPTH_BITS    = $clog2(MIN_WR_WORDS);
+    localparam int FIFO_WDEPTH    = 1 << WDEPTH_BITS;
+
+    localparam int FIFO_RDEPTH     = FIFO_WDEPTH * ACCUM_WIDTH / 8;
+    localparam int RDEPTH_BITS     = $clog2(FIFO_RDEPTH) + 1;
+
+    wire wr_unavail;
+    wire wr_rst_busy;
+    reg rd_en;
+    
+    
+    typedef enum logic [2:0] {
+        WR_IDLE         = 3'd0,
+        WR_CHECK        = 3'd1,
+        WR_RUN          = 3'd2,
+        WR_END          = 3'd3
+    } wr_state_t;
+
+    (* MARK_DEBUG="true" *) wr_state_t wr_state;
+    
+    // Write FSM
+    reg [31:0] wr_cnt;       // current BIT mem ptr
+    reg [31:0] wr_batch_tgt; // next 'target' that should be written from batch
+    reg [31:0] wr_total;     // total BITS to be sent!
+
+    wire [WDEPTH_BITS:0] wr_data_count;
+
+    // NOTE:
+    // each written "acc_din" ACCUM_WIDTH word
+    // is counted as WINDOWS_SIZE samples actually
+    // because hw division for counters is painful
+    // so we just increased the counter sizes
+
+    always_ff @(posedge acc_clk_in) begin
+        if (rst_acc) begin
+            wr_state        <= WR_IDLE;
+            wr_cnt          <= 32'b0;
+            wr_batch_tgt    <= 32'b0;
+            wr_total        <= 32'b0;
+            batch_req       <= 0;
+            finish          <= 0;
+            
+        end else begin
+
+            case (wr_state)
+                // wait until readout is requested
+                WR_IDLE: begin
+                    if (readout_begin) begin 
+                        wr_cnt <= 32'b0;
+                        wr_state <= WR_CHECK;
+                        wr_total <= smp_num * ACCUM_WIDTH;
+                        wr_batch_tgt <= 32'b0;
+                        batch_req <= 0;
+                        finish <= 0;
+                    end
+                end
+                
+                // wait until we can request a word
+                // depends on prog_full signal
+                WR_CHECK: begin
+                    if (~wr_unavail && ~wr_rst_busy) begin
+                        batch_req <= 1;
+                        // should give us exactly PACKET_SIZE * 8 bits
+                        // multiplied by WINDOW_SIZE, because we count 
+                        // each given ACCUM_WIDTH word as WINDOWS_SIZE samples !!!
+                        wr_batch_tgt <= wr_batch_tgt + (8 * WINDOW_SIZE * PACKET_SIZE);
+                        wr_state <= WR_RUN;
+                    end else begin
+                        batch_req <= 0;
+                    end
+                end
+
+                // wait until all requested packet is written
+                WR_RUN: begin
+                    batch_req <= 0;
+                    if (wr_cnt == wr_batch_tgt) begin
+                        // got enough words
+                        wr_state <= WR_END;
+                    end else if (wr_cnt > wr_batch_tgt) begin
+                        // weird case when accum gave us too much words
+                        // block resets
+                        wr_cnt <= 32'hffffffff;  // sort of signal for sim/ila
+                        wr_state <= WR_END;
+                    end
+
+                    if (din_valid) begin
+                        // data supplied
+                        // count as we got WINDOW_SIZE samples
+                        wr_cnt <= wr_cnt + ACCUM_WIDTH * WINDOW_SIZE;
+                    end
+                end
+
+                // check if this was last data batch
+                WR_END: begin
+                    // here we check that we sent enough data
+                    // wr_cnt should be by design PACKET_SIZE-aligned
+                    if (wr_cnt >= wr_total) begin
+                        // wait until all data is sent
+                        if (wr_data_count == 0) begin
+                            finish <= 1;
+                            wr_state <= WR_IDLE;
+                        end
+                    end else begin
+                        // next word
+                        wr_state <= WR_CHECK;
+                    end
+                end
+            endcase
+        end
+    end
+
+    // Readout FSM with ethernet request
+
+    assign udp_data_length = PACKET_SIZE;  // fixed packet size
+    reg [15:0] sent_cnt;
+
+    typedef enum logic [2:0] {
+        RD_IDLE         = 3'd0,
+        RD_CHECK        = 3'd1,
+        RD_SEND         = 3'd2
+    } rd_state_t;
+
+    (* MARK_DEBUG="true" *) rd_state_t rd_state;
+
+    wire rd_valid;
+    wire [RDEPTH_BITS-1:0] rd_data_count;
+
+    always_ff @(posedge eth_clk_in) begin
+        if (rst_eth) begin
+            rd_state <= RD_IDLE;
+            send_req <= 1'b0;
+            sent_cnt <= 16'd0;
+            s_axis_tlast <= 1'b0;
+            s_axis_tvalid <= 1'b0;
+            rd_en <= 1'b0;
+            
+        end else begin
+
+            case (rd_state)
+                // wait until fifo has enough data to send
+                RD_IDLE: begin
+                    if (rd_data_count == PACKET_SIZE) begin
+                        // enough data to send packet, begin
+                        rd_state <= RD_CHECK;
+                    end
+                    send_req <= 1'b0;
+                    sent_cnt <= 16'd0;
+                    rd_en <= 1'b0;
+                    s_axis_tlast <= 1'b0;
+                    s_axis_tvalid <= 1'b0;
+                end
+
+                // await udp ready
+                RD_CHECK: begin
+                    if (req_ready) begin
+                        send_req <= 1'b1;
+                        rd_state <= RD_SEND;
+                    end
+                end
+
+                // send data
+                RD_SEND: begin
+                    // udp is ready and fifo is ready = sent
+                    send_req <= 1'b0;
+                    if (s_axis_tready && rd_valid) begin
+                        rd_en <= 1'b1;
+                        s_axis_tvalid <= 1'b1;
+                        sent_cnt <= sent_cnt + 1;
+                        // final packet of the batch
+                        if (sent_cnt == PACKET_SIZE - 1) begin
+                            rd_state <= RD_IDLE;
+                            s_axis_tlast <= 1'b1;
+                        end
+                    end else begin
+                        rd_en <= 1'b0;
+                        s_axis_tvalid <= 1'b0;
+                    end
+                end
+            endcase
+        end
+    end
+
+    logic [ACCUM_WIDTH-1:0] fifo_din_r, acc_din_reg, din_valid_reg;
+    logic                   fifo_wr_en_r;
+
+    always_ff @(posedge acc_clk_in) begin
+        if (rst_acc) begin
+            fifo_din_r   <= '0;
+            fifo_wr_en_r <= 1'b0;
+   
+            din_valid_reg <= 1'b0;
+        end else begin
+            fifo_wr_en_r  <= 1'b0;
+            acc_din_reg <= acc_din;
+            
+            if (!wr_rst_busy && din_valid_reg) begin
+                fifo_din_r   <= acc_din_reg;
+                fifo_wr_en_r  <= 1'b1;
+            end
+
+            din_valid_reg <= din_valid;
+        end
+    end
+
+    // xpm_fifo_async: Asynchronous FIFO
+    // Xilinx Parameterized Macro, version 2025.1
+
+    xpm_fifo_async #(
+        .DOUT_RESET_VALUE("0"),        // String
+        .FIFO_READ_LATENCY(1),         // DECIMAL
+        .FIFO_WRITE_DEPTH(FIFO_WDEPTH), 
+        .FULL_RESET_VALUE(0),
+        .PROG_EMPTY_THRESH(PACKET_SIZE),
+        .PROG_FULL_THRESH(PACKET_SIZE / (ACCUM_WIDTH / 8)),
+        .RD_DATA_COUNT_WIDTH(RDEPTH_BITS),    
+        .READ_DATA_WIDTH(8),           // always 8 bit for eth
+        .READ_MODE("fwft"),            
+        .SIM_ASSERT_CHK(1),            // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+        .USE_ADV_FEATURES("1616"),     // String
+        .WRITE_DATA_WIDTH(ACCUM_WIDTH),
+        .WR_DATA_COUNT_WIDTH(WDEPTH_BITS+1)
+    )
+    xpm_fifo_async_inst (
+
+        .data_valid(rd_valid),       // 1-bit output: Read Data Valid: When asserted, this signal indicates that valid data is available on the
+                                        // output bus (dout).
+
+        .dout(s_axis_tdata),
+        .empty( ), 
+    
+        .full( ),                 
+
+        .prog_full(wr_unavail),         // 1-bit output: Programmable Full: This signal is asserted when the number of words in the FIFO is greater than
+                                        // or equal to the programmable full threshold value. It is de-asserted when the number of words in the FIFO is
+                                        // less than the programmable full threshold value.
+
+        .rd_data_count(rd_data_count), // RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates the number of words read from the FIFO.
+
+        .wr_data_count(wr_data_count), // WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates the number of words written into the
+                                        // FIFO.
+
+
+
+
+        .rd_clk(eth_clk_in),               // 1-bit input: Read clock: Used for read operation. rd_clk must be a free running clock.
+        .rd_en(rd_en),                 // 1-bit input: Read Enable: If the FIFO is not empty, asserting this signal causes data (on dout) to be read
+                                        // from the FIFO. Must be held active-low when rd_rst_busy is active high.
+
+        .rst(rst),
+        
+        .din(fifo_din_r),                     // WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when writing the FIFO.
+        .wr_clk(acc_clk_in),               // 1-bit input: Write clock: Used for write operation. wr_clk must be a free running clock.
+        .wr_en(fifo_wr_en_r),
+
+        .wr_rst_busy(wr_rst_busy)
+
+    );
+
+endmodule

rtl/accum/tests/Makefile

@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xc7a35tfgg484-1
+FPGA_TOP = accum
+FPGA_ARCH = artix7
+
+RTL_DIR = ../src
+
+
+include ../../../scripts/vivado.mk
+
+SYN_FILES += $(sort $(shell find ../src -type f \( -name '*.v' -o -name '*.sv' \)))
+
+XCI_FILES = $(sort $(shell find ../src -type f -name '*.xci'))
+
+XDC_FILES += ../../../constraints/ax7a035b.xdc
+XDC_FILES += test_timing.xdc
+
+SYN_FILES += out_axis_fifo_tb.sv
+SIM_TOP = control_tb
+
+
+program: $(PROJECT).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
+	echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;

rtl/accum/tests/out_axis_fifo_tb.sv

@@ -0,0 +1,290 @@
+`timescale 1ns/1ps
+
+module tb_out_axis_fifo;
+
+    localparam int ACCUM_WIDTH = 32;
+    localparam int WINDOW_SIZE = 65;
+    localparam int PACKET_SIZE = 1024;
+    localparam int BYTES_PER_WORD = ACCUM_WIDTH / 8;
+    localparam int WORDS_PER_BATCH = PACKET_SIZE / BYTES_PER_WORD; // 1024 / 4 = 256 слов
+
+    logic eth_clk_in;
+    logic acc_clk_in;
+    logic rst;
+
+    logic [31:0] smp_num;
+
+    logic [7:0]  s_axis_tdata;
+    logic        s_axis_tvalid;
+    logic        s_axis_tready;
+    logic        s_axis_tlast;
+
+    logic [ACCUM_WIDTH-1:0] acc_din;
+    logic                   din_valid;
+
+    logic send_req;
+    logic req_ready;
+
+    logic readout_begin;
+
+    logic batch_req;
+    logic finish;
+
+    out_axis_fifo #(
+        .ACCUM_WIDTH(ACCUM_WIDTH),
+        .WINDOW_SIZE(WINDOW_SIZE),
+        .PACKET_SIZE(PACKET_SIZE)
+    ) dut (
+        .eth_clk_in    (eth_clk_in),
+        .acc_clk_in    (acc_clk_in),
+        .rst           (rst),
+        .smp_num       (smp_num),
+
+        .s_axis_tdata  (s_axis_tdata),
+        .s_axis_tvalid (s_axis_tvalid),
+        .s_axis_tready (s_axis_tready),
+        .s_axis_tlast  (s_axis_tlast),
+
+        .acc_din       (acc_din),
+        .din_valid     (din_valid),
+
+        .readout_begin (readout_begin),
+
+        .req_ready     (req_ready),
+        .send_req      (send_req),
+
+        .batch_req     (batch_req),
+        .finish        (finish)
+    );
+
+    // clocks
+    initial begin
+        eth_clk_in = 0;
+        forever #6 eth_clk_in = ~eth_clk_in;   // 125
+    end
+
+    initial begin
+        acc_clk_in = 0;
+        forever #7.692307692 acc_clk_in = ~acc_clk_in;   // 65
+    end
+
+    // scoreboard
+    byte expected_bytes[$];
+    int unsigned compared_bytes;
+    int unsigned mismatch_count;
+    int unsigned total_pushed_words;
+
+    task automatic scoreboard_reset();
+        begin
+            expected_bytes.delete();
+            compared_bytes   = 0;
+            mismatch_count   = 0;
+            total_pushed_words = 0;
+        end
+    endtask
+
+    task automatic push_expected_word(input logic [ACCUM_WIDTH-1:0] word);
+        begin
+            // queue push
+            expected_bytes.push_back(word[7:0]);
+            expected_bytes.push_back(word[15:8]);
+            expected_bytes.push_back(word[23:16]);
+            expected_bytes.push_back(word[31:24]);
+            total_pushed_words++;
+        end
+    endtask
+
+    task automatic check_expected_empty(string case_name);
+        begin
+            if (expected_bytes.size() != 0) begin
+                $error("[%0t] %s: expected_bytes is not empty, remaining=%0d",
+                       $time, case_name, expected_bytes.size());
+            end else begin
+                $display("[%0t] %s: scoreboard queue empty, all expected bytes were transmitted",
+                         $time, case_name);
+            end
+        end
+    endtask
+
+    // axis check
+    always_ff @(posedge eth_clk_in or posedge rst) begin
+        byte exp_byte;
+        if (rst) begin
+            compared_bytes <= 0;
+            mismatch_count <= 0;
+        end else begin
+            if (s_axis_tvalid && s_axis_tready) begin
+                if (expected_bytes.size() == 0) begin
+                    $error("[%0t] AXIS produced unexpected byte 0x%02x: expected queue is empty",
+                           $time, s_axis_tdata);
+                    mismatch_count <= mismatch_count + 1;
+                end else begin
+                    exp_byte = expected_bytes.pop_front();
+                    compared_bytes <= compared_bytes + 1;
+
+                    if (s_axis_tdata !== exp_byte) begin
+                        $error("[%0t] AXIS mismatch at byte #%0d: got=0x%02x expected=0x%02x",
+                               $time, compared_bytes, s_axis_tdata, exp_byte);
+                        mismatch_count <= mismatch_count + 1;
+                    end
+                end
+            end
+        end
+    end
+
+    // helpers
+    task automatic do_reset();
+        begin
+            rst           = 1'b1;
+            readout_begin = 1'b0;
+            din_valid     = 1'b0;
+            acc_din       = '0;
+            smp_num       = '0;
+
+            scoreboard_reset();
+
+            repeat (10) @(posedge acc_clk_in);
+            rst = 1'b0;
+
+            repeat (10) @(posedge acc_clk_in);
+        end
+    endtask
+
+    task automatic pulse_readout_begin(input logic [31:0] smp_num_i);
+        begin
+            smp_num = smp_num_i;
+            @(posedge acc_clk_in);
+            readout_begin <= 1'b1;
+            @(posedge acc_clk_in);
+            readout_begin <= 1'b0;
+        end
+    endtask
+
+    task automatic send_random_words(input int unsigned n_words);
+        int unsigned i;
+        logic [ACCUM_WIDTH-1:0] rand_word;
+        begin
+            for (i = 0; i < n_words; i++) begin
+                rand_word = $urandom;
+
+                @(posedge acc_clk_in);
+                din_valid <= 1'b1;
+                acc_din   <= rand_word;
+
+                // expected result
+                push_expected_word(rand_word);
+            end
+
+            @(posedge acc_clk_in);
+            din_valid <= 1'b0;
+            acc_din   <= '0;
+        end
+    endtask
+
+
+    // 1. set smp_num
+    // 2. pulse readout_begon
+    // 3. send 1KB (PACKET_SIZE) after each batch_req pulse
+    // 4. wait for finish
+    // 5. compare axis result
+    task automatic run_case(input logic [31:0] smp_num_i);
+        int batch_count;
+        string case_name;
+        begin
+            batch_count = 0;
+            case_name = $sformatf("run_case(smp_num=%0d)", smp_num_i);
+
+            $display("[%0t] %s start", $time, case_name);
+
+            pulse_readout_begin(smp_num_i);
+
+            while (finish !== 1'b1) begin
+                @(posedge acc_clk_in);
+
+                if (batch_req) begin
+                    batch_count++;
+                    $display("[%0t] %s: batch_req #%0d -> send %0d words",
+                             $time, case_name, batch_count, WORDS_PER_BATCH);
+
+                    send_random_words(WORDS_PER_BATCH);
+                end
+            end
+
+
+            repeat (200) @(posedge eth_clk_in);
+
+            $display("[%0t] %s done: batches=%0d, pushed_words=%0d, compared_bytes=%0d, mismatches=%0d, wr_cnt=%0d, wr_total=%0d",
+                     $time, case_name, batch_count, total_pushed_words, compared_bytes, mismatch_count,
+                     dut.wr_cnt, dut.wr_total);
+
+            check_expected_empty(case_name);
+
+            if (mismatch_count != 0) begin
+                $fatal(1, "[%0t] %s FAILED: mismatches=%0d", $time, case_name, mismatch_count);
+            end else begin
+                $display("[%0t] %s PASSED", $time, case_name);
+            end
+
+            @(posedge acc_clk_in);
+        end
+    endtask
+
+    // eth beh simulator
+    int axis_byte_count;
+
+    always_ff @(posedge eth_clk_in or posedge rst) begin
+        if (rst) begin
+            axis_byte_count <= 0;
+            req_ready       <= 0;
+            s_axis_tready   <= 1'b0;
+        end else begin
+            req_ready <= 1;
+
+            // request send
+            if (send_req) begin
+                s_axis_tready <= 1'b1;
+                req_ready <= 0;
+            end
+
+            if (s_axis_tvalid && s_axis_tready) begin
+                axis_byte_count <= axis_byte_count + 1;
+            end
+        end
+    end
+
+
+    // main
+    initial begin
+        // init
+        rst           = 1'b0;
+        readout_begin = 1'b0;
+        din_valid     = 1'b0;
+        acc_din       = '0;
+        smp_num       = '0;
+
+        repeat (500) @(posedge acc_clk_in);
+
+        // 1
+        do_reset();
+        repeat (500) @(posedge acc_clk_in);
+        run_case(32'd17);
+        repeat (20) @(posedge acc_clk_in);
+
+        // 2
+        do_reset();
+        run_case(32'd1024);
+        repeat (20) @(posedge acc_clk_in);
+
+        // 3
+        do_reset();
+        run_case(32'd77777);
+        repeat (20) @(posedge acc_clk_in);
+
+        do_reset();
+        repeat (20) @(posedge acc_clk_in);
+
+        $display("[%0t] ALL TESTS DONE", $time);
+        $finish;
+    end
+
+endmodule

rtl/accum/tests/test_timing.xdc

@@ -0,0 +1,10 @@
+# Primary clocks
+create_clock -name eth_clk -period 8.000  [get_ports eth_clk_in]
+create_clock -name acc_clk -period 15.385  [get_ports acc_clk_in]
+
+
+# Asynchronous clock groups
+
+set_clock_groups -name ASYNC_ETH_ACC -asynchronous \
+    -group [get_clocks eth_clk] \
+    -group [get_clocks acc_clk]

rtl/controller/README.md

@@ -0,0 +1,62 @@
+# Системный контроллер
+
+Контроллер принимает входные пакеты udp с ethernet, передаваемые по axi stream, и выполняет настройку выходных регистров в соотвествии с содержимым этого пакета, а также синхронизирует сигналы между тремя clock domains - есть clk от ethernet, clk для ЦАП и clk для АЦП
+
+## Список параметров:
+- dac_data_width - битность данных ЦАП, <= 16bit
+
+## Список входных портов:
+- eth_clk_in - базовая входная частота
+- dac_clk_in - входная частота ЦАП
+- adc_clk_in - входная частота АЦП
+- rst_n - общий reset 
+- s_axis [8 bit] - AXI stream slave для приема данных от ethernet udp (уже разобранный payload по байтам) - домен eth_clk
+- finish - сигнал окончания приема данных с АЦП, домен adc_clk !
+
+## Список выходных портов:
+- dac_pulse_width[31:0] - выход pulse_width в домене dac_clk
+- dac_pulse_period[31:0] - выход pulse_period в домене dac_clk
+- dac_pulse_height[dac_data_width-1:0] - выход pulse_height в домене dac_clk
+- dac_pulse_num[15:0] - выход pulse_num в домене dac_clk
+---
+- adc_pulse_period[31:0] - выход pulse_period в домене adc_clk
+- adc_pulse_num[15:0] - выход pulse_num в домене adc_clk
+---
+- dac_start - start в домене dac_clk
+- adc_start - start в домене adc_clk
+---
+- dac_rst - rst в домене dac_clk
+- adc_rst - rst в домене adc_clk
+
+## Логика работы:
+по умолчанию после инициализации блок встает в состояние ожидания (*idle*), и становится *ready* для приема данных по axis.
+далее ждет контрольный пакет. всего есть 3 вариации контрольных пакетов (в любом порядке), получаемых по axi stream:
+```
+8'b00001111 - soft reset
+8'b11110000 - start
+8'b10001000 - set_data
+```
+
+*soft reset* отправляет пульс rst на dac_rst и adc_rst, синхронизировав пульсы в их доменах. при этом сброс самого контроллера не происходит, значения остаются как и были
+
+*start* отправляет пульс start на dac_start и adc_start в их доменах. при этом после этого блок перестает быть ready и ждет, пока не придет пульс finish, после этого он возвращается снова в *idle* состояние
+
+*set_data* значит, что следующие 96 бит = 12*8 байт, пришедшии по axis - это конфигурационная информация и ее нужно записать в внутренний регистр на 96 бит.
+
+конфигурационный регистр на 96 бит делится так:
+```
+reg[31:0] - pulse_width
+reg[63:32] - pulse_period
+reg[79:64] - pulse_num
+reg[79+dac_data_width:80] - pulse_height
+```
+
+соотвественно эти записанные значения выставляются на соотвествующие выходные сигналы в доменах dac_clk и adc_clk. выходы обновляются каждый раз, когда происходит set_data, и сигналы сохраняют своё значение до следующего set_data.
+
+## Симуляция
+Тесты запускаются автоматически через make.
+```
+cd tests
+make sim
+```
+Должно выдать "All tests done" в конце симуляции.

rtl/generator/src/generator.sv

@@ -0,0 +1,103 @@
+`timescale 1ns / 1ps
+
+
+module generator
+#(
+    parameter DATA_WIDTH = 14
+    )
+(
+    input clk_in,
+    input rst,
+    input start,
+    input [31:0]           pulse_width,
+    input [31:0]           pulse_period,
+    input [DATA_WIDTH-1:0] pulse_height,
+    input [15:0]           pulse_num,
+    
+    output pulse,
+    output[DATA_WIDTH-1:0] pulse_height_out
+    
+    );
+    
+    logic [DATA_WIDTH-1:0] pulse_height_reg, pulse_height_out_reg;
+    logic pulse_reg;
+    
+    logic [31:0] pulse_width_reg, pulse_period_reg;
+    logic [15:0] pulse_num_reg;
+    
+    logic enable;
+    logic [15:0] cnt_pulse_num;
+    logic [31:0] cnt_period;
+    
+    logic start_d;
+
+    always @(posedge clk_in) begin
+        start_d <= start;
+    end
+
+    wire start_pulse = start & ~start_d;
+
+    
+    always @(posedge clk_in) begin
+        if (rst) begin
+            pulse_reg <= '0;
+            pulse_height_reg <= 0;
+            pulse_height_out_reg <= '0;
+            
+            pulse_width_reg <= '0;
+            pulse_period_reg <= '0;
+            pulse_num_reg <= '0;
+            enable <= 0;
+            cnt_pulse_num <= '0;
+            cnt_period <= '0;
+        end else begin
+            if (start) begin
+                enable <= 1'b1;
+//                pulse_width_reg <= pulse_width;
+//                pulse_period_reg <= pulse_period;
+//                pulse_num_reg <= pulse_num;
+//                pulse_height_reg <= pulse_height;
+                
+                cnt_pulse_num <= '0;
+                cnt_period <= '0;
+            end
+            if (enable) begin
+                pulse_reg <= 1;
+                
+                pulse_width_reg <= pulse_width;
+                pulse_period_reg <= pulse_period;
+                pulse_num_reg <= pulse_num;
+                pulse_height_reg <= pulse_height;
+                
+                if (pulse_reg) begin
+                
+                if (cnt_period < pulse_width_reg) begin
+                    pulse_height_out_reg <= pulse_height_reg;
+                end else begin
+                    pulse_height_out_reg <= '0;
+                end
+                if (cnt_period == pulse_period_reg - 1) begin
+                    cnt_period <= 0;
+                    if (cnt_pulse_num == pulse_num_reg - 1) begin
+                        enable <= 0;
+                        pulse_reg <= 0;
+                    end else begin
+                        cnt_pulse_num <= cnt_pulse_num + 1;
+                    end
+                end else begin
+                    cnt_period <= cnt_period + 1;
+                end
+                
+                end
+            end
+        end
+    end
+
+     OBUF OBUF_pulse_clk (
+        .I(clk_in),
+        .O(pulse)
+    );
+    
+    assign pulse_height_out = pulse_height_out_reg;
+    
+endmodule

rtl/generator/tests/generator_tb.sv

@@ -0,0 +1,105 @@
+`timescale 1ns / 1ps
+
+module generator_tb;
+
+    parameter DATA_WIDTH = 14;
+    parameter CLK_PERIOD = 16;
+
+    logic clk;
+    logic rst;
+    logic start;
+
+    logic [31:0] pulse_width;
+    logic [31:0] pulse_period;
+    logic [DATA_WIDTH-1:0] pulse_height;
+    logic [15:0] pulse_num;
+
+    logic pulse;
+    logic [DATA_WIDTH-1:0] pulse_height_out;
+
+    // DUT
+    generator #(
+        .DATA_WIDTH(DATA_WIDTH)
+    ) dut (
+        .clk_in(clk),
+        .rst(rst),
+        .start(start),
+        .pulse_width(pulse_width),
+        .pulse_period(pulse_period),
+        .pulse_height(pulse_height),
+        .pulse_num(pulse_num),
+        .pulse(pulse),
+        .pulse_height_out(pulse_height_out)
+    );
+
+    // Clock
+    initial begin
+        clk = 0;
+        forever #(CLK_PERIOD/2) clk = ~clk;
+    end
+
+    initial begin
+        $display("\n=== GENERATOR TEST ===\n");
+
+        rst = 1;
+        start = 0;
+
+        pulse_width  = 0;
+        pulse_period = 0;
+        pulse_height = 0;
+        pulse_num    = 0;
+
+        repeat(5) @(posedge clk);
+        rst = 0;
+
+        // --- Test 1 ---
+        // 3 clk 1, 5 clk 0,  4 pulses
+       repeat(2) @(posedge clk);
+        pulse_width  = 3;
+        pulse_period = 8;
+        pulse_num    = 4;
+        pulse_height = 14'h3FF;
+        start = 1;
+
+       repeat(1) @(posedge clk);
+        start = 0;
+
+        repeat(50) @(posedge clk);
+
+        // --- Test 2 ---
+        $display("\n--- SECOND RUN ---\n");
+
+        @(posedge clk);
+        pulse_width  = 2;
+        pulse_period = 5;
+        pulse_num    = 3;
+        pulse_height = 14'h155;
+        start = 1;
+
+        @(posedge clk);
+        start = 0;
+
+        repeat(40) @(posedge clk);
+        
+         pulse_width  = 3;
+        pulse_period = 8;
+        pulse_num    = 4;
+        pulse_height = 14'h3FF;
+        start = 1;
+
+       repeat(1) @(posedge clk);
+        start = 0;
+
+        repeat(50) @(posedge clk);
+
+        $display("\n=== TEST FINISHED ===");
+        $finish;
+    end
+
+    // Display
+    always @(posedge clk) begin
+        $display("t=%0t | pulse=%0b | height=%h",
+                  $time, pulse, pulse_height_out);
+    end
+
+endmodule

rtl/sampler/src/sampler.sv

@@ -0,0 +1,72 @@
+`timescale 1ns / 1ps
+
+
+
+module sampler
+#(
+    parameter DATA_WIDTH = 12,
+    parameter PACK_FACTOR = 3,
+    parameter PROCESS_MODE = 1
+    )
+(
+    input clk_in,
+    input rst,
+    input [DATA_WIDTH-1:0] data_in,
+    input out_of_range,
+
+    output logic [DATA_WIDTH*PACK_FACTOR-1:0]  m_axis_tdata,
+    output logic                              m_axis_tvalid
+    );
+    logic [DATA_WIDTH-1:0] data_converted;
+    logic out_of_range_reg;
+
+    always @( posedge clk_in) begin
+        if (rst) begin
+            data_converted <= '0;
+        end else begin
+            out_of_range_reg <= out_of_range;
+            if (PROCESS_MODE) begin
+                if (data_in == 12'b100000000000) begin
+                    data_converted <= data_in;
+                end else begin
+                    data_converted <= data_in[DATA_WIDTH-1]  ? {1'b1, (~data_in[DATA_WIDTH-2:0] + 1'b1)} : data_in; 
+                    
+                end
+            end else begin
+                data_converted <= data_in; 
+            end
+        end
+    end 
+    
+         
+    logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
+    logic buffer_ready;
+
+    logic [$clog2(PACK_FACTOR):0] cnt;
+    
+    always @(posedge clk_in) begin
+        if (rst) begin
+            buffer <= '0;
+            cnt <= -1; //
+            buffer_ready <= 0;
+        end
+        else begin
+            buffer_ready <= 0;
+            if (!out_of_range_reg) begin
+                buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
+                if (cnt == PACK_FACTOR-1) begin
+                    cnt <= 0;
+                    buffer_ready <= 1;
+                    buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
+                end
+                else begin
+                    cnt <= cnt + 1;
+                end
+            end
+        end
+    end
+    
+    assign m_axis_tdata = buffer;
+    assign m_axis_tvalid = buffer_ready;
+    
+endmodule

rtl/sampler/tests/sampler_tb_advanced.sv

@@ -0,0 +1,120 @@
+`timescale 1ns / 1ps
+
+module sampler_tb;
+
+    parameter DATA_WIDTH = 12;
+    parameter PACK_FACTOR = 3;
+    parameter PROCESS_MODE = 1;
+    parameter CLK_PERIOD = 15.3846;  // 65 MHz
+
+    logic clk;
+    logic rst;
+    logic [DATA_WIDTH-1:0] data_in;
+    logic out_of_range;
+    logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
+    logic m_axis_tvalid;
+
+    sampler #(
+        .DATA_WIDTH(DATA_WIDTH),
+        .PACK_FACTOR(PACK_FACTOR),
+        .PROCESS_MODE(PROCESS_MODE)
+    ) dut (
+        .clk_in(clk),
+        .rst(rst),
+        .data_in(data_in),
+        .out_of_range(out_of_range),
+        .m_axis_tdata(m_axis_tdata),
+        .m_axis_tvalid(m_axis_tvalid)
+    );
+
+    initial begin
+        clk = 0;
+        forever #(CLK_PERIOD/2) clk = ~clk;
+    end
+
+    task send(input [DATA_WIDTH-1:0] word, input bit oor);
+        @(posedge clk);
+        data_in <= word;
+        out_of_range <= oor;
+        $display("Send: %h (%0d) OOR=%b", word, word, oor);
+    endtask
+
+    initial begin
+        $display("\n=== SAMPLER TEST (MODE=%0d) ===\n", PROCESS_MODE);
+        
+        // Reset
+        rst = 1;
+        out_of_range = 0;
+        data_in = 0;
+//        send(12'h001, 0);
+        repeat(5) @(posedge clk);
+        rst = 0;
+        send(12'h001, 0);
+        repeat(1) @(posedge clk);
+        
+        // 1. Positive
+        $display("\n--- Positive numbers ---");
+//        send(12'h001, 0);
+        send(12'h002, 0);
+        send(12'h003, 0);
+        
+        send(12'h004, 0);
+        send(12'h005, 0);
+        send(12'h806, 0);
+        
+        // 2. Negative
+        $display("\n--- Negative numbers ---");
+        send(12'hFFF, 0);  // -1
+        send(12'hFFE, 0);  // -2
+        send(12'hFFD, 0);  // -3
+        
+        send(12'h800, 0);  // -2048
+        send(12'h801, 0);  // -2047
+        send(12'h802, 0);  // -2046
+        
+        // 3. Boundary
+        $display("\n--- Boundary values ---");
+        send(12'h000, 0);  // 0
+        send(12'h001, 0);  // 1
+        send(12'h7FF, 0);  // 2047 (max positive)
+        
+        send(12'h7FE, 0);  // 2046
+        send(12'h800, 0);  // -2048 (min negative)
+        send(12'hFFF, 0);  // -1
+        
+        // 4. Out of range tests
+        $display("\n--- Out of range tests ---");
+        
+
+        send(12'h00A, 0);
+        send(12'h00B, 1);  // 
+        send(12'h00C, 0);
+        send(12'h00D, 0);
+        send(12'h00E, 0);
+        send(12'h00F, 0);  
+        
+        send(12'h010, 0);
+        send(12'h011, 0);
+        send(12'h012, 1);  // 
+        
+        send(12'h013, 0);
+        send(12'h014, 0);
+        send(12'h015, 0); 
+        
+        repeat(10) @(posedge clk);
+        $display("\n=== TEST FINISHED ===");
+        $finish;
+    end
+
+    // Results
+    always @(posedge clk) begin
+        if (m_axis_tvalid) begin
+            $display("\n>>> PACKET RECEIVED at %0t ns:", $time);
+            $display("    Full: %h", m_axis_tdata);
+            $display("    Word0: %h", m_axis_tdata[11:0]);
+            $display("    Word1: %h", m_axis_tdata[23:12]);
+            $display("    Word2: %h\n", m_axis_tdata[35:24]);
+        end
+    end
+
+endmodule

rtl/sampler/tests/sampler_tb_basic.sv

@@ -0,0 +1,67 @@
+`timescale 1ns / 1ps
+
+module sampler_tb;
+
+    parameter DATA_WIDTH = 12;
+    parameter PACK_FACTOR = 3;
+    parameter PROCESS_MODE = 0;
+    
+    parameter CLK_PERIOD = 15.3846; 
+
+    logic clk;
+    logic rst;
+    logic [DATA_WIDTH-1:0] data_in;
+    logic out_of_range;
+
+    logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
+    logic m_axis_tvalid;
+
+    // DUT
+    sampler #(
+        .DATA_WIDTH(DATA_WIDTH),
+        .PACK_FACTOR(PACK_FACTOR),
+        .PROCESS_MODE(PROCESS_MODE)
+    ) dut (
+        .clk_in(clk),
+        .rst(rst),
+        .data_in(data_in),
+        .out_of_range(out_of_range),
+        .m_axis_tdata(m_axis_tdata),
+        .m_axis_tvalid(m_axis_tvalid)
+    );
+
+    // clock
+     initial begin
+        clk = 0;
+        forever #(CLK_PERIOD/2) clk = ~clk;
+    end
+
+    integer i;
+
+    initial begin
+        clk = 0;
+        rst = 1;
+        data_in = 0;
+        out_of_range = 0;
+
+        #20;
+        rst = 0;
+        repeat(5) @(posedge clk);
+
+        for (i = 1; i < 20; i++) begin
+            @(posedge clk);
+
+            data_in <= i;
+        end
+
+        #50;
+        $finish;
+    end
+
+    always @(posedge clk) begin
+        if (m_axis_tvalid) begin
+            $display("TIME=%0t PACKED DATA = %h", $time, m_axis_tdata);
+        end
+    end
+
+endmodule

scripts/vivado.mk

@@ -177,12 +177,11 @@ gen_ip:
 
 sim: $(PROJECT).xpr gen_ip
 	echo "open_project $(PROJECT).xpr" > run_sim.tcl
-	echo "add_files -fileset sim_1 $(TB_FILES)" >> run_sim.tcl
-	echo "set_property top $(SIM_TOP) [get_filesets sim_1]" >> run_sim.tcl
 	echo "update_compile_order -fileset sources_1" >> run_sim.tcl
 	echo "update_compile_order -fileset sim_1" >> run_sim.tcl
 	echo "launch_simulation" >> run_sim.tcl
-	echo "run all" >> run_sim.tcl
+	echo "run 1000 us" >> run_sim.tcl
+	echo "quit" >> run_sim.tcl
 	vivado -mode batch -source run_sim.tcl
 
 simclean:

software/console.py

@@ -49,8 +49,36 @@ def format_ctrl_data(pulse_width: int, pulse_period: int,
     return output
 
 
+def verify_args(args):
+    """check args are non zero and in bound, request from user if needed"""
+    if args.pulse_width == 0:
+        args.pulse_width = int(input("pulse_width: "))
+
+    if args.pulse_period == 0:
+        args.pulse_period = int(input("pulse_period: "))
+
+    if args.pulse_num == 0:
+        args.pulse_num = int(input("pulse_num: "))
+
+    if args.pulse_height == 0:
+        args.pulse_height = int(input("pulse_height: "))
+
+
 def run(args, sock):
-    pass
+    dest = (args.ip, args.send_port)
+
+    # reset
+    sock.sendto(0x0f00.to_bytes(2), dest)
+
+    # config data
+    sock.sendto(format_ctrl_data(args.pulse_width,
+                                 args.pulse_period,
+                                 args.pulse_height,
+                                 args.pulse_num,
+                                 dac_bits=args.dac_bits), dest)
+
+    sock.sendto(0xf000.to_bytes(2), dest)
+    print("Sent start!")
 
 
 def main():
@@ -85,6 +113,7 @@ def main():
     if args.debug:
         run_debug(args, sock)
     else:
+        verify_args(args)
         run(args, sock)
 
     sock.close()