Files
reflectometer_fpga_project/rtl/accum/tests/test_timing.xdc
2026-04-21 19:48:20 +03:00

11 lines
298 B
Tcl

# Primary clocks
create_clock -name eth_clk -period 8.000 [get_ports eth_clk_in]
create_clock -name acc_clk -period 15.385 [get_ports acc_clk_in]
# Asynchronous clock groups
set_clock_groups -name ASYNC_ETH_ACC -asynchronous \
-group [get_clocks eth_clk] \
-group [get_clocks acc_clk]