 otroubi
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8ca0e197d5
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add accum_done signal
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2026-07-29 14:03:18 +03:00 |
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otroubi
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5eb746c0ad
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testbench for accum adaptation for dma
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2026-07-29 10:18:33 +03:00 |
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otroubi
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4247a107ef
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accumulator adaptation for dma
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2026-07-29 10:17:58 +03:00 |
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otroubi
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bec1cee7a8
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transferring tests
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2026-07-28 14:07:40 +03:00 |
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otroubi
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ea9a6ad1e6
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accumulator's changes for dma integration
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2026-07-28 14:07:25 +03:00 |
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otroubi
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4acaea8d39
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Merge branch 'dev/design' into integration_new_controller
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2026-07-28 12:54:48 +03:00 |
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otroubi
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b731b1b75d
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transferring base tests for new controller design
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2026-07-28 12:51:42 +03:00 |
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otroubi
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32076b19f7
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transferring new controller design
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2026-07-28 12:51:05 +03:00 |
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otroubi
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c21c9d2ab5
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transferring test for controller dma ram connective
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2026-07-28 12:50:30 +03:00 |
|
 babintsev.lv
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56a0240f8e
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upd: sampler & TB complete
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2026-07-24 17:54:37 +03:00 |
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babintsev.lv
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81970c8b42
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upd: new TB, sampler refactor
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2026-07-21 16:54:06 +03:00 |
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babintsev.lv
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a528838741
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fix: patch for sampler
upd: reflectometer TB readaout data task
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2026-07-17 17:29:58 +03:00 |
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babintsev.lv
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04eb927a25
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fix: encoding issues, generator explicit default state
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2026-07-17 15:21:49 +03:00 |
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otroubi
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4240604f26
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sampler version with debugged OTR and debugged testbench
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2026-07-17 13:38:47 +03:00 |
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Zer0Nu11
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ef65dd1a97
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upd: DUT fully working. TB tests WIP
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2026-07-16 22:45:21 +03:00 |
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Zer0Nu11
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71b825ef2c
|
upd:
fix axi-stream interface definition;
successful TB DUT launch
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2026-07-16 19:33:51 +03:00 |
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babintsev.lv
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d80f5ff31f
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fix: revert synchronizer changes (false changes) and sampler
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2026-07-14 13:02:55 +03:00 |
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babintsev.lv
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493d6844c0
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bug: TB tasks broken
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2026-07-10 18:52:52 +03:00 |
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babintsev.lv
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11a9e97691
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upd: reflectometer on axis bus iface + TB
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2026-07-10 18:46:48 +03:00 |
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babintsev.lv
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0ba25a3541
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add: vrtual DAC & ADC subsystem for TB
fix: makefile
upd: clocking wiz IP
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2026-07-10 14:15:49 +03:00 |
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babintsev.lv
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64f94a90e6
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add: virtual DAC (100%) and ADC (80%)
upd: makefile
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2026-07-08 17:47:56 +03:00 |
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babintsev.lv
|
7665afd50b
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add: half-baked reflectometer TB
fix: constraints port names;
ready: reflectometer top module
|
2026-07-08 14:56:51 +03:00 |
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babintsev.lv
|
c3275d5b46
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upd: ref
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2026-07-07 15:12:48 +03:00 |
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otroubi
|
7b96fbddbf
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rtl: sampler modified
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2026-07-07 15:05:14 +03:00 |
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otroubi
|
2282eb4e16
|
Merge branch 'dev/design' of https://git.radiophotonics.ru/baulin.fa/reflectometer_fpga_project into dev/design
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2026-07-07 14:58:18 +03:00 |
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otroubi
|
287d855df4
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rtl: sampler modified
|
2026-07-07 14:47:34 +03:00 |
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babintsev.lv
|
725826b07c
|
add: new reflectometer top design (not ready)
|
2026-07-03 16:32:48 +03:00 |
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babintsev.lv
|
d878bac42a
|
upd: new top design WIP
|
2026-06-30 17:21:49 +03:00 |
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|
babintsev.lv
|
771225cd77
|
fix: post-implementation timing sim TB passed
|
2026-06-23 17:27:20 +03:00 |
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|
Zer0Nu11
|
b38a693676
|
fix: timing. New DAC-ADC line code
|
2026-06-20 09:33:33 +03:00 |
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Zer0Nu11
|
789255fa04
|
fix: add timing sim tricks
|
2026-06-20 04:05:37 +03:00 |
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|
Zer0Nu11
|
efcd6ef5d0
|
upd:
fast fix of sampler OTR.
fix debug.xdc
Major add of full automated testing for TB.
|
2026-06-20 03:07:05 +03:00 |
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Zer0Nu11
|
4fbecd5e30
|
upd: sync design log verbosity + optimal delay latency
|
2026-06-19 20:49:17 +03:00 |
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Zer0Nu11
|
d71aaf1650
|
fix: request/done protocol
|
2026-06-19 08:05:03 +03:00 |
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Zer0Nu11
|
035d02234c
|
Merge branch 'dev/design' of https://git.radiophotonics.ru/baulin.fa/reflectometer_fpga_project into dev/design
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2026-06-19 08:00:44 +03:00 |
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Zer0Nu11
|
4923f01322
|
upd: TB automation,
DA->AD delay line for signal integrity
|
2026-06-19 08:00:00 +03:00 |
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otroubi
|
45a57d57e4
|
sampler fix: made it beauty
|
2026-06-17 19:54:19 +03:00 |
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otroubi
|
29e1541ffb
|
Merge branch 'dev/design' of https://git.radiophotonics.ru/baulin.fa/reflectometer_fpga_project into dev/design
|
2026-06-17 19:32:46 +03:00 |
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babintsev.lv
|
fd9280737d
|
fix: refactoring
|
2026-06-16 20:26:45 +03:00 |
|
|
otroubi
|
64843b462d
|
rtl: sampler validation changes
|
2026-06-10 17:07:40 +03:00 |
|
|
babintsev.lv
|
c0714f271e
|
Merge remote-tracking branch 'refs/remotes/origin/dev/design' into dev/design
|
2026-06-10 16:44:00 +03:00 |
|
|
babintsev.lv
|
c165d346a0
|
update: new synchronizer + half-baked TB
|
2026-06-10 16:40:53 +03:00 |
|
|
otroubi
|
753f4a2128
|
readme sampler modification
|
2026-06-10 16:31:02 +03:00 |
|
|
otroubi
|
6155c6a9fb
|
change: sampler remark 2
|
2026-06-10 16:23:20 +03:00 |
|
|
otroubi
|
bb65aea4f1
|
change: sampler remarks
|
2026-06-10 16:22:05 +03:00 |
|
|
otroubi
|
5d3b761b07
|
change: delete makefile
|
2026-06-10 16:16:33 +03:00 |
|
|
otroubi
|
d7e46445d8
|
change: delete tb
|
2026-06-10 16:15:53 +03:00 |
|
|
otroubi
|
cacfe04061
|
change: naming problem
|
2026-06-10 16:14:29 +03:00 |
|
|
otroubi
|
4270c2fca8
|
rtl: final modified sampler
|
2026-06-10 15:50:39 +03:00 |
|
|
otroubi
|
cf2985813a
|
rtl: sampler synchronization modification
|
2026-06-10 13:10:50 +03:00 |
|