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fix: syntax errors

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This commit is contained in:
Phil
2026-05-29 15:30:24 +03:00
parent 338f30c0d7
commit 3261b66aaa
3 changed files with 7 additions and 7 deletions
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2
axi/axi_crossbar_wrapper.sv
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@ -2,7 +2,7 @@ module axi_crossbar_wrapper #(
parameter int SLAVE_QTY = 3,
parameter int MASTER_QTY = 3,
parameter int ADDR_WIDTH = 32,
parameter int DATA_WIDTH = 32
parameter int DATA_WIDTH = 32,
parameter int STRB_WIDTH = (DATA_WIDTH/8)
)(
input wire clk,

4
axi/axi_if.sv
View File

@ -13,7 +13,7 @@ interface axi4_if #(
typedef logic [DATA_W/8-1:0] strb_t;
typedef logic [ID_W-1:0] id_t;
typedef logic [USER_W-1:0] user_t;
`AXI4_TYPEDEF_ALL(axi, addr_t, data_t, strb_t, id_t, user_t)
`AXI4_TYPEDEF_ALL(axi, addr_t, data_t, strb_t, id_t, user_t);
axi_req_t req;
axi_resp_t resp;
modport master (input aclk, aresetn, output req, input resp);
@ -34,7 +34,7 @@ interface axi4l_if #(
typedef logic [DATA_W-1:0] data_t;
typedef logic [DATA_W/8-1:0] strb_t;
typedef logic [USER_W-1:0] user_t;
`AXI4L_TYPEDEF_ALL(axil, addr_t, data_t, strb_t, user_t)
`AXI4L_TYPEDEF_ALL(axil, addr_t, data_t, strb_t, user_t);
axil_req_t req;
axil_resp_t resp;
modport master (input aclk, aresetn, output req, input resp);

8
axi/axil_cdc_wrapper.sv
View File

@ -1,6 +1,6 @@
module axil_cdc_wrapper #(
parameter int ADDR_WIDTH = 32
parameter int DATA_WIDTH = 32,
parameter int ADDR_WIDTH = 32,
parameter int DATA_WIDTH = 32
)(
input wire s_clk,
input wire s_rst,
@ -83,8 +83,8 @@ module axil_cdc_wrapper #(
);
axil_cdc #(
.ADDR_WIDTH (ADDR_WIDTH)
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.DATA_WIDTH (DATA_WIDTH)
) i_axil_cdc (
.s_clk (s_clk),
.s_rst (s_rst),