rtl: add AXI if defines
This commit is contained in:
Phil
97
axi/axi4_flat_to_if.sv
Normal file
97
axi/axi4_flat_to_if.sv
Normal file
@ -0,0 +1,97 @@
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module axi4_flat_to_if #(
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parameter int unsigned ADDR_W = 32,
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parameter int unsigned DATA_W = 64,
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parameter int unsigned ID_W = 4,
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parameter int unsigned USER_W = 1
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)(
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input logic [ID_W-1:0] s_axi_awid,
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input logic [ADDR_W-1:0] s_axi_awaddr,
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input logic [7:0] s_axi_awlen,
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input logic [2:0] s_axi_awsize,
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input logic [1:0] s_axi_awburst,
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input logic s_axi_awlock,
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input logic [3:0] s_axi_awcache,
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input logic [2:0] s_axi_awprot,
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input logic [3:0] s_axi_awqos,
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input logic [3:0] s_axi_awregion,
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input logic [USER_W-1:0] s_axi_awuser,
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input logic s_axi_awvalid,
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output logic s_axi_awready,
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input logic [DATA_W-1:0] s_axi_wdata,
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input logic [DATA_W/8-1:0] s_axi_wstrb,
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input logic s_axi_wlast,
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input logic [USER_W-1:0] s_axi_wuser,
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input logic s_axi_wvalid,
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output logic s_axi_wready,
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output logic [ID_W-1:0] s_axi_bid,
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output logic [1:0] s_axi_bresp,
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output logic [USER_W-1:0] s_axi_buser,
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output logic s_axi_bvalid,
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input logic s_axi_bready,
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input logic [ID_W-1:0] s_axi_arid,
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input logic [ADDR_W-1:0] s_axi_araddr,
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input logic [7:0] s_axi_arlen,
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input logic [2:0] s_axi_arsize,
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input logic [1:0] s_axi_arburst,
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input logic s_axi_arlock,
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input logic [3:0] s_axi_arcache,
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input logic [2:0] s_axi_arprot,
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input logic [3:0] s_axi_arqos,
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input logic [3:0] s_axi_arregion,
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input logic [USER_W-1:0] s_axi_aruser,
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input logic s_axi_arvalid,
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output logic s_axi_arready,
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output logic [ID_W-1:0] s_axi_rid,
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output logic [DATA_W-1:0] s_axi_rdata,
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output logic [1:0] s_axi_rresp,
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output logic s_axi_rlast,
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output logic [USER_W-1:0] s_axi_ruser,
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output logic s_axi_rvalid,
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input logic s_axi_rready,
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axi4_if.master m_axi
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);
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assign m_axi.req.aw.id = s_axi_awid;
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assign m_axi.req.aw.addr = s_axi_awaddr;
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assign m_axi.req.aw.len = s_axi_awlen;
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assign m_axi.req.aw.size = s_axi_awsize;
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assign m_axi.req.aw.burst = axi_pkg::axi_burst_t'(s_axi_awburst);
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assign m_axi.req.aw.lock = s_axi_awlock;
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assign m_axi.req.aw.cache = s_axi_awcache;
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assign m_axi.req.aw.prot = s_axi_awprot;
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assign m_axi.req.aw.qos = s_axi_awqos;
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assign m_axi.req.aw.region = s_axi_awregion;
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assign m_axi.req.aw.user = s_axi_awuser;
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assign m_axi.req.aw.valid = s_axi_awvalid;
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assign s_axi_awready = m_axi.resp.aw_ready;
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assign m_axi.req.w.data = s_axi_wdata;
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assign m_axi.req.w.strb = s_axi_wstrb;
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assign m_axi.req.w.last = s_axi_wlast;
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assign m_axi.req.w.user = s_axi_wuser;
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assign m_axi.req.w.valid = s_axi_wvalid;
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assign s_axi_wready = m_axi.resp.w_ready;
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assign s_axi_bid = m_axi.resp.b.id;
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assign s_axi_bresp = m_axi.resp.b.resp;
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assign s_axi_buser = m_axi.resp.b.user;
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assign s_axi_bvalid = m_axi.resp.b.valid;
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assign m_axi.req.b_ready = s_axi_bready;
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assign m_axi.req.ar.id = s_axi_arid;
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assign m_axi.req.ar.addr = s_axi_araddr;
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assign m_axi.req.ar.len = s_axi_arlen;
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assign m_axi.req.ar.size = s_axi_arsize;
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assign m_axi.req.ar.burst = axi_pkg::axi_burst_t'(s_axi_arburst);
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assign m_axi.req.ar.lock = s_axi_arlock;
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assign m_axi.req.ar.cache = s_axi_arcache;
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assign m_axi.req.ar.prot = s_axi_arprot;
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assign m_axi.req.ar.qos = s_axi_arqos;
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assign m_axi.req.ar.region = s_axi_arregion;
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assign m_axi.req.ar.user = s_axi_aruser;
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assign m_axi.req.ar.valid = s_axi_arvalid;
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assign s_axi_arready = m_axi.resp.ar_ready;
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assign s_axi_rid = m_axi.resp.r.id;
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assign s_axi_rdata = m_axi.resp.r.data;
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assign s_axi_rresp = m_axi.resp.r.resp;
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assign s_axi_rlast = m_axi.resp.r.last;
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assign s_axi_ruser = m_axi.resp.r.user;
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assign s_axi_rvalid = m_axi.resp.r.valid;
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assign m_axi.req.r_ready = s_axi_rready;
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endmodule
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97
axi/axi4_if_to_flat.sv
Normal file
97
axi/axi4_if_to_flat.sv
Normal file
@ -0,0 +1,97 @@
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module axi4_if_to_flat #(
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parameter int unsigned ADDR_W = 32,
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parameter int unsigned DATA_W = 64,
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parameter int unsigned ID_W = 4,
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parameter int unsigned USER_W = 1
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)(
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axi4_if.slave s_axi,
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output logic [ID_W-1:0] m_axi_awid,
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output logic [ADDR_W-1:0] m_axi_awaddr,
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output logic [7:0] m_axi_awlen,
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output logic [2:0] m_axi_awsize,
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output logic [1:0] m_axi_awburst,
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output logic m_axi_awlock,
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output logic [3:0] m_axi_awcache,
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output logic [2:0] m_axi_awprot,
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output logic [3:0] m_axi_awqos,
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output logic [3:0] m_axi_awregion,
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output logic [USER_W-1:0] m_axi_awuser,
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output logic m_axi_awvalid,
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input logic m_axi_awready,
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output logic [DATA_W-1:0] m_axi_wdata,
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output logic [DATA_W/8-1:0] m_axi_wstrb,
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output logic m_axi_wlast,
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output logic [USER_W-1:0] m_axi_wuser,
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output logic m_axi_wvalid,
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input logic m_axi_wready,
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input logic [ID_W-1:0] m_axi_bid,
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input logic [1:0] m_axi_bresp,
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input logic [USER_W-1:0] m_axi_buser,
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input logic m_axi_bvalid,
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output logic m_axi_bready,
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output logic [ID_W-1:0] m_axi_arid,
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output logic [ADDR_W-1:0] m_axi_araddr,
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output logic [7:0] m_axi_arlen,
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output logic [2:0] m_axi_arsize,
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output logic [1:0] m_axi_arburst,
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output logic m_axi_arlock,
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output logic [3:0] m_axi_arcache,
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output logic [2:0] m_axi_arprot,
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output logic [3:0] m_axi_arqos,
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output logic [3:0] m_axi_arregion,
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output logic [USER_W-1:0] m_axi_aruser,
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output logic m_axi_arvalid,
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input logic m_axi_arready,
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input logic [ID_W-1:0] m_axi_rid,
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input logic [DATA_W-1:0] m_axi_rdata,
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input logic [1:0] m_axi_rresp,
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input logic m_axi_rlast,
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input logic [USER_W-1:0] m_axi_ruser,
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input logic m_axi_rvalid,
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output logic m_axi_rready
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);
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assign m_axi_awid = s_axi.req.aw.id;
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assign m_axi_awaddr = s_axi.req.aw.addr;
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assign m_axi_awlen = s_axi.req.aw.len;
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assign m_axi_awsize = s_axi.req.aw.size;
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assign m_axi_awburst = s_axi.req.aw.burst;
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assign m_axi_awlock = s_axi.req.aw.lock;
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assign m_axi_awcache = s_axi.req.aw.cache;
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assign m_axi_awprot = s_axi.req.aw.prot;
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assign m_axi_awqos = s_axi.req.aw.qos;
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assign m_axi_awregion = s_axi.req.aw.region;
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assign m_axi_awuser = s_axi.req.aw.user;
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assign m_axi_awvalid = s_axi.req.aw.valid;
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assign s_axi.resp.aw_ready = m_axi_awready;
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assign m_axi_wdata = s_axi.req.w.data;
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assign m_axi_wstrb = s_axi.req.w.strb;
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assign m_axi_wlast = s_axi.req.w.last;
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assign m_axi_wuser = s_axi.req.w.user;
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assign m_axi_wvalid = s_axi.req.w.valid;
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assign s_axi.resp.w_ready = m_axi_wready;
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assign s_axi.resp.b.id = m_axi_bid;
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assign s_axi.resp.b.resp = axi_pkg::axi_resp_t'(m_axi_bresp);
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assign s_axi.resp.b.user = m_axi_buser;
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assign s_axi.resp.b.valid= m_axi_bvalid;
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assign m_axi_bready = s_axi.req.b_ready;
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assign m_axi_arid = s_axi.req.ar.id;
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assign m_axi_araddr = s_axi.req.ar.addr;
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assign m_axi_arlen = s_axi.req.ar.len;
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assign m_axi_arsize = s_axi.req.ar.size;
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assign m_axi_arburst = s_axi.req.ar.burst;
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assign m_axi_arlock = s_axi.req.ar.lock;
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assign m_axi_arcache = s_axi.req.ar.cache;
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assign m_axi_arprot = s_axi.req.ar.prot;
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assign m_axi_arqos = s_axi.req.ar.qos;
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assign m_axi_arregion = s_axi.req.ar.region;
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assign m_axi_aruser = s_axi.req.ar.user;
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assign m_axi_arvalid = s_axi.req.ar.valid;
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assign s_axi.resp.ar_ready = m_axi_arready;
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assign s_axi.resp.r.id = m_axi_rid;
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assign s_axi.resp.r.data = m_axi_rdata;
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assign s_axi.resp.r.resp = axi_pkg::axi_resp_t'(m_axi_rresp);
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assign s_axi.resp.r.last = m_axi_rlast;
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assign s_axi.resp.r.user = m_axi_ruser;
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assign s_axi.resp.r.valid= m_axi_rvalid;
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assign m_axi_rready = s_axi.req.r_ready;
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endmodule
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58
axi/axi4l_flat_to_if.sv
Normal file
58
axi/axi4l_flat_to_if.sv
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@ -0,0 +1,58 @@
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module axi4l_flat_to_if #(
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parameter int unsigned ADDR_W = 32,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1
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)(
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input logic aclk,
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input logic aresetn,
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input logic [ADDR_W-1:0] s_axil_awaddr,
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input logic [2:0] s_axil_awprot,
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input logic [USER_W-1:0] s_axil_awuser,
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input logic s_axil_awvalid,
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output logic s_axil_awready,
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input logic [DATA_W-1:0] s_axil_wdata,
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input logic [DATA_W/8-1:0] s_axil_wstrb,
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input logic [USER_W-1:0] s_axil_wuser,
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input logic s_axil_wvalid,
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output logic s_axil_wready,
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output logic [1:0] s_axil_bresp,
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output logic [USER_W-1:0] s_axil_buser,
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output logic s_axil_bvalid,
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input logic s_axil_bready,
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input logic [ADDR_W-1:0] s_axil_araddr,
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input logic [2:0] s_axil_arprot,
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input logic [USER_W-1:0] s_axil_aruser,
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input logic s_axil_arvalid,
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output logic s_axil_arready,
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output logic [DATA_W-1:0] s_axil_rdata,
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output logic [1:0] s_axil_rresp,
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output logic [USER_W-1:0] s_axil_ruser,
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output logic s_axil_rvalid,
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input logic s_axil_rready,
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axi4l_if.master m_axil
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);
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assign m_axil.req.aw.addr = s_axil_awaddr;
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assign m_axil.req.aw.prot = s_axil_awprot;
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assign m_axil.req.aw.user = s_axil_awuser;
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assign m_axil.req.aw.valid = s_axil_awvalid;
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assign s_axil_awready = m_axil.resp.aw_ready;
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assign m_axil.req.w.data = s_axil_wdata;
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assign m_axil.req.w.strb = s_axil_wstrb;
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assign m_axil.req.w.user = s_axil_wuser;
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assign m_axil.req.w.valid = s_axil_wvalid;
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assign s_axil_wready = m_axil.resp.w_ready;
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assign s_axil_bresp = m_axil.resp.b.resp;
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assign s_axil_buser = m_axil.resp.b.user;
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assign s_axil_bvalid = m_axil.resp.b.valid;
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assign m_axil.req.b_ready = s_axil_bready;
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assign m_axil.req.ar.addr = s_axil_araddr;
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assign m_axil.req.ar.prot = s_axil_arprot;
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assign m_axil.req.ar.user = s_axil_aruser;
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assign m_axil.req.ar.valid = s_axil_arvalid;
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assign s_axil_arready = m_axil.resp.ar_ready;
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assign s_axil_rdata = m_axil.resp.r.data;
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assign s_axil_rresp = m_axil.resp.r.resp;
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assign s_axil_ruser = m_axil.resp.r.user;
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assign s_axil_rvalid = m_axil.resp.r.valid;
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assign m_axil.req.r_ready = s_axil_rready;
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endmodule
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56
axi/axi4l_if_to_flat.sv
Normal file
56
axi/axi4l_if_to_flat.sv
Normal file
@ -0,0 +1,56 @@
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module axi4l_if_to_flat #(
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parameter int unsigned ADDR_W = 32,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1
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)(
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axi4l_if.slave s_axil,
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output logic [ADDR_W-1:0] m_axil_awaddr,
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output logic [2:0] m_axil_awprot,
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output logic [USER_W-1:0] m_axil_awuser,
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output logic m_axil_awvalid,
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input logic m_axil_awready,
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output logic [DATA_W-1:0] m_axil_wdata,
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output logic [DATA_W/8-1:0] m_axil_wstrb,
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output logic [USER_W-1:0] m_axil_wuser,
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output logic m_axil_wvalid,
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input logic m_axil_wready,
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input logic [1:0] m_axil_bresp,
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input logic [USER_W-1:0] m_axil_buser,
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input logic m_axil_bvalid,
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output logic m_axil_bready,
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output logic [ADDR_W-1:0] m_axil_araddr,
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output logic [2:0] m_axil_arprot,
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output logic [USER_W-1:0] m_axil_aruser,
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output logic m_axil_arvalid,
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input logic m_axil_arready,
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input logic [DATA_W-1:0] m_axil_rdata,
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input logic [1:0] m_axil_rresp,
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input logic [USER_W-1:0] m_axil_ruser,
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input logic m_axil_rvalid,
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output logic m_axil_rready
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);
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assign m_axil_awaddr = s_axil.req.aw.addr;
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assign m_axil_awprot = s_axil.req.aw.prot;
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assign m_axil_awuser = s_axil.req.aw.user;
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assign m_axil_awvalid = s_axil.req.aw.valid;
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assign s_axil.resp.aw_ready = m_axil_awready;
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assign m_axil_wdata = s_axil.req.w.data;
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assign m_axil_wstrb = s_axil.req.w.strb;
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assign m_axil_wuser = s_axil.req.w.user;
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assign m_axil_wvalid = s_axil.req.w.valid;
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assign s_axil.resp.w_ready = m_axil_wready;
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assign s_axil.resp.b.resp = axi_pkg::axi_resp_t'(m_axil_bresp);
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assign s_axil.resp.b.user = m_axil_buser;
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assign s_axil.resp.b.valid = m_axil_bvalid;
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assign m_axil_bready = s_axil.req.b_ready;
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assign m_axil_araddr = s_axil.req.ar.addr;
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assign m_axil_arprot = s_axil.req.ar.prot;
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assign m_axil_aruser = s_axil.req.ar.user;
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assign m_axil_arvalid = s_axil.req.ar.valid;
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assign s_axil.resp.ar_ready = m_axil_arready;
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assign s_axil.resp.r.data = m_axil_rdata;
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assign s_axil.resp.r.resp = axi_pkg::axi_resp_t'(m_axil_rresp);
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assign s_axil.resp.r.user = m_axil_ruser;
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assign s_axil.resp.r.valid = m_axil_rvalid;
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assign m_axil_rready = s_axil.req.r_ready;
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endmodule
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189
axi/axi4l_reg_map.sv
Normal file
189
axi/axi4l_reg_map.sv
Normal file
@ -0,0 +1,189 @@
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module axi4l_reg_map #(
|
||||
parameter int unsigned ADDR_W = 16,
|
||||
parameter int unsigned DATA_W = 32,
|
||||
parameter int unsigned USER_W = 1,
|
||||
parameter int unsigned N_REGS = 4,
|
||||
|
||||
parameter logic [N_REGS-1:0][31:0][2:0] REG_MODE = '{default:'0},
|
||||
parameter logic [N_REGS-1:0][31:0] REG_RST = '{default:'0}
|
||||
)(
|
||||
input logic clk,
|
||||
input logic rst_n,
|
||||
axi4l_if.slave s_axil,
|
||||
|
||||
input logic [N_REGS-1:0][31:0] reg_i,
|
||||
output logic [N_REGS-1:0][31:0] reg_o
|
||||
);
|
||||
import axi_pkg::*;
|
||||
|
||||
typedef enum logic [2:0] {
|
||||
REG_BIT_RSVD = 3'd0,
|
||||
REG_BIT_RO = 3'd1,
|
||||
REG_BIT_RW = 3'd2,
|
||||
REG_BIT_W1S = 3'd3,
|
||||
REG_BIT_W1C = 3'd4
|
||||
} reg_bit_mode_t;
|
||||
|
||||
localparam int unsigned STRB_W = DATA_W/8;
|
||||
localparam int unsigned ADDR_LSB = $clog2(DATA_W/8);
|
||||
localparam int unsigned REG_INDEX_W = (N_REGS <= 1) ? 1 : $clog2(N_REGS);
|
||||
|
||||
logic [ADDR_W-1:0] awaddr_q;
|
||||
logic aw_seen_q;
|
||||
logic [DATA_W-1:0] wdata_q;
|
||||
logic [STRB_W-1:0] wstrb_q;
|
||||
logic w_seen_q;
|
||||
|
||||
logic bvalid_q;
|
||||
logic [1:0] bresp_q;
|
||||
|
||||
logic rvalid_q;
|
||||
logic [1:0] rresp_q;
|
||||
logic [DATA_W-1:0] rdata_q;
|
||||
|
||||
logic [REG_INDEX_W-1:0] wr_idx;
|
||||
logic [REG_INDEX_W-1:0] rd_idx;
|
||||
logic wr_addr_valid;
|
||||
logic rd_addr_valid;
|
||||
|
||||
integer b;
|
||||
logic [31:0] wr_mask;
|
||||
logic [31:0] wr_data32;
|
||||
logic [31:0] rw_cur;
|
||||
logic [31:0] rw_new;
|
||||
logic [31:0] rd_word;
|
||||
|
||||
always_comb begin
|
||||
wr_idx = '0;
|
||||
rd_idx = '0;
|
||||
wr_addr_valid = 1'b0;
|
||||
rd_addr_valid = 1'b0;
|
||||
|
||||
if (awaddr_q[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W] < N_REGS) begin
|
||||
wr_idx = awaddr_q[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W];
|
||||
wr_addr_valid = 1'b1;
|
||||
end
|
||||
|
||||
if (s_axil.req.ar.addr[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W] < N_REGS) begin
|
||||
rd_idx = s_axil.req.ar.addr[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W];
|
||||
rd_addr_valid = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
wr_mask = '0;
|
||||
for (int k = 0; k < STRB_W; k++) begin
|
||||
wr_mask[k*8 +: 8] = {8{wstrb_q[k]}};
|
||||
end
|
||||
wr_data32 = wdata_q[31:0];
|
||||
end
|
||||
|
||||
assign s_axil.resp.aw_ready = !aw_seen_q && !bvalid_q;
|
||||
assign s_axil.resp.w_ready = !w_seen_q && !bvalid_q;
|
||||
assign s_axil.resp.ar_ready = !rvalid_q;
|
||||
|
||||
assign s_axil.resp.b.valid = bvalid_q;
|
||||
assign s_axil.resp.b.resp = axi_resp_t'(bresp_q);
|
||||
assign s_axil.resp.b.user = '0;
|
||||
|
||||
assign s_axil.resp.r.valid = rvalid_q;
|
||||
assign s_axil.resp.r.resp = axi_resp_t'(rresp_q);
|
||||
assign s_axil.resp.r.data = rdata_q;
|
||||
assign s_axil.resp.r.user = '0;
|
||||
|
||||
always_ff @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
awaddr_q <= '0;
|
||||
aw_seen_q <= 1'b0;
|
||||
wdata_q <= '0;
|
||||
wstrb_q <= '0;
|
||||
w_seen_q <= 1'b0;
|
||||
bvalid_q <= 1'b0;
|
||||
bresp_q <= 2'b00;
|
||||
rvalid_q <= 1'b0;
|
||||
rresp_q <= 2'b00;
|
||||
rdata_q <= '0;
|
||||
reg_o <= REG_RST;
|
||||
end else begin
|
||||
for (int r = 0; r < N_REGS; r++) begin
|
||||
for (int bit_idx = 0; bit_idx < 32; bit_idx++) begin
|
||||
if (reg_bit_mode_t'(REG_MODE[r][bit_idx]) == REG_BIT_W1S)
|
||||
reg_o[r][bit_idx] <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (s_axil.req.aw.valid && s_axil.resp.aw_ready) begin
|
||||
awaddr_q <= s_axil.req.aw.addr;
|
||||
aw_seen_q <= 1'b1;
|
||||
end
|
||||
|
||||
if (s_axil.req.w.valid && s_axil.resp.w_ready) begin
|
||||
wdata_q <= s_axil.req.w.data;
|
||||
wstrb_q <= s_axil.req.w.strb;
|
||||
w_seen_q <= 1'b1;
|
||||
end
|
||||
|
||||
if (aw_seen_q && w_seen_q && !bvalid_q) begin
|
||||
bvalid_q <= 1'b1;
|
||||
bresp_q <= 2'b00;
|
||||
|
||||
if (!wr_addr_valid) begin
|
||||
bresp_q <= 2'b10;
|
||||
end else begin
|
||||
rw_cur = reg_o[wr_idx];
|
||||
rw_new = rw_cur;
|
||||
|
||||
for (b = 0; b < 32; b = b + 1) begin
|
||||
if (wr_mask[b]) begin
|
||||
unique case (reg_bit_mode_t'(REG_MODE[wr_idx][b]))
|
||||
REG_BIT_RSVD: begin end
|
||||
REG_BIT_RO : begin bresp_q <= 2'b10; end
|
||||
REG_BIT_RW : rw_new[b] = wr_data32[b];
|
||||
REG_BIT_W1S : if (wr_data32[b]) rw_new[b] = 1'b1;
|
||||
REG_BIT_W1C : if (wr_data32[b]) rw_new[b] = 1'b0;
|
||||
default : begin end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
reg_o[wr_idx] <= rw_new;
|
||||
end
|
||||
|
||||
aw_seen_q <= 1'b0;
|
||||
w_seen_q <= 1'b0;
|
||||
end
|
||||
|
||||
if (bvalid_q && s_axil.req.b_ready) begin
|
||||
bvalid_q <= 1'b0;
|
||||
end
|
||||
|
||||
if (s_axil.req.ar.valid && s_axil.resp.ar_ready) begin
|
||||
rvalid_q <= 1'b1;
|
||||
rresp_q <= 2'b00;
|
||||
rd_word = '0;
|
||||
|
||||
if (!rd_addr_valid) begin
|
||||
rresp_q <= 2'b10;
|
||||
end else begin
|
||||
for (b = 0; b < 32; b = b + 1) begin
|
||||
unique case (reg_bit_mode_t'(REG_MODE[rd_idx][b]))
|
||||
REG_BIT_RSVD: rd_word[b] = 1'b0;
|
||||
REG_BIT_RO : rd_word[b] = reg_i[rd_idx][b];
|
||||
REG_BIT_RW : rd_word[b] = reg_o[rd_idx][b];
|
||||
REG_BIT_W1S : rd_word[b] = 1'b0;
|
||||
REG_BIT_W1C : rd_word[b] = reg_o[rd_idx][b];
|
||||
default : rd_word[b] = 1'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
rdata_q <= rd_word;
|
||||
end
|
||||
|
||||
if (rvalid_q && s_axil.req.r_ready) begin
|
||||
rvalid_q <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
59
axi/axi4l_to_axi4.sv
Normal file
59
axi/axi4l_to_axi4.sv
Normal file
@ -0,0 +1,59 @@
|
||||
module axi4l_to_axi4 #(
|
||||
parameter int unsigned ADDR_W = 32,
|
||||
parameter int unsigned DATA_W = 32,
|
||||
parameter int unsigned ID_W = 4,
|
||||
parameter int unsigned USER_W = 1,
|
||||
parameter logic [ID_W-1:0] AXI_ID_CONST = '0,
|
||||
parameter logic [3:0] AXI_CACHE_CONST = 4'b0000,
|
||||
parameter logic [3:0] AXI_QOS_CONST = 4'b0000,
|
||||
parameter logic [3:0] AXI_REGION_CONST = 4'b0000
|
||||
)(
|
||||
axi4l_if.slave s_axil,
|
||||
axi4_if.master m_axi
|
||||
);
|
||||
assign m_axi.req.aw.id = AXI_ID_CONST;
|
||||
assign m_axi.req.aw.addr = s_axil.req.aw.addr;
|
||||
assign m_axi.req.aw.len = 8'd0;
|
||||
assign m_axi.req.aw.size = axi_pkg::axi_size_from_bytes(DATA_W/8);
|
||||
assign m_axi.req.aw.burst = axi_pkg::AXI_BURST_INCR;
|
||||
assign m_axi.req.aw.lock = 1'b0;
|
||||
assign m_axi.req.aw.cache = AXI_CACHE_CONST;
|
||||
assign m_axi.req.aw.prot = s_axil.req.aw.prot;
|
||||
assign m_axi.req.aw.qos = AXI_QOS_CONST;
|
||||
assign m_axi.req.aw.region = AXI_REGION_CONST;
|
||||
assign m_axi.req.aw.user = s_axil.req.aw.user;
|
||||
assign m_axi.req.aw.valid = s_axil.req.aw.valid;
|
||||
assign s_axil.resp.aw_ready = m_axi.resp.aw_ready;
|
||||
|
||||
assign m_axi.req.w.data = s_axil.req.w.data;
|
||||
assign m_axi.req.w.strb = s_axil.req.w.strb;
|
||||
assign m_axi.req.w.last = 1'b1;
|
||||
assign m_axi.req.w.user = s_axil.req.w.user;
|
||||
assign m_axi.req.w.valid = s_axil.req.w.valid;
|
||||
assign s_axil.resp.w_ready = m_axi.resp.w_ready;
|
||||
|
||||
assign s_axil.resp.b.resp = m_axi.resp.b.resp;
|
||||
assign s_axil.resp.b.user = m_axi.resp.b.user;
|
||||
assign s_axil.resp.b.valid = m_axi.resp.b.valid;
|
||||
assign m_axi.req.b_ready = s_axil.req.b_ready;
|
||||
|
||||
assign m_axi.req.ar.id = AXI_ID_CONST;
|
||||
assign m_axi.req.ar.addr = s_axil.req.ar.addr;
|
||||
assign m_axi.req.ar.len = 8'd0;
|
||||
assign m_axi.req.ar.size = axi_pkg::axi_size_from_bytes(DATA_W/8);
|
||||
assign m_axi.req.ar.burst = axi_pkg::AXI_BURST_INCR;
|
||||
assign m_axi.req.ar.lock = 1'b0;
|
||||
assign m_axi.req.ar.cache = AXI_CACHE_CONST;
|
||||
assign m_axi.req.ar.prot = s_axil.req.ar.prot;
|
||||
assign m_axi.req.ar.qos = AXI_QOS_CONST;
|
||||
assign m_axi.req.ar.region = AXI_REGION_CONST;
|
||||
assign m_axi.req.ar.user = s_axil.req.ar.user;
|
||||
assign m_axi.req.ar.valid = s_axil.req.ar.valid;
|
||||
assign s_axil.resp.ar_ready = m_axi.resp.ar_ready;
|
||||
|
||||
assign s_axil.resp.r.data = m_axi.resp.r.data;
|
||||
assign s_axil.resp.r.resp = m_axi.resp.r.resp;
|
||||
assign s_axil.resp.r.user = m_axi.resp.r.user;
|
||||
assign s_axil.resp.r.valid = m_axi.resp.r.valid;
|
||||
assign m_axi.req.r_ready = s_axil.req.r_ready;
|
||||
endmodule
|
||||
654
axi/axi_crossbar_core_wrapper.sv
Normal file
654
axi/axi_crossbar_core_wrapper.sv
Normal file
@ -0,0 +1,654 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2020 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 3x3 crossbar (wrapper)
|
||||
*/
|
||||
module axi_crossbar_core_wrapper #
|
||||
(
|
||||
// Width of data bus in bits
|
||||
parameter DATA_WIDTH = 32,
|
||||
// Width of address bus in bits
|
||||
parameter ADDR_WIDTH = 32,
|
||||
// Width of wstrb (width of data bus in words)
|
||||
parameter STRB_WIDTH = (DATA_WIDTH/8),
|
||||
// Input ID field width (from AXI masters)
|
||||
parameter S_ID_WIDTH = 8,
|
||||
// Output ID field width (towards AXI slaves)
|
||||
// Additional bits required for response routing
|
||||
parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),
|
||||
// Propagate awuser signal
|
||||
parameter AWUSER_ENABLE = 0,
|
||||
// Width of awuser signal
|
||||
parameter AWUSER_WIDTH = 1,
|
||||
// Propagate wuser signal
|
||||
parameter WUSER_ENABLE = 0,
|
||||
// Width of wuser signal
|
||||
parameter WUSER_WIDTH = 1,
|
||||
// Propagate buser signal
|
||||
parameter BUSER_ENABLE = 0,
|
||||
// Width of buser signal
|
||||
parameter BUSER_WIDTH = 1,
|
||||
// Propagate aruser signal
|
||||
parameter ARUSER_ENABLE = 0,
|
||||
// Width of aruser signal
|
||||
parameter ARUSER_WIDTH = 1,
|
||||
// Propagate ruser signal
|
||||
parameter RUSER_ENABLE = 0,
|
||||
// Width of ruser signal
|
||||
parameter RUSER_WIDTH = 1,
|
||||
// Number of concurrent unique IDs
|
||||
parameter S00_THREADS = 2,
|
||||
// Number of concurrent operations
|
||||
parameter S00_ACCEPT = 16,
|
||||
// Number of concurrent unique IDs
|
||||
parameter S01_THREADS = 2,
|
||||
// Number of concurrent operations
|
||||
parameter S01_ACCEPT = 16,
|
||||
// Number of concurrent unique IDs
|
||||
parameter S02_THREADS = 2,
|
||||
// Number of concurrent operations
|
||||
parameter S02_ACCEPT = 16,
|
||||
// Number of regions per master interface
|
||||
parameter M_REGIONS = 1,
|
||||
// Master interface base addresses
|
||||
// M_REGIONS concatenated fields of ADDR_WIDTH bits
|
||||
parameter M00_BASE_ADDR = 0,
|
||||
// Master interface address widths
|
||||
// M_REGIONS concatenated fields of 32 bits
|
||||
parameter M00_ADDR_WIDTH = {M_REGIONS{32'd24}},
|
||||
// Read connections between interfaces
|
||||
// S_COUNT bits
|
||||
parameter M00_CONNECT_READ = 3'b111,
|
||||
// Write connections between interfaces
|
||||
// S_COUNT bits
|
||||
parameter M00_CONNECT_WRITE = 3'b111,
|
||||
// Number of concurrent operations for each master interface
|
||||
parameter M00_ISSUE = 4,
|
||||
// Secure master (fail operations based on awprot/arprot)
|
||||
parameter M00_SECURE = 0,
|
||||
// Master interface base addresses
|
||||
// M_REGIONS concatenated fields of ADDR_WIDTH bits
|
||||
parameter M01_BASE_ADDR = 0,
|
||||
// Master interface address widths
|
||||
// M_REGIONS concatenated fields of 32 bits
|
||||
parameter M01_ADDR_WIDTH = {M_REGIONS{32'd24}},
|
||||
// Read connections between interfaces
|
||||
// S_COUNT bits
|
||||
parameter M01_CONNECT_READ = 3'b111,
|
||||
// Write connections between interfaces
|
||||
// S_COUNT bits
|
||||
parameter M01_CONNECT_WRITE = 3'b111,
|
||||
// Number of concurrent operations for each master interface
|
||||
parameter M01_ISSUE = 4,
|
||||
// Secure master (fail operations based on awprot/arprot)
|
||||
parameter M01_SECURE = 0,
|
||||
// Master interface base addresses
|
||||
// M_REGIONS concatenated fields of ADDR_WIDTH bits
|
||||
parameter M02_BASE_ADDR = 0,
|
||||
// Master interface address widths
|
||||
// M_REGIONS concatenated fields of 32 bits
|
||||
parameter M02_ADDR_WIDTH = {M_REGIONS{32'd24}},
|
||||
// Read connections between interfaces
|
||||
// S_COUNT bits
|
||||
parameter M02_CONNECT_READ = 3'b111,
|
||||
// Write connections between interfaces
|
||||
// S_COUNT bits
|
||||
parameter M02_CONNECT_WRITE = 3'b111,
|
||||
// Number of concurrent operations for each master interface
|
||||
parameter M02_ISSUE = 4,
|
||||
// Secure master (fail operations based on awprot/arprot)
|
||||
parameter M02_SECURE = 0,
|
||||
// Slave interface AW channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S00_AW_REG_TYPE = 0,
|
||||
// Slave interface W channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S00_W_REG_TYPE = 0,
|
||||
// Slave interface B channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S00_B_REG_TYPE = 1,
|
||||
// Slave interface AR channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S00_AR_REG_TYPE = 0,
|
||||
// Slave interface R channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S00_R_REG_TYPE = 2,
|
||||
// Slave interface AW channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S01_AW_REG_TYPE = 0,
|
||||
// Slave interface W channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S01_W_REG_TYPE = 0,
|
||||
// Slave interface B channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S01_B_REG_TYPE = 1,
|
||||
// Slave interface AR channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S01_AR_REG_TYPE = 0,
|
||||
// Slave interface R channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S01_R_REG_TYPE = 2,
|
||||
// Slave interface AW channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S02_AW_REG_TYPE = 0,
|
||||
// Slave interface W channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S02_W_REG_TYPE = 0,
|
||||
// Slave interface B channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S02_B_REG_TYPE = 1,
|
||||
// Slave interface AR channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S02_AR_REG_TYPE = 0,
|
||||
// Slave interface R channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S02_R_REG_TYPE = 2,
|
||||
// Master interface AW channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M00_AW_REG_TYPE = 1,
|
||||
// Master interface W channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M00_W_REG_TYPE = 2,
|
||||
// Master interface B channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M00_B_REG_TYPE = 0,
|
||||
// Master interface AR channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M00_AR_REG_TYPE = 1,
|
||||
// Master interface R channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M00_R_REG_TYPE = 0,
|
||||
// Master interface AW channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M01_AW_REG_TYPE = 1,
|
||||
// Master interface W channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M01_W_REG_TYPE = 2,
|
||||
// Master interface B channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M01_B_REG_TYPE = 0,
|
||||
// Master interface AR channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M01_AR_REG_TYPE = 1,
|
||||
// Master interface R channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M01_R_REG_TYPE = 0,
|
||||
// Master interface AW channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M02_AW_REG_TYPE = 1,
|
||||
// Master interface W channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M02_W_REG_TYPE = 2,
|
||||
// Master interface B channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M02_B_REG_TYPE = 0,
|
||||
// Master interface AR channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M02_AR_REG_TYPE = 1,
|
||||
// Master interface R channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M02_R_REG_TYPE = 0
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* AXI slave interface
|
||||
*/
|
||||
input wire [S_ID_WIDTH-1:0] s00_axi_awid,
|
||||
input wire [ADDR_WIDTH-1:0] s00_axi_awaddr,
|
||||
input wire [7:0] s00_axi_awlen,
|
||||
input wire [2:0] s00_axi_awsize,
|
||||
input wire [1:0] s00_axi_awburst,
|
||||
input wire s00_axi_awlock,
|
||||
input wire [3:0] s00_axi_awcache,
|
||||
input wire [2:0] s00_axi_awprot,
|
||||
input wire [3:0] s00_axi_awqos,
|
||||
input wire [AWUSER_WIDTH-1:0] s00_axi_awuser,
|
||||
input wire s00_axi_awvalid,
|
||||
output wire s00_axi_awready,
|
||||
input wire [DATA_WIDTH-1:0] s00_axi_wdata,
|
||||
input wire [STRB_WIDTH-1:0] s00_axi_wstrb,
|
||||
input wire s00_axi_wlast,
|
||||
input wire [WUSER_WIDTH-1:0] s00_axi_wuser,
|
||||
input wire s00_axi_wvalid,
|
||||
output wire s00_axi_wready,
|
||||
output wire [S_ID_WIDTH-1:0] s00_axi_bid,
|
||||
output wire [1:0] s00_axi_bresp,
|
||||
output wire [BUSER_WIDTH-1:0] s00_axi_buser,
|
||||
output wire s00_axi_bvalid,
|
||||
input wire s00_axi_bready,
|
||||
input wire [S_ID_WIDTH-1:0] s00_axi_arid,
|
||||
input wire [ADDR_WIDTH-1:0] s00_axi_araddr,
|
||||
input wire [7:0] s00_axi_arlen,
|
||||
input wire [2:0] s00_axi_arsize,
|
||||
input wire [1:0] s00_axi_arburst,
|
||||
input wire s00_axi_arlock,
|
||||
input wire [3:0] s00_axi_arcache,
|
||||
input wire [2:0] s00_axi_arprot,
|
||||
input wire [3:0] s00_axi_arqos,
|
||||
input wire [ARUSER_WIDTH-1:0] s00_axi_aruser,
|
||||
input wire s00_axi_arvalid,
|
||||
output wire s00_axi_arready,
|
||||
output wire [S_ID_WIDTH-1:0] s00_axi_rid,
|
||||
output wire [DATA_WIDTH-1:0] s00_axi_rdata,
|
||||
output wire [1:0] s00_axi_rresp,
|
||||
output wire s00_axi_rlast,
|
||||
output wire [RUSER_WIDTH-1:0] s00_axi_ruser,
|
||||
output wire s00_axi_rvalid,
|
||||
input wire s00_axi_rready,
|
||||
|
||||
input wire [S_ID_WIDTH-1:0] s01_axi_awid,
|
||||
input wire [ADDR_WIDTH-1:0] s01_axi_awaddr,
|
||||
input wire [7:0] s01_axi_awlen,
|
||||
input wire [2:0] s01_axi_awsize,
|
||||
input wire [1:0] s01_axi_awburst,
|
||||
input wire s01_axi_awlock,
|
||||
input wire [3:0] s01_axi_awcache,
|
||||
input wire [2:0] s01_axi_awprot,
|
||||
input wire [3:0] s01_axi_awqos,
|
||||
input wire [AWUSER_WIDTH-1:0] s01_axi_awuser,
|
||||
input wire s01_axi_awvalid,
|
||||
output wire s01_axi_awready,
|
||||
input wire [DATA_WIDTH-1:0] s01_axi_wdata,
|
||||
input wire [STRB_WIDTH-1:0] s01_axi_wstrb,
|
||||
input wire s01_axi_wlast,
|
||||
input wire [WUSER_WIDTH-1:0] s01_axi_wuser,
|
||||
input wire s01_axi_wvalid,
|
||||
output wire s01_axi_wready,
|
||||
output wire [S_ID_WIDTH-1:0] s01_axi_bid,
|
||||
output wire [1:0] s01_axi_bresp,
|
||||
output wire [BUSER_WIDTH-1:0] s01_axi_buser,
|
||||
output wire s01_axi_bvalid,
|
||||
input wire s01_axi_bready,
|
||||
input wire [S_ID_WIDTH-1:0] s01_axi_arid,
|
||||
input wire [ADDR_WIDTH-1:0] s01_axi_araddr,
|
||||
input wire [7:0] s01_axi_arlen,
|
||||
input wire [2:0] s01_axi_arsize,
|
||||
input wire [1:0] s01_axi_arburst,
|
||||
input wire s01_axi_arlock,
|
||||
input wire [3:0] s01_axi_arcache,
|
||||
input wire [2:0] s01_axi_arprot,
|
||||
input wire [3:0] s01_axi_arqos,
|
||||
input wire [ARUSER_WIDTH-1:0] s01_axi_aruser,
|
||||
input wire s01_axi_arvalid,
|
||||
output wire s01_axi_arready,
|
||||
output wire [S_ID_WIDTH-1:0] s01_axi_rid,
|
||||
output wire [DATA_WIDTH-1:0] s01_axi_rdata,
|
||||
output wire [1:0] s01_axi_rresp,
|
||||
output wire s01_axi_rlast,
|
||||
output wire [RUSER_WIDTH-1:0] s01_axi_ruser,
|
||||
output wire s01_axi_rvalid,
|
||||
input wire s01_axi_rready,
|
||||
|
||||
input wire [S_ID_WIDTH-1:0] s02_axi_awid,
|
||||
input wire [ADDR_WIDTH-1:0] s02_axi_awaddr,
|
||||
input wire [7:0] s02_axi_awlen,
|
||||
input wire [2:0] s02_axi_awsize,
|
||||
input wire [1:0] s02_axi_awburst,
|
||||
input wire s02_axi_awlock,
|
||||
input wire [3:0] s02_axi_awcache,
|
||||
input wire [2:0] s02_axi_awprot,
|
||||
input wire [3:0] s02_axi_awqos,
|
||||
input wire [AWUSER_WIDTH-1:0] s02_axi_awuser,
|
||||
input wire s02_axi_awvalid,
|
||||
output wire s02_axi_awready,
|
||||
input wire [DATA_WIDTH-1:0] s02_axi_wdata,
|
||||
input wire [STRB_WIDTH-1:0] s02_axi_wstrb,
|
||||
input wire s02_axi_wlast,
|
||||
input wire [WUSER_WIDTH-1:0] s02_axi_wuser,
|
||||
input wire s02_axi_wvalid,
|
||||
output wire s02_axi_wready,
|
||||
output wire [S_ID_WIDTH-1:0] s02_axi_bid,
|
||||
output wire [1:0] s02_axi_bresp,
|
||||
output wire [BUSER_WIDTH-1:0] s02_axi_buser,
|
||||
output wire s02_axi_bvalid,
|
||||
input wire s02_axi_bready,
|
||||
input wire [S_ID_WIDTH-1:0] s02_axi_arid,
|
||||
input wire [ADDR_WIDTH-1:0] s02_axi_araddr,
|
||||
input wire [7:0] s02_axi_arlen,
|
||||
input wire [2:0] s02_axi_arsize,
|
||||
input wire [1:0] s02_axi_arburst,
|
||||
input wire s02_axi_arlock,
|
||||
input wire [3:0] s02_axi_arcache,
|
||||
input wire [2:0] s02_axi_arprot,
|
||||
input wire [3:0] s02_axi_arqos,
|
||||
input wire [ARUSER_WIDTH-1:0] s02_axi_aruser,
|
||||
input wire s02_axi_arvalid,
|
||||
output wire s02_axi_arready,
|
||||
output wire [S_ID_WIDTH-1:0] s02_axi_rid,
|
||||
output wire [DATA_WIDTH-1:0] s02_axi_rdata,
|
||||
output wire [1:0] s02_axi_rresp,
|
||||
output wire s02_axi_rlast,
|
||||
output wire [RUSER_WIDTH-1:0] s02_axi_ruser,
|
||||
output wire s02_axi_rvalid,
|
||||
input wire s02_axi_rready,
|
||||
|
||||
/*
|
||||
* AXI master interface
|
||||
*/
|
||||
output wire [M_ID_WIDTH-1:0] m00_axi_awid,
|
||||
output wire [ADDR_WIDTH-1:0] m00_axi_awaddr,
|
||||
output wire [7:0] m00_axi_awlen,
|
||||
output wire [2:0] m00_axi_awsize,
|
||||
output wire [1:0] m00_axi_awburst,
|
||||
output wire m00_axi_awlock,
|
||||
output wire [3:0] m00_axi_awcache,
|
||||
output wire [2:0] m00_axi_awprot,
|
||||
output wire [3:0] m00_axi_awqos,
|
||||
output wire [3:0] m00_axi_awregion,
|
||||
output wire [AWUSER_WIDTH-1:0] m00_axi_awuser,
|
||||
output wire m00_axi_awvalid,
|
||||
input wire m00_axi_awready,
|
||||
output wire [DATA_WIDTH-1:0] m00_axi_wdata,
|
||||
output wire [STRB_WIDTH-1:0] m00_axi_wstrb,
|
||||
output wire m00_axi_wlast,
|
||||
output wire [WUSER_WIDTH-1:0] m00_axi_wuser,
|
||||
output wire m00_axi_wvalid,
|
||||
input wire m00_axi_wready,
|
||||
input wire [M_ID_WIDTH-1:0] m00_axi_bid,
|
||||
input wire [1:0] m00_axi_bresp,
|
||||
input wire [BUSER_WIDTH-1:0] m00_axi_buser,
|
||||
input wire m00_axi_bvalid,
|
||||
output wire m00_axi_bready,
|
||||
output wire [M_ID_WIDTH-1:0] m00_axi_arid,
|
||||
output wire [ADDR_WIDTH-1:0] m00_axi_araddr,
|
||||
output wire [7:0] m00_axi_arlen,
|
||||
output wire [2:0] m00_axi_arsize,
|
||||
output wire [1:0] m00_axi_arburst,
|
||||
output wire m00_axi_arlock,
|
||||
output wire [3:0] m00_axi_arcache,
|
||||
output wire [2:0] m00_axi_arprot,
|
||||
output wire [3:0] m00_axi_arqos,
|
||||
output wire [3:0] m00_axi_arregion,
|
||||
output wire [ARUSER_WIDTH-1:0] m00_axi_aruser,
|
||||
output wire m00_axi_arvalid,
|
||||
input wire m00_axi_arready,
|
||||
input wire [M_ID_WIDTH-1:0] m00_axi_rid,
|
||||
input wire [DATA_WIDTH-1:0] m00_axi_rdata,
|
||||
input wire [1:0] m00_axi_rresp,
|
||||
input wire m00_axi_rlast,
|
||||
input wire [RUSER_WIDTH-1:0] m00_axi_ruser,
|
||||
input wire m00_axi_rvalid,
|
||||
output wire m00_axi_rready,
|
||||
|
||||
output wire [M_ID_WIDTH-1:0] m01_axi_awid,
|
||||
output wire [ADDR_WIDTH-1:0] m01_axi_awaddr,
|
||||
output wire [7:0] m01_axi_awlen,
|
||||
output wire [2:0] m01_axi_awsize,
|
||||
output wire [1:0] m01_axi_awburst,
|
||||
output wire m01_axi_awlock,
|
||||
output wire [3:0] m01_axi_awcache,
|
||||
output wire [2:0] m01_axi_awprot,
|
||||
output wire [3:0] m01_axi_awqos,
|
||||
output wire [3:0] m01_axi_awregion,
|
||||
output wire [AWUSER_WIDTH-1:0] m01_axi_awuser,
|
||||
output wire m01_axi_awvalid,
|
||||
input wire m01_axi_awready,
|
||||
output wire [DATA_WIDTH-1:0] m01_axi_wdata,
|
||||
output wire [STRB_WIDTH-1:0] m01_axi_wstrb,
|
||||
output wire m01_axi_wlast,
|
||||
output wire [WUSER_WIDTH-1:0] m01_axi_wuser,
|
||||
output wire m01_axi_wvalid,
|
||||
input wire m01_axi_wready,
|
||||
input wire [M_ID_WIDTH-1:0] m01_axi_bid,
|
||||
input wire [1:0] m01_axi_bresp,
|
||||
input wire [BUSER_WIDTH-1:0] m01_axi_buser,
|
||||
input wire m01_axi_bvalid,
|
||||
output wire m01_axi_bready,
|
||||
output wire [M_ID_WIDTH-1:0] m01_axi_arid,
|
||||
output wire [ADDR_WIDTH-1:0] m01_axi_araddr,
|
||||
output wire [7:0] m01_axi_arlen,
|
||||
output wire [2:0] m01_axi_arsize,
|
||||
output wire [1:0] m01_axi_arburst,
|
||||
output wire m01_axi_arlock,
|
||||
output wire [3:0] m01_axi_arcache,
|
||||
output wire [2:0] m01_axi_arprot,
|
||||
output wire [3:0] m01_axi_arqos,
|
||||
output wire [3:0] m01_axi_arregion,
|
||||
output wire [ARUSER_WIDTH-1:0] m01_axi_aruser,
|
||||
output wire m01_axi_arvalid,
|
||||
input wire m01_axi_arready,
|
||||
input wire [M_ID_WIDTH-1:0] m01_axi_rid,
|
||||
input wire [DATA_WIDTH-1:0] m01_axi_rdata,
|
||||
input wire [1:0] m01_axi_rresp,
|
||||
input wire m01_axi_rlast,
|
||||
input wire [RUSER_WIDTH-1:0] m01_axi_ruser,
|
||||
input wire m01_axi_rvalid,
|
||||
output wire m01_axi_rready,
|
||||
|
||||
output wire [M_ID_WIDTH-1:0] m02_axi_awid,
|
||||
output wire [ADDR_WIDTH-1:0] m02_axi_awaddr,
|
||||
output wire [7:0] m02_axi_awlen,
|
||||
output wire [2:0] m02_axi_awsize,
|
||||
output wire [1:0] m02_axi_awburst,
|
||||
output wire m02_axi_awlock,
|
||||
output wire [3:0] m02_axi_awcache,
|
||||
output wire [2:0] m02_axi_awprot,
|
||||
output wire [3:0] m02_axi_awqos,
|
||||
output wire [3:0] m02_axi_awregion,
|
||||
output wire [AWUSER_WIDTH-1:0] m02_axi_awuser,
|
||||
output wire m02_axi_awvalid,
|
||||
input wire m02_axi_awready,
|
||||
output wire [DATA_WIDTH-1:0] m02_axi_wdata,
|
||||
output wire [STRB_WIDTH-1:0] m02_axi_wstrb,
|
||||
output wire m02_axi_wlast,
|
||||
output wire [WUSER_WIDTH-1:0] m02_axi_wuser,
|
||||
output wire m02_axi_wvalid,
|
||||
input wire m02_axi_wready,
|
||||
input wire [M_ID_WIDTH-1:0] m02_axi_bid,
|
||||
input wire [1:0] m02_axi_bresp,
|
||||
input wire [BUSER_WIDTH-1:0] m02_axi_buser,
|
||||
input wire m02_axi_bvalid,
|
||||
output wire m02_axi_bready,
|
||||
output wire [M_ID_WIDTH-1:0] m02_axi_arid,
|
||||
output wire [ADDR_WIDTH-1:0] m02_axi_araddr,
|
||||
output wire [7:0] m02_axi_arlen,
|
||||
output wire [2:0] m02_axi_arsize,
|
||||
output wire [1:0] m02_axi_arburst,
|
||||
output wire m02_axi_arlock,
|
||||
output wire [3:0] m02_axi_arcache,
|
||||
output wire [2:0] m02_axi_arprot,
|
||||
output wire [3:0] m02_axi_arqos,
|
||||
output wire [3:0] m02_axi_arregion,
|
||||
output wire [ARUSER_WIDTH-1:0] m02_axi_aruser,
|
||||
output wire m02_axi_arvalid,
|
||||
input wire m02_axi_arready,
|
||||
input wire [M_ID_WIDTH-1:0] m02_axi_rid,
|
||||
input wire [DATA_WIDTH-1:0] m02_axi_rdata,
|
||||
input wire [1:0] m02_axi_rresp,
|
||||
input wire m02_axi_rlast,
|
||||
input wire [RUSER_WIDTH-1:0] m02_axi_ruser,
|
||||
input wire m02_axi_rvalid,
|
||||
output wire m02_axi_rready
|
||||
);
|
||||
|
||||
localparam S_COUNT = 3;
|
||||
localparam M_COUNT = 3;
|
||||
|
||||
// parameter sizing helpers
|
||||
function [ADDR_WIDTH*M_REGIONS-1:0] w_a_r(input [ADDR_WIDTH*M_REGIONS-1:0] val);
|
||||
w_a_r = val;
|
||||
endfunction
|
||||
|
||||
function [32*M_REGIONS-1:0] w_32_r(input [32*M_REGIONS-1:0] val);
|
||||
w_32_r = val;
|
||||
endfunction
|
||||
|
||||
function [S_COUNT-1:0] w_s(input [S_COUNT-1:0] val);
|
||||
w_s = val;
|
||||
endfunction
|
||||
|
||||
function [31:0] w_32(input [31:0] val);
|
||||
w_32 = val;
|
||||
endfunction
|
||||
|
||||
function [1:0] w_2(input [1:0] val);
|
||||
w_2 = val;
|
||||
endfunction
|
||||
|
||||
function w_1(input val);
|
||||
w_1 = val;
|
||||
endfunction
|
||||
|
||||
axi_crossbar #(
|
||||
.S_COUNT(S_COUNT),
|
||||
.M_COUNT(M_COUNT),
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ADDR_WIDTH(ADDR_WIDTH),
|
||||
.STRB_WIDTH(STRB_WIDTH),
|
||||
.S_ID_WIDTH(S_ID_WIDTH),
|
||||
.M_ID_WIDTH(M_ID_WIDTH),
|
||||
.AWUSER_ENABLE(AWUSER_ENABLE),
|
||||
.AWUSER_WIDTH(AWUSER_WIDTH),
|
||||
.WUSER_ENABLE(WUSER_ENABLE),
|
||||
.WUSER_WIDTH(WUSER_WIDTH),
|
||||
.BUSER_ENABLE(BUSER_ENABLE),
|
||||
.BUSER_WIDTH(BUSER_WIDTH),
|
||||
.ARUSER_ENABLE(ARUSER_ENABLE),
|
||||
.ARUSER_WIDTH(ARUSER_WIDTH),
|
||||
.RUSER_ENABLE(RUSER_ENABLE),
|
||||
.RUSER_WIDTH(RUSER_WIDTH),
|
||||
.S_THREADS({ w_32(S02_THREADS), w_32(S01_THREADS), w_32(S00_THREADS) }),
|
||||
.S_ACCEPT({ w_32(S02_ACCEPT), w_32(S01_ACCEPT), w_32(S00_ACCEPT) }),
|
||||
.M_REGIONS(M_REGIONS),
|
||||
.M_BASE_ADDR({ w_a_r(M02_BASE_ADDR), w_a_r(M01_BASE_ADDR), w_a_r(M00_BASE_ADDR) }),
|
||||
.M_ADDR_WIDTH({ w_32_r(M02_ADDR_WIDTH), w_32_r(M01_ADDR_WIDTH), w_32_r(M00_ADDR_WIDTH) }),
|
||||
.M_CONNECT_READ({ w_s(M02_CONNECT_READ), w_s(M01_CONNECT_READ), w_s(M00_CONNECT_READ) }),
|
||||
.M_CONNECT_WRITE({ w_s(M02_CONNECT_WRITE), w_s(M01_CONNECT_WRITE), w_s(M00_CONNECT_WRITE) }),
|
||||
.M_ISSUE({ w_32(M02_ISSUE), w_32(M01_ISSUE), w_32(M00_ISSUE) }),
|
||||
.M_SECURE({ w_1(M02_SECURE), w_1(M01_SECURE), w_1(M00_SECURE) }),
|
||||
.S_AR_REG_TYPE({ w_2(S02_AR_REG_TYPE), w_2(S01_AR_REG_TYPE), w_2(S00_AR_REG_TYPE) }),
|
||||
.S_R_REG_TYPE({ w_2(S02_R_REG_TYPE), w_2(S01_R_REG_TYPE), w_2(S00_R_REG_TYPE) }),
|
||||
.S_AW_REG_TYPE({ w_2(S02_AW_REG_TYPE), w_2(S01_AW_REG_TYPE), w_2(S00_AW_REG_TYPE) }),
|
||||
.S_W_REG_TYPE({ w_2(S02_W_REG_TYPE), w_2(S01_W_REG_TYPE), w_2(S00_W_REG_TYPE) }),
|
||||
.S_B_REG_TYPE({ w_2(S02_B_REG_TYPE), w_2(S01_B_REG_TYPE), w_2(S00_B_REG_TYPE) }),
|
||||
.M_AR_REG_TYPE({ w_2(M02_AR_REG_TYPE), w_2(M01_AR_REG_TYPE), w_2(M00_AR_REG_TYPE) }),
|
||||
.M_R_REG_TYPE({ w_2(M02_R_REG_TYPE), w_2(M01_R_REG_TYPE), w_2(M00_R_REG_TYPE) }),
|
||||
.M_AW_REG_TYPE({ w_2(M02_AW_REG_TYPE), w_2(M01_AW_REG_TYPE), w_2(M00_AW_REG_TYPE) }),
|
||||
.M_W_REG_TYPE({ w_2(M02_W_REG_TYPE), w_2(M01_W_REG_TYPE), w_2(M00_W_REG_TYPE) }),
|
||||
.M_B_REG_TYPE({ w_2(M02_B_REG_TYPE), w_2(M01_B_REG_TYPE), w_2(M00_B_REG_TYPE) })
|
||||
)
|
||||
axi_crossbar_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.s_axi_awid({ s02_axi_awid, s01_axi_awid, s00_axi_awid }),
|
||||
.s_axi_awaddr({ s02_axi_awaddr, s01_axi_awaddr, s00_axi_awaddr }),
|
||||
.s_axi_awlen({ s02_axi_awlen, s01_axi_awlen, s00_axi_awlen }),
|
||||
.s_axi_awsize({ s02_axi_awsize, s01_axi_awsize, s00_axi_awsize }),
|
||||
.s_axi_awburst({ s02_axi_awburst, s01_axi_awburst, s00_axi_awburst }),
|
||||
.s_axi_awlock({ s02_axi_awlock, s01_axi_awlock, s00_axi_awlock }),
|
||||
.s_axi_awcache({ s02_axi_awcache, s01_axi_awcache, s00_axi_awcache }),
|
||||
.s_axi_awprot({ s02_axi_awprot, s01_axi_awprot, s00_axi_awprot }),
|
||||
.s_axi_awqos({ s02_axi_awqos, s01_axi_awqos, s00_axi_awqos }),
|
||||
.s_axi_awuser({ s02_axi_awuser, s01_axi_awuser, s00_axi_awuser }),
|
||||
.s_axi_awvalid({ s02_axi_awvalid, s01_axi_awvalid, s00_axi_awvalid }),
|
||||
.s_axi_awready({ s02_axi_awready, s01_axi_awready, s00_axi_awready }),
|
||||
.s_axi_wdata({ s02_axi_wdata, s01_axi_wdata, s00_axi_wdata }),
|
||||
.s_axi_wstrb({ s02_axi_wstrb, s01_axi_wstrb, s00_axi_wstrb }),
|
||||
.s_axi_wlast({ s02_axi_wlast, s01_axi_wlast, s00_axi_wlast }),
|
||||
.s_axi_wuser({ s02_axi_wuser, s01_axi_wuser, s00_axi_wuser }),
|
||||
.s_axi_wvalid({ s02_axi_wvalid, s01_axi_wvalid, s00_axi_wvalid }),
|
||||
.s_axi_wready({ s02_axi_wready, s01_axi_wready, s00_axi_wready }),
|
||||
.s_axi_bid({ s02_axi_bid, s01_axi_bid, s00_axi_bid }),
|
||||
.s_axi_bresp({ s02_axi_bresp, s01_axi_bresp, s00_axi_bresp }),
|
||||
.s_axi_buser({ s02_axi_buser, s01_axi_buser, s00_axi_buser }),
|
||||
.s_axi_bvalid({ s02_axi_bvalid, s01_axi_bvalid, s00_axi_bvalid }),
|
||||
.s_axi_bready({ s02_axi_bready, s01_axi_bready, s00_axi_bready }),
|
||||
.s_axi_arid({ s02_axi_arid, s01_axi_arid, s00_axi_arid }),
|
||||
.s_axi_araddr({ s02_axi_araddr, s01_axi_araddr, s00_axi_araddr }),
|
||||
.s_axi_arlen({ s02_axi_arlen, s01_axi_arlen, s00_axi_arlen }),
|
||||
.s_axi_arsize({ s02_axi_arsize, s01_axi_arsize, s00_axi_arsize }),
|
||||
.s_axi_arburst({ s02_axi_arburst, s01_axi_arburst, s00_axi_arburst }),
|
||||
.s_axi_arlock({ s02_axi_arlock, s01_axi_arlock, s00_axi_arlock }),
|
||||
.s_axi_arcache({ s02_axi_arcache, s01_axi_arcache, s00_axi_arcache }),
|
||||
.s_axi_arprot({ s02_axi_arprot, s01_axi_arprot, s00_axi_arprot }),
|
||||
.s_axi_arqos({ s02_axi_arqos, s01_axi_arqos, s00_axi_arqos }),
|
||||
.s_axi_aruser({ s02_axi_aruser, s01_axi_aruser, s00_axi_aruser }),
|
||||
.s_axi_arvalid({ s02_axi_arvalid, s01_axi_arvalid, s00_axi_arvalid }),
|
||||
.s_axi_arready({ s02_axi_arready, s01_axi_arready, s00_axi_arready }),
|
||||
.s_axi_rid({ s02_axi_rid, s01_axi_rid, s00_axi_rid }),
|
||||
.s_axi_rdata({ s02_axi_rdata, s01_axi_rdata, s00_axi_rdata }),
|
||||
.s_axi_rresp({ s02_axi_rresp, s01_axi_rresp, s00_axi_rresp }),
|
||||
.s_axi_rlast({ s02_axi_rlast, s01_axi_rlast, s00_axi_rlast }),
|
||||
.s_axi_ruser({ s02_axi_ruser, s01_axi_ruser, s00_axi_ruser }),
|
||||
.s_axi_rvalid({ s02_axi_rvalid, s01_axi_rvalid, s00_axi_rvalid }),
|
||||
.s_axi_rready({ s02_axi_rready, s01_axi_rready, s00_axi_rready }),
|
||||
.m_axi_awid({ m02_axi_awid, m01_axi_awid, m00_axi_awid }),
|
||||
.m_axi_awaddr({ m02_axi_awaddr, m01_axi_awaddr, m00_axi_awaddr }),
|
||||
.m_axi_awlen({ m02_axi_awlen, m01_axi_awlen, m00_axi_awlen }),
|
||||
.m_axi_awsize({ m02_axi_awsize, m01_axi_awsize, m00_axi_awsize }),
|
||||
.m_axi_awburst({ m02_axi_awburst, m01_axi_awburst, m00_axi_awburst }),
|
||||
.m_axi_awlock({ m02_axi_awlock, m01_axi_awlock, m00_axi_awlock }),
|
||||
.m_axi_awcache({ m02_axi_awcache, m01_axi_awcache, m00_axi_awcache }),
|
||||
.m_axi_awprot({ m02_axi_awprot, m01_axi_awprot, m00_axi_awprot }),
|
||||
.m_axi_awqos({ m02_axi_awqos, m01_axi_awqos, m00_axi_awqos }),
|
||||
.m_axi_awregion({ m02_axi_awregion, m01_axi_awregion, m00_axi_awregion }),
|
||||
.m_axi_awuser({ m02_axi_awuser, m01_axi_awuser, m00_axi_awuser }),
|
||||
.m_axi_awvalid({ m02_axi_awvalid, m01_axi_awvalid, m00_axi_awvalid }),
|
||||
.m_axi_awready({ m02_axi_awready, m01_axi_awready, m00_axi_awready }),
|
||||
.m_axi_wdata({ m02_axi_wdata, m01_axi_wdata, m00_axi_wdata }),
|
||||
.m_axi_wstrb({ m02_axi_wstrb, m01_axi_wstrb, m00_axi_wstrb }),
|
||||
.m_axi_wlast({ m02_axi_wlast, m01_axi_wlast, m00_axi_wlast }),
|
||||
.m_axi_wuser({ m02_axi_wuser, m01_axi_wuser, m00_axi_wuser }),
|
||||
.m_axi_wvalid({ m02_axi_wvalid, m01_axi_wvalid, m00_axi_wvalid }),
|
||||
.m_axi_wready({ m02_axi_wready, m01_axi_wready, m00_axi_wready }),
|
||||
.m_axi_bid({ m02_axi_bid, m01_axi_bid, m00_axi_bid }),
|
||||
.m_axi_bresp({ m02_axi_bresp, m01_axi_bresp, m00_axi_bresp }),
|
||||
.m_axi_buser({ m02_axi_buser, m01_axi_buser, m00_axi_buser }),
|
||||
.m_axi_bvalid({ m02_axi_bvalid, m01_axi_bvalid, m00_axi_bvalid }),
|
||||
.m_axi_bready({ m02_axi_bready, m01_axi_bready, m00_axi_bready }),
|
||||
.m_axi_arid({ m02_axi_arid, m01_axi_arid, m00_axi_arid }),
|
||||
.m_axi_araddr({ m02_axi_araddr, m01_axi_araddr, m00_axi_araddr }),
|
||||
.m_axi_arlen({ m02_axi_arlen, m01_axi_arlen, m00_axi_arlen }),
|
||||
.m_axi_arsize({ m02_axi_arsize, m01_axi_arsize, m00_axi_arsize }),
|
||||
.m_axi_arburst({ m02_axi_arburst, m01_axi_arburst, m00_axi_arburst }),
|
||||
.m_axi_arlock({ m02_axi_arlock, m01_axi_arlock, m00_axi_arlock }),
|
||||
.m_axi_arcache({ m02_axi_arcache, m01_axi_arcache, m00_axi_arcache }),
|
||||
.m_axi_arprot({ m02_axi_arprot, m01_axi_arprot, m00_axi_arprot }),
|
||||
.m_axi_arqos({ m02_axi_arqos, m01_axi_arqos, m00_axi_arqos }),
|
||||
.m_axi_arregion({ m02_axi_arregion, m01_axi_arregion, m00_axi_arregion }),
|
||||
.m_axi_aruser({ m02_axi_aruser, m01_axi_aruser, m00_axi_aruser }),
|
||||
.m_axi_arvalid({ m02_axi_arvalid, m01_axi_arvalid, m00_axi_arvalid }),
|
||||
.m_axi_arready({ m02_axi_arready, m01_axi_arready, m00_axi_arready }),
|
||||
.m_axi_rid({ m02_axi_rid, m01_axi_rid, m00_axi_rid }),
|
||||
.m_axi_rdata({ m02_axi_rdata, m01_axi_rdata, m00_axi_rdata }),
|
||||
.m_axi_rresp({ m02_axi_rresp, m01_axi_rresp, m00_axi_rresp }),
|
||||
.m_axi_rlast({ m02_axi_rlast, m01_axi_rlast, m00_axi_rlast }),
|
||||
.m_axi_ruser({ m02_axi_ruser, m01_axi_ruser, m00_axi_ruser }),
|
||||
.m_axi_rvalid({ m02_axi_rvalid, m01_axi_rvalid, m00_axi_rvalid }),
|
||||
.m_axi_rready({ m02_axi_rready, m01_axi_rready, m00_axi_rready })
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
1045
axi/axi_crossbar_wrapper.sv
Normal file
1045
axi/axi_crossbar_wrapper.sv
Normal file
File diff suppressed because it is too large
Load Diff
309
axi/axi_dma_wrapper.sv
Normal file
309
axi/axi_dma_wrapper.sv
Normal file
@ -0,0 +1,309 @@
|
||||
module axi_dma_wrapper #(
|
||||
parameter AXI_DATA_WIDTH = 32,
|
||||
parameter AXI_ADDR_WIDTH = 16,
|
||||
parameter AXI_ID_WIDTH = 8,
|
||||
parameter AXI_MAX_BURST_LEN = 16,
|
||||
parameter AXIS_LAST_ENABLE = 1,
|
||||
parameter AXIS_ID_ENABLE = 0,
|
||||
parameter AXIS_ID_WIDTH = 8,
|
||||
parameter AXIS_DEST_ENABLE = 0,
|
||||
parameter AXIS_DEST_WIDTH = 8,
|
||||
parameter AXIS_USER_ENABLE = 1,
|
||||
parameter AXIS_USER_WIDTH = 1,
|
||||
parameter LEN_WIDTH = 20,
|
||||
parameter TAG_WIDTH = 8,
|
||||
parameter ENABLE_SG = 0,
|
||||
parameter ENABLE_UNALIGNED = 0
|
||||
)(
|
||||
input wire crossbar_clk,
|
||||
input wire crossbar_rst,
|
||||
|
||||
input wire dma_clk,
|
||||
input wire dma_rst,
|
||||
|
||||
axi4l_if.slave s_axil_control,
|
||||
axi4_if.master m_axi_data,
|
||||
|
||||
output wire [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata,
|
||||
output wire [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep,
|
||||
output wire m_axis_read_data_tvalid,
|
||||
input wire m_axis_read_data_tready,
|
||||
output wire m_axis_read_data_tlast,
|
||||
output wire [AXIS_ID_WIDTH-1:0] m_axis_read_data_tid,
|
||||
output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest,
|
||||
output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser,
|
||||
|
||||
input wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata,
|
||||
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep,
|
||||
input wire s_axis_write_data_tvalid,
|
||||
output wire s_axis_write_data_tready,
|
||||
input wire s_axis_write_data_tlast,
|
||||
input wire [AXIS_ID_WIDTH-1:0] s_axis_write_data_tid,
|
||||
input wire [AXIS_DEST_WIDTH-1:0] s_axis_write_data_tdest,
|
||||
input wire [AXIS_USER_WIDTH-1:0] s_axis_write_data_tuser
|
||||
);
|
||||
|
||||
wire [AXI_ADDR_WIDTH-1:0] dma_s_axis_read_desc_addr;
|
||||
wire [LEN_WIDTH-1:0] dma_s_axis_read_desc_len;
|
||||
wire [TAG_WIDTH-1:0] dma_s_axis_read_desc_tag;
|
||||
wire [AXIS_ID_WIDTH-1:0] dma_s_axis_read_desc_id;
|
||||
wire [AXIS_DEST_WIDTH-1:0] dma_s_axis_read_desc_dest;
|
||||
wire [AXIS_USER_WIDTH-1:0] dma_s_axis_read_desc_user;
|
||||
wire dma_s_axis_read_desc_valid;
|
||||
wire dma_s_axis_read_desc_ready;
|
||||
|
||||
wire [TAG_WIDTH-1:0] dma_m_axis_read_desc_status_tag;
|
||||
wire [3:0] dma_m_axis_read_desc_status_error;
|
||||
wire dma_m_axis_read_desc_status_valid;
|
||||
|
||||
wire [AXI_ID_WIDTH-1:0] dma_m_axi_awid;
|
||||
wire [AXI_ADDR_WIDTH-1:0] dma_m_axi_awaddr;
|
||||
wire [7:0] dma_m_axi_awlen;
|
||||
wire [2:0] dma_m_axi_awsize;
|
||||
wire [1:0] dma_m_axi_awburst;
|
||||
wire dma_m_axi_awlock;
|
||||
wire [3:0] dma_m_axi_awcache;
|
||||
wire [2:0] dma_m_axi_awprot;
|
||||
wire dma_m_axi_awvalid;
|
||||
wire dma_m_axi_awready;
|
||||
wire [AXI_DATA_WIDTH-1:0] dma_m_axi_wdata;
|
||||
wire [AXI_STRB_WIDTH-1:0] dma_m_axi_wstrb;
|
||||
wire dma_m_axi_wlast;
|
||||
wire dma_m_axi_wvalid;
|
||||
wire dma_m_axi_wready;
|
||||
wire [AXI_ID_WIDTH-1:0] dma_m_axi_bid;
|
||||
wire [1:0] dma_m_axi_bresp;
|
||||
wire dma_m_axi_bvalid;
|
||||
wire dma_m_axi_bready;
|
||||
wire [AXI_ID_WIDTH-1:0] dma_m_axi_arid;
|
||||
wire [AXI_ADDR_WIDTH-1:0] dma_m_axi_araddr;
|
||||
wire [7:0] dma_m_axi_arlen;
|
||||
wire [2:0] dma_m_axi_arsize;
|
||||
wire [1:0] dma_m_axi_arburst;
|
||||
wire dma_m_axi_arlock;
|
||||
wire [3:0] dma_m_axi_arcache;
|
||||
wire [2:0] dma_m_axi_arprot;
|
||||
wire dma_m_axi_arvalid;
|
||||
wire dma_m_axi_arready;
|
||||
wire [AXI_ID_WIDTH-1:0] dma_m_axi_rid;
|
||||
wire [AXI_DATA_WIDTH-1:0] dma_m_axi_rdata;
|
||||
wire [1:0] dma_m_axi_rresp;
|
||||
wire dma_m_axi_rlast;
|
||||
wire dma_m_axi_rvalid;
|
||||
wire dma_m_axi_rready;
|
||||
|
||||
wire [AXI_ADDR_WIDTH-1:0] dma_s_axis_write_desc_addr;
|
||||
wire [LEN_WIDTH-1:0] dma_s_axis_write_desc_len;
|
||||
wire [TAG_WIDTH-1:0] dma_s_axis_write_desc_tag;
|
||||
wire dma_s_axis_write_desc_valid;
|
||||
wire dma_s_axis_write_desc_ready;
|
||||
|
||||
wire [LEN_WIDTH-1:0] dma_m_axis_write_desc_status_len;
|
||||
wire [TAG_WIDTH-1:0] dma_m_axis_write_desc_status_tag;
|
||||
wire [AXIS_ID_WIDTH-1:0] dma_m_axis_write_desc_status_id;
|
||||
wire [AXIS_DEST_WIDTH-1:0] dma_m_axis_write_desc_status_dest;
|
||||
wire [AXIS_USER_WIDTH-1:0] dma_m_axis_write_desc_status_user;
|
||||
wire [3:0] dma_m_axis_write_desc_status_error;
|
||||
wire dma_m_axis_write_desc_status_valid;
|
||||
|
||||
wire dma_read_enable;
|
||||
wire dma_write_enable;
|
||||
wire dma_write_abort;
|
||||
|
||||
|
||||
axi4l_if #(.ADDR_W(AXI_ADDR_WIDTH), .DATA_W(AXI_DATA_WIDTH)) axi4_if_cdc ();
|
||||
|
||||
axil_cdc_wrapper #(
|
||||
.ADDR_WIDTH (AXI_ADDR_WIDTH),
|
||||
.DATA_WIDTH (AXI_DATA_WIDTH)
|
||||
) i_dma_ctrl_cdc (
|
||||
.s_clk (crossbar_clk),
|
||||
.s_rst (crossbar_rst),
|
||||
.s_axi (s_axil_control),
|
||||
|
||||
.m_clk (dma_clk),
|
||||
.m_rst (dma_rst),
|
||||
.m_axi (axi4_if_cdc)
|
||||
);
|
||||
|
||||
wire [N_REGS-1:0][31:0] reg_i;
|
||||
wire [N_REGS-1:0][31:0] reg_o;
|
||||
|
||||
import dma_axil_reg_map_pkg::*;
|
||||
axi4l_reg_map #(
|
||||
.ADDR_W (AXI_ADDR_WIDTH),
|
||||
.DATA_W (AXI_DATA_WIDTH),
|
||||
.USER_W (0),
|
||||
.N_REGS (DMA_AXIL_REG_MAP_N_REGS),
|
||||
.REG_MODE (DMA_AXIL_REG_MAP_REG_MODE),
|
||||
.REG_RST (DMA_AXIL_REG_MAP_REG_RST)
|
||||
) i_axi4l_dma_reg_map (
|
||||
.clk (dma_clk),
|
||||
.rst_n (!dma_rst),
|
||||
.s_axil (axi4_if_cdc),
|
||||
.reg_i (reg_i),
|
||||
.reg_o (reg_o)
|
||||
);
|
||||
|
||||
always_comb begin
|
||||
dma_s_axis_write_desc_valid = reg_o[DMA_WRITE_DESC_CONTROL_REG][0];
|
||||
dma_s_axis_write_desc_addr = reg_o[DMA_WRITE_DESC_ADDR_REG][31:0];
|
||||
dma_s_axis_write_desc_len = reg_o[DMA_WRITE_DESC_LEN_REG][31:0];
|
||||
reg_i[DMA_WRITE_DESC_CONTROL_REG][1] = dma_s_axis_write_desc_ready;
|
||||
|
||||
dma_s_axis_read_desc_valid = reg_o[DMA_READ_DESC_CONTROL_REG][0];
|
||||
dma_s_axis_read_desc_addr = reg_o[DMA_READ_DESC_ADDR_REG][31:0];
|
||||
dma_s_axis_read_desc_len = reg_o[DMA_READ_DESC_LEN_REG][31:0];
|
||||
reg_i[DMA_READ_DESC_CONTROL_REG][1] = dma_s_axis_read_desc_ready;
|
||||
end
|
||||
|
||||
axi4_flat_to_if #(
|
||||
.ADDR_W (AXI_ADDR_WIDTH),
|
||||
.DATA_W (AXI_DATA_WIDTH)
|
||||
) i_axi4_flat_to_if (
|
||||
.s_axi_awid (dma_m_axi_awid),
|
||||
.s_axi_awaddr (dma_m_axi_awaddr),
|
||||
.s_axi_awlen (dma_m_axi_awlen),
|
||||
.s_axi_awsize (dma_m_axi_awsize),
|
||||
.s_axi_awburst (dma_m_axi_awburst),
|
||||
.s_axi_awlock (dma_m_axi_awlock),
|
||||
.s_axi_awcache (dma_m_axi_awcache),
|
||||
.s_axi_awprot (dma_m_axi_awprot),
|
||||
.s_axi_awqos (dma_m_axi_awqos),
|
||||
.s_axi_awregion (dma_m_axi_awregion),
|
||||
.s_axi_awuser (dma_m_axi_awuser),
|
||||
.s_axi_awvalid (dma_m_axi_awvalid),
|
||||
.s_axi_awready (dma_m_axi_awready),
|
||||
.s_axi_wdata (dma_m_axi_wdata),
|
||||
.s_axi_wstrb (dma_m_axi_wstrb),
|
||||
.s_axi_wlast (dma_m_axi_wlast),
|
||||
.s_axi_wuser (dma_m_axi_wuser),
|
||||
.s_axi_wvalid (dma_m_axi_wvalid),
|
||||
.s_axi_wready (dma_m_axi_wready),
|
||||
.s_axi_bid (dma_m_axi_bid),
|
||||
.s_axi_bresp (dma_m_axi_bresp),
|
||||
.s_axi_buser (dma_m_axi_buser),
|
||||
.s_axi_bvalid (dma_m_axi_bvalid),
|
||||
.s_axi_bready (dma_m_axi_bready),
|
||||
.s_axi_arid (dma_m_axi_arid),
|
||||
.s_axi_araddr (dma_m_axi_araddr),
|
||||
.s_axi_arlen (dma_m_axi_arlen),
|
||||
.s_axi_arsize (dma_m_axi_arsize),
|
||||
.s_axi_arburst (dma_m_axi_arburst),
|
||||
.s_axi_arlock (dma_m_axi_arlock),
|
||||
.s_axi_arcache (dma_m_axi_arcache),
|
||||
.s_axi_arprot (dma_m_axi_arprot),
|
||||
.s_axi_arqos (dma_m_axi_arqos),
|
||||
.s_axi_arregion (dma_m_axi_arregion),
|
||||
.s_axi_aruser (dma_m_axi_aruser),
|
||||
.s_axi_arvalid (dma_m_axi_arvalid),
|
||||
.s_axi_arready (dma_m_axi_arready),
|
||||
.s_axi_rid (dma_m_axi_rid),
|
||||
.s_axi_rdata (dma_m_axi_rdata),
|
||||
.s_axi_rresp (dma_m_axi_rresp),
|
||||
.s_axi_rlast (dma_m_axi_rlast),
|
||||
.s_axi_ruser (dma_m_axi_ruser),
|
||||
.s_axi_rvalid (dma_m_axi_rvalid),
|
||||
.s_axi_rready (dma_m_axi_rready),
|
||||
.m_axi (m_axi_data)
|
||||
);
|
||||
|
||||
axi_dma #(
|
||||
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
|
||||
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
|
||||
.AXI_ID_WIDTH (AXI_ID_WIDTH),
|
||||
.AXI_MAX_BURST_LEN (AXI_MAX_BURST_LEN),
|
||||
.AXIS_LAST_ENABLE (AXIS_LAST_ENABLE),
|
||||
.AXIS_ID_ENABLE (AXIS_ID_ENABLE),
|
||||
.AXIS_ID_WIDTH (AXIS_ID_WIDTH),
|
||||
.AXIS_DEST_ENABLE (AXIS_DEST_ENABLE),
|
||||
.AXIS_DEST_WIDTH (AXIS_DEST_WIDTH),
|
||||
.AXIS_USER_ENABLE (AXIS_USER_ENABLE),
|
||||
.AXIS_USER_WIDTH (AXIS_USER_WIDTH),
|
||||
.LEN_WIDTH (LEN_WIDTH),
|
||||
.TAG_WIDTH (TAG_WIDTH),
|
||||
.ENABLE_SG (ENABLE_SG),
|
||||
.ENABLE_UNALIGNED (ENABLE_UNALIGNED)
|
||||
) i_axi_dma (
|
||||
.clk (dma_clk),
|
||||
.rst (dma_rst),
|
||||
.s_axis_read_desc_addr (dma_s_axis_read_desc_addr),
|
||||
.s_axis_read_desc_len (dma_s_axis_read_desc_len),
|
||||
.s_axis_read_desc_tag (dma_s_axis_read_desc_tag),
|
||||
.s_axis_read_desc_id (dma_s_axis_read_desc_id),
|
||||
.s_axis_read_desc_dest (dma_s_axis_read_desc_dest),
|
||||
.s_axis_read_desc_user (dma_s_axis_read_desc_user),
|
||||
.s_axis_read_desc_valid (dma_s_axis_read_desc_valid),
|
||||
.s_axis_read_desc_ready (dma_s_axis_read_desc_ready),
|
||||
.m_axis_read_desc_status_tag (dma_m_axis_read_desc_status_tag),
|
||||
.m_axis_read_desc_status_error (dma_m_axis_read_desc_status_error),
|
||||
.m_axis_read_desc_status_valid (dma_m_axis_read_desc_status_valid),
|
||||
.m_axis_read_data_tdata (m_axis_read_data_tdata),
|
||||
.m_axis_read_data_tkeep (m_axis_read_data_tkeep),
|
||||
.m_axis_read_data_tvalid (m_axis_read_data_tvalid),
|
||||
.m_axis_read_data_tready (m_axis_read_data_tready),
|
||||
.m_axis_read_data_tlast (m_axis_read_data_tlast),
|
||||
.m_axis_read_data_tid (m_axis_read_data_tid),
|
||||
.m_axis_read_data_tdest (m_axis_read_data_tdest),
|
||||
.m_axis_read_data_tuser (m_axis_read_data_tuser),
|
||||
.s_axis_write_desc_addr (dma_s_axis_write_desc_addr),
|
||||
.s_axis_write_desc_len (dma_s_axis_write_desc_len),
|
||||
.s_axis_write_desc_tag (dma_s_axis_write_desc_tag),
|
||||
.s_axis_write_desc_valid (dma_s_axis_write_desc_valid),
|
||||
.s_axis_write_desc_ready (dma_s_axis_write_desc_ready),
|
||||
.m_axis_write_desc_status_len (dma_m_axis_write_desc_status_len),
|
||||
.m_axis_write_desc_status_tag (dma_m_axis_write_desc_status_tag),
|
||||
.m_axis_write_desc_status_id (dma_m_axis_write_desc_status_id),
|
||||
.m_axis_write_desc_status_dest (dma_m_axis_write_desc_status_dest),
|
||||
.m_axis_write_desc_status_user (dma_m_axis_write_desc_status_user),
|
||||
.m_axis_write_desc_status_error (dma_m_axis_write_desc_status_error),
|
||||
.m_axis_write_desc_status_valid (dma_m_axis_write_desc_status_valid),
|
||||
.s_axis_write_data_tdata (s_axis_write_data_tdata),
|
||||
.s_axis_write_data_tkeep (s_axis_write_data_tkeep),
|
||||
.s_axis_write_data_tvalid (s_axis_write_data_tvalid),
|
||||
.s_axis_write_data_tready (s_axis_write_data_tready),
|
||||
.s_axis_write_data_tlast (s_axis_write_data_tlast),
|
||||
.s_axis_write_data_tid (s_axis_write_data_tid),
|
||||
.s_axis_write_data_tdest (s_axis_write_data_tdest),
|
||||
.s_axis_write_data_tuser (s_axis_write_data_tuser),
|
||||
.m_axi_awid (dma_m_axi_awid),
|
||||
.m_axi_awaddr (dma_m_axi_awaddr),
|
||||
.m_axi_awlen (dma_m_axi_awlen),
|
||||
.m_axi_awsize (dma_m_axi_awsize),
|
||||
.m_axi_awburst (dma_m_axi_awburst),
|
||||
.m_axi_awlock (dma_m_axi_awlock),
|
||||
.m_axi_awcache (dma_m_axi_awcache),
|
||||
.m_axi_awprot (dma_m_axi_awprot),
|
||||
.m_axi_awvalid (dma_m_axi_awvalid),
|
||||
.m_axi_awready (dma_m_axi_awready),
|
||||
.m_axi_wdata (dma_m_axi_wdata),
|
||||
.m_axi_wstrb (dma_m_axi_wstrb),
|
||||
.m_axi_wlast (dma_m_axi_wlast),
|
||||
.m_axi_wvalid (dma_m_axi_wvalid),
|
||||
.m_axi_wready (dma_m_axi_wready),
|
||||
.m_axi_bid (dma_m_axi_bid),
|
||||
.m_axi_bresp (dma_m_axi_bresp),
|
||||
.m_axi_bvalid (dma_m_axi_bvalid),
|
||||
.m_axi_bready (dma_m_axi_bready),
|
||||
.m_axi_arid (dma_m_axi_arid),
|
||||
.m_axi_araddr (dma_m_axi_araddr),
|
||||
.m_axi_arlen (dma_m_axi_arlen),
|
||||
.m_axi_arsize (dma_m_axi_arsize),
|
||||
.m_axi_arburst (dma_m_axi_arburst),
|
||||
.m_axi_arlock (dma_m_axi_arlock),
|
||||
.m_axi_arcache (dma_m_axi_arcache),
|
||||
.m_axi_arprot (dma_m_axi_arprot),
|
||||
.m_axi_arvalid (dma_m_axi_arvalid),
|
||||
.m_axi_arready (dma_m_axi_arready),
|
||||
.m_axi_rid (dma_m_axi_rid),
|
||||
.m_axi_rdata (dma_m_axi_rdata),
|
||||
.m_axi_rresp (dma_m_axi_rresp),
|
||||
.m_axi_rlast (dma_m_axi_rlast),
|
||||
.m_axi_rvalid (dma_m_axi_rvalid),
|
||||
.m_axi_rready (dma_m_axi_rready),
|
||||
.read_enable (dma_read_enable),
|
||||
.write_enable (dma_write_enable),
|
||||
.write_abort (dma_write_abort)
|
||||
);
|
||||
|
||||
endmodule
|
||||
43
axi/axi_if.sv
Normal file
43
axi/axi_if.sv
Normal file
@ -0,0 +1,43 @@
|
||||
interface axi4_if #(
|
||||
parameter int unsigned ADDR_W = 32,
|
||||
parameter int unsigned DATA_W = 32,
|
||||
parameter int unsigned ID_W = 4,
|
||||
parameter int unsigned USER_W = 1
|
||||
)(
|
||||
input logic aclk,
|
||||
input logic aresetn
|
||||
);
|
||||
import axi_pkg::*;
|
||||
typedef logic [ADDR_W-1:0] addr_t;
|
||||
typedef logic [DATA_W-1:0] data_t;
|
||||
typedef logic [DATA_W/8-1:0] strb_t;
|
||||
typedef logic [ID_W-1:0] id_t;
|
||||
typedef logic [USER_W-1:0] user_t;
|
||||
`AXI4_TYPEDEF_ALL(axi, addr_t, data_t, strb_t, id_t, user_t)
|
||||
axi_req_t req;
|
||||
axi_resp_t resp;
|
||||
modport master (input aclk, aresetn, output req, input resp);
|
||||
modport slave (input aclk, aresetn, input req, output resp);
|
||||
modport monitor(input aclk, aresetn, input req, input resp);
|
||||
endinterface : axi4_if
|
||||
|
||||
interface axi4l_if #(
|
||||
parameter int unsigned ADDR_W = 32,
|
||||
parameter int unsigned DATA_W = 32,
|
||||
parameter int unsigned USER_W = 1
|
||||
)(
|
||||
input logic aclk,
|
||||
input logic aresetn
|
||||
);
|
||||
import axi_pkg::*;
|
||||
typedef logic [ADDR_W-1:0] addr_t;
|
||||
typedef logic [DATA_W-1:0] data_t;
|
||||
typedef logic [DATA_W/8-1:0] strb_t;
|
||||
typedef logic [USER_W-1:0] user_t;
|
||||
`AXI4L_TYPEDEF_ALL(axil, addr_t, data_t, strb_t, user_t)
|
||||
axil_req_t req;
|
||||
axil_resp_t resp;
|
||||
modport master (input aclk, aresetn, output req, input resp);
|
||||
modport slave (input aclk, aresetn, input req, output resp);
|
||||
modport monitor(input aclk, aresetn, input req, input resp);
|
||||
endinterface : axi4l_if
|
||||
140
axi/axi_pkg.sv
Normal file
140
axi/axi_pkg.sv
Normal file
@ -0,0 +1,140 @@
|
||||
package axi_pkg;
|
||||
|
||||
typedef enum logic [1:0] {
|
||||
AXI_BURST_FIXED = 2'b00,
|
||||
AXI_BURST_INCR = 2'b01,
|
||||
AXI_BURST_WRAP = 2'b10
|
||||
} axi_burst_t;
|
||||
|
||||
typedef enum logic [1:0] {
|
||||
AXI_RESP_OKAY = 2'b00,
|
||||
AXI_RESP_EXOKAY = 2'b01,
|
||||
AXI_RESP_SLVERR = 2'b10,
|
||||
AXI_RESP_DECERR = 2'b11
|
||||
} axi_resp_t;
|
||||
|
||||
function automatic logic [2:0] axi_size_from_bytes(input int unsigned nbytes);
|
||||
case (nbytes)
|
||||
1 : return 3'd0;
|
||||
2 : return 3'd1;
|
||||
4 : return 3'd2;
|
||||
8 : return 3'd3;
|
||||
16 : return 3'd4;
|
||||
32 : return 3'd5;
|
||||
64 : return 3'd6;
|
||||
128 : return 3'd7;
|
||||
default: return 3'd0;
|
||||
endcase
|
||||
endfunction
|
||||
|
||||
endpackage : axi_pkg
|
||||
|
||||
`define AXI4_TYPEDEF_ALL(__name, __addr_t, __data_t, __strb_t, __id_t, __user_t) \
|
||||
typedef struct packed { \
|
||||
__id_t id; \
|
||||
__addr_t addr; \
|
||||
logic [7:0] len; \
|
||||
logic [2:0] size; \
|
||||
axi_pkg::axi_burst_t burst; \
|
||||
logic lock; \
|
||||
logic [3:0] cache; \
|
||||
logic [2:0] prot; \
|
||||
logic [3:0] qos; \
|
||||
logic [3:0] region; \
|
||||
__user_t user; \
|
||||
logic valid; \
|
||||
} __name``_aw_chan_t; \
|
||||
typedef struct packed { \
|
||||
__data_t data; \
|
||||
__strb_t strb; \
|
||||
logic last; \
|
||||
__user_t user; \
|
||||
logic valid; \
|
||||
} __name``_w_chan_t; \
|
||||
typedef struct packed { \
|
||||
__id_t id; \
|
||||
axi_pkg::axi_resp_t resp; \
|
||||
__user_t user; \
|
||||
logic valid; \
|
||||
} __name``_b_chan_t; \
|
||||
typedef struct packed { \
|
||||
__id_t id; \
|
||||
__addr_t addr; \
|
||||
logic [7:0] len; \
|
||||
logic [2:0] size; \
|
||||
axi_pkg::axi_burst_t burst; \
|
||||
logic lock; \
|
||||
logic [3:0] cache; \
|
||||
logic [2:0] prot; \
|
||||
logic [3:0] qos; \
|
||||
logic [3:0] region; \
|
||||
__user_t user; \
|
||||
logic valid; \
|
||||
} __name``_ar_chan_t; \
|
||||
typedef struct packed { \
|
||||
__id_t id; \
|
||||
__data_t data; \
|
||||
axi_pkg::axi_resp_t resp; \
|
||||
logic last; \
|
||||
__user_t user; \
|
||||
logic valid; \
|
||||
} __name``_r_chan_t; \
|
||||
typedef struct packed { \
|
||||
__name``_aw_chan_t aw; \
|
||||
__name``_w_chan_t w; \
|
||||
logic b_ready; \
|
||||
__name``_ar_chan_t ar; \
|
||||
logic r_ready; \
|
||||
} __name``_req_t; \
|
||||
typedef struct packed { \
|
||||
logic aw_ready; \
|
||||
logic w_ready; \
|
||||
__name``_b_chan_t b; \
|
||||
logic ar_ready; \
|
||||
__name``_r_chan_t r; \
|
||||
} __name``_resp_t
|
||||
|
||||
`define AXI4L_TYPEDEF_ALL(__name, __addr_t, __data_t, __strb_t, __user_t) \
|
||||
typedef struct packed { \
|
||||
__addr_t addr; \
|
||||
logic [2:0] prot; \
|
||||
__user_t user; \
|
||||
logic valid; \
|
||||
} __name``_aw_chan_t; \
|
||||
typedef struct packed { \
|
||||
__data_t data; \
|
||||
__strb_t strb; \
|
||||
__user_t user; \
|
||||
logic valid; \
|
||||
} __name``_w_chan_t; \
|
||||
typedef struct packed { \
|
||||
axi_pkg::axi_resp_t resp; \
|
||||
__user_t user; \
|
||||
logic valid; \
|
||||
} __name``_b_chan_t; \
|
||||
typedef struct packed { \
|
||||
__addr_t addr; \
|
||||
logic [2:0] prot; \
|
||||
__user_t user; \
|
||||
logic valid; \
|
||||
} __name``_ar_chan_t; \
|
||||
typedef struct packed { \
|
||||
__data_t data; \
|
||||
axi_pkg::axi_resp_t resp; \
|
||||
__user_t user; \
|
||||
logic valid; \
|
||||
} __name``_r_chan_t; \
|
||||
typedef struct packed { \
|
||||
__name``_aw_chan_t aw; \
|
||||
__name``_w_chan_t w; \
|
||||
logic b_ready; \
|
||||
__name``_ar_chan_t ar; \
|
||||
logic r_ready; \
|
||||
} __name``_req_t; \
|
||||
typedef struct packed { \
|
||||
logic aw_ready; \
|
||||
logic w_ready; \
|
||||
__name``_b_chan_t b; \
|
||||
logic ar_ready; \
|
||||
__name``_r_chan_t r; \
|
||||
} __name``_resp_t
|
||||
146
axi/axi_ram_wrapper.sv
Normal file
146
axi/axi_ram_wrapper.sv
Normal file
@ -0,0 +1,146 @@
|
||||
module axi_ram_wrapper #(
|
||||
parameter DATA_WIDTH = 32,
|
||||
parameter ADDR_WIDTH = 16,
|
||||
parameter ID_WIDTH = 8,
|
||||
parameter PIPELINE_OUTPUT = 0
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
axi4_if.slaver s_axi
|
||||
);
|
||||
|
||||
wire [ID_WIDTH-1:0] ram_s_axi_awid;
|
||||
wire [ADDR_WIDTH-1:0] ram_s_axi_awaddr;
|
||||
wire [7:0] ram_s_axi_awlen;
|
||||
wire [2:0] ram_s_axi_awsize;
|
||||
wire [1:0] ram_s_axi_awburst;
|
||||
wire ram_s_axi_awlock;
|
||||
wire [3:0] ram_s_axi_awcache;
|
||||
wire [2:0] ram_s_axi_awprot;
|
||||
wire ram_s_axi_awvalid;
|
||||
wire ram_s_axi_awready;
|
||||
wire [DATA_WIDTH-1:0] ram_s_axi_wdata;
|
||||
wire [STRB_WIDTH-1:0] ram_s_axi_wstrb;
|
||||
wire ram_s_axi_wlast;
|
||||
wire ram_s_axi_wvalid;
|
||||
wire ram_s_axi_wready;
|
||||
wire [ID_WIDTH-1:0] ram_s_axi_bid;
|
||||
wire [1:0] ram_s_axi_bresp;
|
||||
wire ram_s_axi_bvalid;
|
||||
wire ram_s_axi_bready;
|
||||
wire [ID_WIDTH-1:0] ram_s_axi_arid;
|
||||
wire [ADDR_WIDTH-1:0] ram_s_axi_araddr;
|
||||
wire [7:0] ram_s_axi_arlen;
|
||||
wire [2:0] ram_s_axi_arsize;
|
||||
wire [1:0] ram_s_axi_arburst;
|
||||
wire ram_s_axi_arlock;
|
||||
wire [3:0] ram_s_axi_arcache;
|
||||
wire [2:0] ram_s_axi_arprot;
|
||||
wire ram_s_axi_arvalid;
|
||||
wire ram_s_axi_arready;
|
||||
wire [ID_WIDTH-1:0] ram_s_axi_rid;
|
||||
wire [DATA_WIDTH-1:0] ram_s_axi_rdata;
|
||||
wire [1:0] ram_s_axi_rresp;
|
||||
wire ram_s_axi_rlast;
|
||||
wire ram_s_axi_rvalid;
|
||||
wire ram_s_axi_rready;
|
||||
|
||||
axi4_if_to_flat #(
|
||||
.ADDR_W (ADDR_WIDTH),
|
||||
.DATA_W (DATA_WIDTH)
|
||||
) i_axi4_if_to_flat (
|
||||
.s_axi (s_axi),
|
||||
.m_axi_awid (ram_s_axi_awid),
|
||||
.m_axi_awaddr (ram_s_axi_awaddr),
|
||||
.m_axi_awlen (ram_s_axi_awlen),
|
||||
.m_axi_awsize (ram_s_axi_awsize),
|
||||
.m_axi_awburst (ram_s_axi_awburst),
|
||||
.m_axi_awlock (ram_s_axi_awlock),
|
||||
.m_axi_awcache (ram_s_axi_awcache),
|
||||
.m_axi_awprot (ram_s_axi_awprot),
|
||||
.m_axi_awqos (ram_s_axi_awqos),
|
||||
.m_axi_awregion (ram_s_axi_awregion),
|
||||
.m_axi_awuser (ram_s_axi_awuser),
|
||||
.m_axi_awvalid (ram_s_axi_awvalid),
|
||||
.m_axi_awready (ram_s_axi_awready),
|
||||
.m_axi_wdata (ram_s_axi_wdata),
|
||||
.m_axi_wstrb (ram_s_axi_wstrb),
|
||||
.m_axi_wlast (ram_s_axi_wlast),
|
||||
.m_axi_wuser (ram_s_axi_wuser),
|
||||
.m_axi_wvalid (ram_s_axi_wvalid),
|
||||
.m_axi_wready (ram_s_axi_wready),
|
||||
.m_axi_bid (ram_s_axi_bid),
|
||||
.m_axi_bresp (ram_s_axi_bresp),
|
||||
.m_axi_buser (ram_s_axi_buser),
|
||||
.m_axi_bvalid (ram_s_axi_bvalid),
|
||||
.m_axi_bready (ram_s_axi_bready),
|
||||
.m_axi_arid (ram_s_axi_arid),
|
||||
.m_axi_araddr (ram_s_axi_araddr),
|
||||
.m_axi_arlen (ram_s_axi_arlen),
|
||||
.m_axi_arsize (ram_s_axi_arsize),
|
||||
.m_axi_arburst (ram_s_axi_arburst),
|
||||
.m_axi_arlock (ram_s_axi_arlock),
|
||||
.m_axi_arcache (ram_s_axi_arcache),
|
||||
.m_axi_arprot (ram_s_axi_arprot),
|
||||
.m_axi_arqos (ram_s_axi_arqos),
|
||||
.m_axi_arregion (ram_s_axi_arregion),
|
||||
.m_axi_aruser (ram_s_axi_aruser),
|
||||
.m_axi_arvalid (ram_s_axi_arvalid),
|
||||
.m_axi_arready (ram_s_axi_arready),
|
||||
.m_axi_rid (ram_s_axi_rid),
|
||||
.m_axi_rdata (ram_s_axi_rdata),
|
||||
.m_axi_rresp (ram_s_axi_rresp),
|
||||
.m_axi_rlast (ram_s_axi_rlast),
|
||||
.m_axi_ruser (ram_s_axi_ruser),
|
||||
.m_axi_rvalid (ram_s_axi_rvalid),
|
||||
.m_axi_rready (ram_s_axi_rready)
|
||||
);
|
||||
|
||||
axi_ram #
|
||||
(
|
||||
.DATA_WIDTH (DATA_WIDTH),
|
||||
.ADDR_WIDTH (ADDR_WIDTH),
|
||||
.ID_WIDTH (ID_WIDTH),
|
||||
.PIPELINE_OUTPUT (PIPELINE_OUTPUT)
|
||||
) i_axi_ram (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.s_axi_awid (ram_s_axi_awid),
|
||||
.s_axi_awaddr (ram_s_axi_awaddr),
|
||||
.s_axi_awlen (ram_s_axi_awlen),
|
||||
.s_axi_awsize (ram_s_axi_awsize),
|
||||
.s_axi_awburst (ram_s_axi_awburst),
|
||||
.s_axi_awlock (ram_s_axi_awlock),
|
||||
.s_axi_awcache (ram_s_axi_awcache),
|
||||
.s_axi_awprot (ram_s_axi_awprot),
|
||||
.s_axi_awvalid (ram_s_axi_awvalid),
|
||||
.s_axi_awready (ram_s_axi_awready),
|
||||
.s_axi_wdata (ram_s_axi_wdata),
|
||||
.s_axi_wstrb (ram_s_axi_wstrb),
|
||||
.s_axi_wlast (ram_s_axi_wlast),
|
||||
.s_axi_wvalid (ram_s_axi_wvalid),
|
||||
.s_axi_wready (ram_s_axi_wready),
|
||||
.s_axi_bid (ram_s_axi_bid),
|
||||
.s_axi_bresp (ram_s_axi_bresp),
|
||||
.s_axi_bvalid (ram_s_axi_bvalid),
|
||||
.s_axi_bready (ram_s_axi_bready),
|
||||
.s_axi_arid (ram_s_axi_arid),
|
||||
.s_axi_araddr (ram_s_axi_araddr),
|
||||
.s_axi_arlen (ram_s_axi_arlen),
|
||||
.s_axi_arsize (ram_s_axi_arsize),
|
||||
.s_axi_arburst (ram_s_axi_arburst),
|
||||
.s_axi_arlock (ram_s_axi_arlock),
|
||||
.s_axi_arcache (ram_s_axi_arcache),
|
||||
.s_axi_arprot (ram_s_axi_arprot),
|
||||
.s_axi_arvalid (ram_s_axi_arvalid),
|
||||
.s_axi_arready (ram_s_axi_arready),
|
||||
.s_axi_rid (ram_s_axi_rid),
|
||||
.s_axi_rdata (ram_s_axi_rdata),
|
||||
.s_axi_rresp (ram_s_axi_rresp),
|
||||
.s_axi_rlast (ram_s_axi_rlast),
|
||||
.s_axi_rvalid (ram_s_axi_rvalid),
|
||||
.s_axi_rready (ram_s_axi_rready)
|
||||
);
|
||||
|
||||
endmodule
|
||||
189
axi/axi_reg/axi4l_reg_map.sv
Normal file
189
axi/axi_reg/axi4l_reg_map.sv
Normal file
@ -0,0 +1,189 @@
|
||||
module axi4l_reg_map #(
|
||||
parameter int unsigned ADDR_W = 16,
|
||||
parameter int unsigned DATA_W = 32,
|
||||
parameter int unsigned USER_W = 1,
|
||||
parameter int unsigned N_REGS = 4,
|
||||
|
||||
parameter logic [N_REGS-1:0][31:0][2:0] REG_MODE = '{default:'0},
|
||||
parameter logic [N_REGS-1:0][31:0] REG_RST = '{default:'0}
|
||||
)(
|
||||
input logic clk,
|
||||
input logic rst_n,
|
||||
axi4l_if.slave s_axil,
|
||||
|
||||
input logic [N_REGS-1:0][31:0] reg_i,
|
||||
output logic [N_REGS-1:0][31:0] reg_o
|
||||
);
|
||||
import axi_pkg::*;
|
||||
|
||||
typedef enum logic [2:0] {
|
||||
REG_BIT_RSVD = 3'd0,
|
||||
REG_BIT_RO = 3'd1,
|
||||
REG_BIT_RW = 3'd2,
|
||||
REG_BIT_W1S = 3'd3,
|
||||
REG_BIT_W1C = 3'd4
|
||||
} reg_bit_mode_t;
|
||||
|
||||
localparam int unsigned STRB_W = DATA_W/8;
|
||||
localparam int unsigned ADDR_LSB = $clog2(DATA_W/8);
|
||||
localparam int unsigned REG_INDEX_W = (N_REGS <= 1) ? 1 : $clog2(N_REGS);
|
||||
|
||||
logic [ADDR_W-1:0] awaddr_q;
|
||||
logic aw_seen_q;
|
||||
logic [DATA_W-1:0] wdata_q;
|
||||
logic [STRB_W-1:0] wstrb_q;
|
||||
logic w_seen_q;
|
||||
|
||||
logic bvalid_q;
|
||||
logic [1:0] bresp_q;
|
||||
|
||||
logic rvalid_q;
|
||||
logic [1:0] rresp_q;
|
||||
logic [DATA_W-1:0] rdata_q;
|
||||
|
||||
logic [REG_INDEX_W-1:0] wr_idx;
|
||||
logic [REG_INDEX_W-1:0] rd_idx;
|
||||
logic wr_addr_valid;
|
||||
logic rd_addr_valid;
|
||||
|
||||
integer b;
|
||||
logic [31:0] wr_mask;
|
||||
logic [31:0] wr_data32;
|
||||
logic [31:0] rw_cur;
|
||||
logic [31:0] rw_new;
|
||||
logic [31:0] rd_word;
|
||||
|
||||
always_comb begin
|
||||
wr_idx = '0;
|
||||
rd_idx = '0;
|
||||
wr_addr_valid = 1'b0;
|
||||
rd_addr_valid = 1'b0;
|
||||
|
||||
if (awaddr_q[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W] < N_REGS) begin
|
||||
wr_idx = awaddr_q[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W];
|
||||
wr_addr_valid = 1'b1;
|
||||
end
|
||||
|
||||
if (s_axil.req.ar.addr[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W] < N_REGS) begin
|
||||
rd_idx = s_axil.req.ar.addr[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W];
|
||||
rd_addr_valid = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
wr_mask = '0;
|
||||
for (int k = 0; k < STRB_W; k++) begin
|
||||
wr_mask[k*8 +: 8] = {8{wstrb_q[k]}};
|
||||
end
|
||||
wr_data32 = wdata_q[31:0];
|
||||
end
|
||||
|
||||
assign s_axil.resp.aw_ready = !aw_seen_q && !bvalid_q;
|
||||
assign s_axil.resp.w_ready = !w_seen_q && !bvalid_q;
|
||||
assign s_axil.resp.ar_ready = !rvalid_q;
|
||||
|
||||
assign s_axil.resp.b.valid = bvalid_q;
|
||||
assign s_axil.resp.b.resp = axi_resp_t'(bresp_q);
|
||||
assign s_axil.resp.b.user = '0;
|
||||
|
||||
assign s_axil.resp.r.valid = rvalid_q;
|
||||
assign s_axil.resp.r.resp = axi_resp_t'(rresp_q);
|
||||
assign s_axil.resp.r.data = rdata_q;
|
||||
assign s_axil.resp.r.user = '0;
|
||||
|
||||
always_ff @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
awaddr_q <= '0;
|
||||
aw_seen_q <= 1'b0;
|
||||
wdata_q <= '0;
|
||||
wstrb_q <= '0;
|
||||
w_seen_q <= 1'b0;
|
||||
bvalid_q <= 1'b0;
|
||||
bresp_q <= 2'b00;
|
||||
rvalid_q <= 1'b0;
|
||||
rresp_q <= 2'b00;
|
||||
rdata_q <= '0;
|
||||
reg_o <= REG_RST;
|
||||
end else begin
|
||||
for (int r = 0; r < N_REGS; r++) begin
|
||||
for (int bit_idx = 0; bit_idx < 32; bit_idx++) begin
|
||||
if (reg_bit_mode_t'(REG_MODE[r][bit_idx]) == REG_BIT_W1S)
|
||||
reg_o[r][bit_idx] <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (s_axil.req.aw.valid && s_axil.resp.aw_ready) begin
|
||||
awaddr_q <= s_axil.req.aw.addr;
|
||||
aw_seen_q <= 1'b1;
|
||||
end
|
||||
|
||||
if (s_axil.req.w.valid && s_axil.resp.w_ready) begin
|
||||
wdata_q <= s_axil.req.w.data;
|
||||
wstrb_q <= s_axil.req.w.strb;
|
||||
w_seen_q <= 1'b1;
|
||||
end
|
||||
|
||||
if (aw_seen_q && w_seen_q && !bvalid_q) begin
|
||||
bvalid_q <= 1'b1;
|
||||
bresp_q <= 2'b00;
|
||||
|
||||
if (!wr_addr_valid) begin
|
||||
bresp_q <= 2'b10;
|
||||
end else begin
|
||||
rw_cur = reg_o[wr_idx];
|
||||
rw_new = rw_cur;
|
||||
|
||||
for (b = 0; b < 32; b = b + 1) begin
|
||||
if (wr_mask[b]) begin
|
||||
unique case (reg_bit_mode_t'(REG_MODE[wr_idx][b]))
|
||||
REG_BIT_RSVD: begin end
|
||||
REG_BIT_RO : begin bresp_q <= 2'b10; end
|
||||
REG_BIT_RW : rw_new[b] = wr_data32[b];
|
||||
REG_BIT_W1S : if (wr_data32[b]) rw_new[b] = 1'b1;
|
||||
REG_BIT_W1C : if (wr_data32[b]) rw_new[b] = 1'b0;
|
||||
default : begin end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
reg_o[wr_idx] <= rw_new;
|
||||
end
|
||||
|
||||
aw_seen_q <= 1'b0;
|
||||
w_seen_q <= 1'b0;
|
||||
end
|
||||
|
||||
if (bvalid_q && s_axil.req.b_ready) begin
|
||||
bvalid_q <= 1'b0;
|
||||
end
|
||||
|
||||
if (s_axil.req.ar.valid && s_axil.resp.ar_ready) begin
|
||||
rvalid_q <= 1'b1;
|
||||
rresp_q <= 2'b00;
|
||||
rd_word = '0;
|
||||
|
||||
if (!rd_addr_valid) begin
|
||||
rresp_q <= 2'b10;
|
||||
end else begin
|
||||
for (b = 0; b < 32; b = b + 1) begin
|
||||
unique case (reg_bit_mode_t'(REG_MODE[rd_idx][b]))
|
||||
REG_BIT_RSVD: rd_word[b] = 1'b0;
|
||||
REG_BIT_RO : rd_word[b] = reg_i[rd_idx][b];
|
||||
REG_BIT_RW : rd_word[b] = reg_o[rd_idx][b];
|
||||
REG_BIT_W1S : rd_word[b] = 1'b0;
|
||||
REG_BIT_W1C : rd_word[b] = reg_o[rd_idx][b];
|
||||
default : rd_word[b] = 1'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
rdata_q <= rd_word;
|
||||
end
|
||||
|
||||
if (rvalid_q && s_axil.req.r_ready) begin
|
||||
rvalid_q <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
60
axi/axi_reg/axi4l_reg_map_example.sv
Normal file
60
axi/axi_reg/axi4l_reg_map_example.sv
Normal file
@ -0,0 +1,60 @@
|
||||
module axi4l_reg_map_example #(
|
||||
parameter int unsigned ADDR_W = 16,
|
||||
parameter int unsigned DATA_W = 32,
|
||||
parameter int unsigned USER_W = 1
|
||||
)(
|
||||
input logic clk,
|
||||
input logic rst_n,
|
||||
axi4l_if.slave s_axil,
|
||||
|
||||
output logic start_o,
|
||||
output logic enable_o,
|
||||
input logic busy_i,
|
||||
input logic [7:0] error_code_i
|
||||
);
|
||||
import axi4l_reg_map_example_pkg::*;
|
||||
|
||||
localparam int unsigned N_REGS = AXI4L_REG_MAP_EXAMPLE_N_REGS;
|
||||
|
||||
logic [N_REGS-1:0][31:0] reg_i;
|
||||
logic [N_REGS-1:0][31:0] reg_o;
|
||||
logic [N_REGS-1:0][31:0] reg_pulse;
|
||||
|
||||
axi4l_reg_map #(
|
||||
.ADDR_W (ADDR_W),
|
||||
.DATA_W (DATA_W),
|
||||
.USER_W (USER_W),
|
||||
.N_REGS (N_REGS),
|
||||
.REG_MODE(AXI4L_REG_MAP_EXAMPLE_REG_MODE),
|
||||
.REG_RST (AXI4L_REG_MAP_EXAMPLE_REG_RST)
|
||||
) u_reg_map (
|
||||
.clk (clk),
|
||||
.rst_n (rst_n),
|
||||
.s_axil (s_axil),
|
||||
.reg_i (reg_i),
|
||||
.reg_o (reg_o),
|
||||
.reg_pulse(reg_pulse)
|
||||
);
|
||||
|
||||
always_comb begin
|
||||
reg_i = '0;
|
||||
|
||||
// REG1 @ 0x04: status register
|
||||
// bit 0 : busy (RO)
|
||||
reg_i[1][0] = busy_i;
|
||||
|
||||
// REG2 @ 0x08: error register
|
||||
// bits 7:0: error_code (RO)
|
||||
reg_i[2][7:0] = error_code_i;
|
||||
end
|
||||
|
||||
// REG0 @ 0x00: control register
|
||||
// bit 0 : start (W1S pulse)
|
||||
// bit 1 : enable (RW)
|
||||
assign start_o = reg_pulse[0][0];
|
||||
assign enable_o = reg_o[0][1];
|
||||
|
||||
// REG3 @ 0x0C: generic configuration register (RW)
|
||||
// reg_o[3] can be manually connected later if needed.
|
||||
|
||||
endmodule
|
||||
35
axi/axi_reg/axi4l_reg_map_example_pkg.sv
Normal file
35
axi/axi_reg/axi4l_reg_map_example_pkg.sv
Normal file
@ -0,0 +1,35 @@
|
||||
package axi4l_reg_map_example_pkg;
|
||||
|
||||
localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 4;
|
||||
|
||||
localparam logic [2:0] REG_BIT_RSVD = 3'd0;
|
||||
localparam logic [2:0] REG_BIT_RO = 3'd1;
|
||||
localparam logic [2:0] REG_BIT_RW = 3'd2;
|
||||
localparam logic [2:0] REG_BIT_W1S = 3'd3;
|
||||
|
||||
localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0][2:0] AXI4L_REG_MAP_EXAMPLE_REG_MODE = '{
|
||||
'{
|
||||
REG_BIT_W1S,
|
||||
REG_BIT_RW,
|
||||
default: REG_BIT_RSVD
|
||||
},
|
||||
'{
|
||||
REG_BIT_RO,
|
||||
default: REG_BIT_RSVD
|
||||
},
|
||||
'{
|
||||
REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
|
||||
REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
|
||||
default: REG_BIT_RSVD
|
||||
},
|
||||
'{default: REG_BIT_RW}
|
||||
};
|
||||
|
||||
localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0] AXI4L_REG_MAP_EXAMPLE_REG_RST = '{
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0001
|
||||
};
|
||||
|
||||
endpackage
|
||||
37
axi/axi_reg/dma_axil_reg_map_pkg.sv
Normal file
37
axi/axi_reg/dma_axil_reg_map_pkg.sv
Normal file
@ -0,0 +1,37 @@
|
||||
package dma_axil_reg_map_pkg;
|
||||
|
||||
localparam int unsigned DMA_AXIL_REG_MAP_N_REGS = 4;
|
||||
|
||||
localparam logic [2:0] REG_BIT_RSVD = 3'd0;
|
||||
localparam logic [2:0] REG_BIT_RO = 3'd1;
|
||||
localparam logic [2:0] REG_BIT_RW = 3'd2;
|
||||
localparam logic [2:0] REG_BIT_W1S = 3'd3;
|
||||
localparam logic [2:0] REG_BIT_W1C = 3'd4;
|
||||
|
||||
localparam DMA_WRITE_DESC_CONTROL_REG = 0;
|
||||
localparam DMA_WRITE_DESC_ADDR_REG = 1;
|
||||
localparam DMA_WRITE_DESC_LEN_REG = 2;
|
||||
localparam DMA_READ_DESC_CONTROL_REG = 3;
|
||||
localparam DMA_READ_DESC_ADDR_REG = 4;
|
||||
localparam DMA_READ_DESC_LEN_REG = 5;
|
||||
|
||||
localparam logic [DMA_AXIL_REG_MAP_N_REGS-1:0][31:0][2:0] DMA_AXIL_REG_MAP_REG_MODE = '{
|
||||
|
||||
'{REG_BIT_RO, REG_BIT_W1S, default: REG_BIT_RSVD},
|
||||
'{32{REG_BIT_RW}, default: REG_BIT_RSVD},
|
||||
'{32{REG_BIT_RW}, default: REG_BIT_RSVD},
|
||||
'{REG_BIT_RO, REG_BIT_W1S, default: REG_BIT_RSVD},
|
||||
'{32{REG_BIT_RW}, default: REG_BIT_RSVD},
|
||||
'{32{REG_BIT_RW}, default: REG_BIT_RSVD}
|
||||
};
|
||||
|
||||
localparam logic [DMA_AXIL_REG_MAP_N_REGS-1:0][31:0] DMA_AXIL_REG_MAP_REG_RST = '{
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000
|
||||
};
|
||||
|
||||
endpackage
|
||||
165
axi/axil_cdc_wrapper.sv
Normal file
165
axi/axil_cdc_wrapper.sv
Normal file
@ -0,0 +1,165 @@
|
||||
module axil_cdc_wrapper #(
|
||||
parameter int ADDR_WIDTH = 32
|
||||
parameter int DATA_WIDTH = 32,
|
||||
)(
|
||||
input wire s_clk,
|
||||
input wire s_rst,
|
||||
axi4l_if.slave s_axi,
|
||||
|
||||
input wire m_clk,
|
||||
input wire m_rst,
|
||||
axi4l_if.master m_axi
|
||||
);
|
||||
|
||||
localparam int STRB_WIDTH = (DATA_WIDTH/8);
|
||||
wire [ADDR_WIDTH-1:0] cdc_s_axil_awaddr;
|
||||
wire [2:0] cdc_s_axil_awprot;
|
||||
wire cdc_s_axil_awvalid;
|
||||
wire cdc_s_axil_awready;
|
||||
wire [DATA_WIDTH-1:0] cdc_s_axil_wdata;
|
||||
wire [STRB_WIDTH-1:0] cdc_s_axil_wstrb;
|
||||
wire cdc_s_axil_wvalid;
|
||||
wire cdc_s_axil_wready;
|
||||
wire [1:0] cdc_s_axil_bresp;
|
||||
wire cdc_s_axil_bvalid;
|
||||
wire cdc_s_axil_bready;
|
||||
wire [ADDR_WIDTH-1:0] cdc_s_axil_araddr;
|
||||
wire [2:0] cdc_s_axil_arprot;
|
||||
wire cdc_s_axil_arvalid;
|
||||
wire cdc_s_axil_arready;
|
||||
wire [DATA_WIDTH-1:0] cdc_s_axil_rdata;
|
||||
wire [1:0] cdc_s_axil_rresp;
|
||||
wire cdc_s_axil_rvalid;
|
||||
wire cdc_s_axil_rready;
|
||||
wire [ADDR_WIDTH-1:0] cdc_m_axil_awaddr;
|
||||
wire [2:0] cdc_m_axil_awprot;
|
||||
wire cdc_m_axil_awvalid;
|
||||
wire cdc_m_axil_awready;
|
||||
wire [DATA_WIDTH-1:0] cdc_m_axil_wdata;
|
||||
wire [STRB_WIDTH-1:0] cdc_m_axil_wstrb;
|
||||
wire cdc_m_axil_wvalid;
|
||||
wire cdc_m_axil_wready;
|
||||
wire [1:0] cdc_m_axil_bresp;
|
||||
wire cdc_m_axil_bvalid;
|
||||
wire cdc_m_axil_bready;
|
||||
wire [ADDR_WIDTH-1:0] cdc_m_axil_araddr;
|
||||
wire [2:0] cdc_m_axil_arprot;
|
||||
wire cdc_m_axil_arvalid;
|
||||
wire cdc_m_axil_arready;
|
||||
wire [DATA_WIDTH-1:0] cdc_m_axil_rdata;
|
||||
wire [1:0] cdc_m_axil_rresp;
|
||||
wire cdc_m_axil_rvalid;
|
||||
wire cdc_m_axil_rready;
|
||||
|
||||
axi4l_if_to_flat #(
|
||||
.ADDR_W (ADDR_WIDTH),
|
||||
.DATA_W (DATA_WIDTH)
|
||||
) i_axi4l_if_to_flat (
|
||||
.s_axil (s_axi),
|
||||
.m_axil_awaddr (cdc_m_axil_awaddr),
|
||||
.m_axil_awprot (cdc_m_axil_awprot),
|
||||
.m_axil_awuser (cdc_m_axil_awuser),
|
||||
.m_axil_awvalid (cdc_m_axil_awvalid),
|
||||
.m_axil_awready (cdc_m_axil_awready),
|
||||
.m_axil_wdata (cdc_m_axil_wdata),
|
||||
.m_axil_wstrb (cdc_m_axil_wstrb),
|
||||
.m_axil_wuser (cdc_m_axil_wuser),
|
||||
.m_axil_wvalid (cdc_m_axil_wvalid),
|
||||
.m_axil_wready (cdc_m_axil_wready),
|
||||
.m_axil_bresp (cdc_m_axil_bresp),
|
||||
.m_axil_buser (cdc_m_axil_buser),
|
||||
.m_axil_bvalid (cdc_m_axil_bvalid),
|
||||
.m_axil_bready (cdc_m_axil_bready),
|
||||
.m_axil_araddr (cdc_m_axil_araddr),
|
||||
.m_axil_arprot (cdc_m_axil_arprot),
|
||||
.m_axil_aruser (cdc_m_axil_aruser),
|
||||
.m_axil_arvalid (cdc_m_axil_arvalid),
|
||||
.m_axil_arready (cdc_m_axil_arready),
|
||||
.m_axil_rdata (cdc_m_axil_rdata),
|
||||
.m_axil_rresp (cdc_m_axil_rresp),
|
||||
.m_axil_ruser (cdc_m_axil_ruser),
|
||||
.m_axil_rvalid (cdc_m_axil_rvalid),
|
||||
.m_axil_rready (cdc_m_axil_rready)
|
||||
);
|
||||
|
||||
axil_cdc #(
|
||||
.ADDR_WIDTH (ADDR_WIDTH)
|
||||
.DATA_WIDTH (DATA_WIDTH),
|
||||
) i_axil_cdc (
|
||||
.s_clk (s_clk),
|
||||
.s_rst (s_rst),
|
||||
.s_axil_awaddr (cdc_m_axil_awaddr),
|
||||
.s_axil_awprot (cdc_m_axil_awprot),
|
||||
.s_axil_awvalid (cdc_m_axil_awvalid),
|
||||
.s_axil_awready (cdc_m_axil_awready),
|
||||
.s_axil_wdata (cdc_m_axil_wdata),
|
||||
.s_axil_wstrb (cdc_m_axil_wstrb),
|
||||
.s_axil_wvalid (cdc_m_axil_wvalid),
|
||||
.s_axil_wready (cdc_m_axil_wready),
|
||||
.s_axil_bresp (cdc_m_axil_bresp),
|
||||
.s_axil_bvalid (cdc_m_axil_bvalid),
|
||||
.s_axil_bready (cdc_m_axil_bready),
|
||||
.s_axil_araddr (cdc_m_axil_araddr),
|
||||
.s_axil_arprot (cdc_m_axil_arprot),
|
||||
.s_axil_arvalid (cdc_m_axil_arvalid),
|
||||
.s_axil_arready (cdc_m_axil_arready),
|
||||
.s_axil_rdata (cdc_m_axil_rdata),
|
||||
.s_axil_rresp (cdc_m_axil_rresp),
|
||||
.s_axil_rvalid (cdc_m_axil_rvalid),
|
||||
.s_axil_rready (cdc_m_axil_rready),
|
||||
|
||||
.m_clk (m_clk),
|
||||
.m_rst (m_rst),
|
||||
.m_axil_awaddr (cdc_s_axil_awaddr),
|
||||
.m_axil_awprot (cdc_s_axil_awprot),
|
||||
.m_axil_awvalid (cdc_s_axil_awvalid),
|
||||
.m_axil_awready (cdc_s_axil_awready),
|
||||
.m_axil_wdata (cdc_s_axil_wdata),
|
||||
.m_axil_wstrb (cdc_s_axil_wstrb),
|
||||
.m_axil_wvalid (cdc_s_axil_wvalid),
|
||||
.m_axil_wready (cdc_s_axil_wready),
|
||||
.m_axil_bresp (cdc_s_axil_bresp),
|
||||
.m_axil_bvalid (cdc_s_axil_bvalid),
|
||||
.m_axil_bready (cdc_s_axil_bready),
|
||||
.m_axil_araddr (cdc_s_axil_araddr),
|
||||
.m_axil_arprot (cdc_s_axil_arprot),
|
||||
.m_axil_arvalid (cdc_s_axil_arvalid),
|
||||
.m_axil_arready (cdc_s_axil_arready),
|
||||
.m_axil_rdata (cdc_s_axil_rdata),
|
||||
.m_axil_rresp (cdc_s_axil_rresp),
|
||||
.m_axil_rvalid (cdc_s_axil_rvalid),
|
||||
.m_axil_rready (cdc_s_axil_rready)
|
||||
);
|
||||
|
||||
axi4l_flat_to_if #(
|
||||
.ADDR_W (ADDR_WIDTH),
|
||||
.DATA_W (DATA_WIDTH)
|
||||
) i_axi4l_flat_to_if (
|
||||
.s_axil_awaddr (cdc_s_axil_awaddr),
|
||||
.s_axil_awprot (cdc_s_axil_awprot),
|
||||
.s_axil_awuser (cdc_s_axil_awuser),
|
||||
.s_axil_awvalid (cdc_s_axil_awvalid),
|
||||
.s_axil_awready (cdc_s_axil_awready),
|
||||
.s_axil_wdata (cdc_s_axil_wdata),
|
||||
.s_axil_wstrb (cdc_s_axil_wstrb),
|
||||
.s_axil_wuser (cdc_s_axil_wuser),
|
||||
.s_axil_wvalid (cdc_s_axil_wvalid),
|
||||
.s_axil_wready (cdc_s_axil_wready),
|
||||
.s_axil_bresp (cdc_s_axil_bresp),
|
||||
.s_axil_buser (cdc_s_axil_buser),
|
||||
.s_axil_bvalid (cdc_s_axil_bvalid),
|
||||
.s_axil_bready (cdc_s_axil_bready),
|
||||
.s_axil_araddr (cdc_s_axil_araddr),
|
||||
.s_axil_arprot (cdc_s_axil_arprot),
|
||||
.s_axil_aruser (cdc_s_axil_aruser),
|
||||
.s_axil_arvalid (cdc_s_axil_arvalid),
|
||||
.s_axil_arready (cdc_s_axil_arready),
|
||||
.s_axil_rdata (cdc_s_axil_rdata),
|
||||
.s_axil_rresp (cdc_s_axil_rresp),
|
||||
.s_axil_ruser (cdc_s_axil_ruser),
|
||||
.s_axil_rvalid (cdc_s_axil_rvalid),
|
||||
.s_axil_rready (cdc_s_axil_rready),
|
||||
.m_axil (m_axil)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user