From 338f30c0d7224feb55a37be725a00f38dce53583 Mon Sep 17 00:00:00 2001 From: Phil Date: Thu, 28 May 2026 16:41:26 +0300 Subject: [PATCH] rtl: add AXI if defines --- axi/axi4_flat_to_if.sv | 97 ++ axi/axi4_if_to_flat.sv | 97 ++ axi/axi4l_flat_to_if.sv | 58 ++ axi/axi4l_if_to_flat.sv | 56 ++ axi/axi4l_reg_map.sv | 189 ++++ axi/axi4l_to_axi4.sv | 59 ++ axi/axi_crossbar_core_wrapper.sv | 654 ++++++++++++++ axi/axi_crossbar_wrapper.sv | 1045 ++++++++++++++++++++++ axi/axi_dma_wrapper.sv | 309 +++++++ axi/axi_if.sv | 43 + axi/axi_pkg.sv | 140 +++ axi/axi_ram_wrapper.sv | 146 +++ axi/axi_reg/axi4l_reg_map.sv | 189 ++++ axi/axi_reg/axi4l_reg_map_example.sv | 60 ++ axi/axi_reg/axi4l_reg_map_example_pkg.sv | 35 + axi/axi_reg/dma_axil_reg_map_pkg.sv | 37 + axi/axil_cdc_wrapper.sv | 165 ++++ 17 files changed, 3379 insertions(+) create mode 100644 axi/axi4_flat_to_if.sv create mode 100644 axi/axi4_if_to_flat.sv create mode 100644 axi/axi4l_flat_to_if.sv create mode 100644 axi/axi4l_if_to_flat.sv create mode 100644 axi/axi4l_reg_map.sv create mode 100644 axi/axi4l_to_axi4.sv create mode 100644 axi/axi_crossbar_core_wrapper.sv create mode 100644 axi/axi_crossbar_wrapper.sv create mode 100644 axi/axi_dma_wrapper.sv create mode 100644 axi/axi_if.sv create mode 100644 axi/axi_pkg.sv create mode 100644 axi/axi_ram_wrapper.sv create mode 100644 axi/axi_reg/axi4l_reg_map.sv create mode 100644 axi/axi_reg/axi4l_reg_map_example.sv create mode 100644 axi/axi_reg/axi4l_reg_map_example_pkg.sv create mode 100644 axi/axi_reg/dma_axil_reg_map_pkg.sv create mode 100644 axi/axil_cdc_wrapper.sv diff --git a/axi/axi4_flat_to_if.sv b/axi/axi4_flat_to_if.sv new file mode 100644 index 0000000..31fe4c2 --- /dev/null +++ b/axi/axi4_flat_to_if.sv @@ -0,0 +1,97 @@ +module axi4_flat_to_if #( + parameter int unsigned ADDR_W = 32, + parameter int unsigned DATA_W = 64, + parameter int unsigned ID_W = 4, + parameter int unsigned USER_W = 1 +)( + input logic [ID_W-1:0] s_axi_awid, + input logic [ADDR_W-1:0] s_axi_awaddr, + input logic [7:0] s_axi_awlen, + input logic [2:0] s_axi_awsize, + input logic [1:0] s_axi_awburst, + input logic s_axi_awlock, + input logic [3:0] s_axi_awcache, + input logic [2:0] s_axi_awprot, + input logic [3:0] s_axi_awqos, + input logic [3:0] s_axi_awregion, + input logic [USER_W-1:0] s_axi_awuser, + input logic s_axi_awvalid, + output logic s_axi_awready, + input logic [DATA_W-1:0] s_axi_wdata, + input logic [DATA_W/8-1:0] s_axi_wstrb, + input logic s_axi_wlast, + input logic [USER_W-1:0] s_axi_wuser, + input logic s_axi_wvalid, + output logic s_axi_wready, + output logic [ID_W-1:0] s_axi_bid, + output logic [1:0] s_axi_bresp, + output logic [USER_W-1:0] s_axi_buser, + output logic s_axi_bvalid, + input logic s_axi_bready, + input logic [ID_W-1:0] s_axi_arid, + input logic [ADDR_W-1:0] s_axi_araddr, + input logic [7:0] s_axi_arlen, + input logic [2:0] s_axi_arsize, + input logic [1:0] s_axi_arburst, + input logic s_axi_arlock, + input logic [3:0] s_axi_arcache, + input logic [2:0] s_axi_arprot, + input logic [3:0] s_axi_arqos, + input logic [3:0] s_axi_arregion, + input logic [USER_W-1:0] s_axi_aruser, + input logic s_axi_arvalid, + output logic s_axi_arready, + output logic [ID_W-1:0] s_axi_rid, + output logic [DATA_W-1:0] s_axi_rdata, + output logic [1:0] s_axi_rresp, + output logic s_axi_rlast, + output logic [USER_W-1:0] s_axi_ruser, + output logic s_axi_rvalid, + input logic s_axi_rready, + axi4_if.master m_axi +); + assign m_axi.req.aw.id = s_axi_awid; + assign m_axi.req.aw.addr = s_axi_awaddr; + assign m_axi.req.aw.len = s_axi_awlen; + assign m_axi.req.aw.size = s_axi_awsize; + assign m_axi.req.aw.burst = axi_pkg::axi_burst_t'(s_axi_awburst); + assign m_axi.req.aw.lock = s_axi_awlock; + assign m_axi.req.aw.cache = s_axi_awcache; + assign m_axi.req.aw.prot = s_axi_awprot; + assign m_axi.req.aw.qos = s_axi_awqos; + assign m_axi.req.aw.region = s_axi_awregion; + assign m_axi.req.aw.user = s_axi_awuser; + assign m_axi.req.aw.valid = s_axi_awvalid; + assign s_axi_awready = m_axi.resp.aw_ready; + assign m_axi.req.w.data = s_axi_wdata; + assign m_axi.req.w.strb = s_axi_wstrb; + assign m_axi.req.w.last = s_axi_wlast; + assign m_axi.req.w.user = s_axi_wuser; + assign m_axi.req.w.valid = s_axi_wvalid; + assign s_axi_wready = m_axi.resp.w_ready; + assign s_axi_bid = m_axi.resp.b.id; + assign s_axi_bresp = m_axi.resp.b.resp; + assign s_axi_buser = m_axi.resp.b.user; + assign s_axi_bvalid = m_axi.resp.b.valid; + assign m_axi.req.b_ready = s_axi_bready; + assign m_axi.req.ar.id = s_axi_arid; + assign m_axi.req.ar.addr = s_axi_araddr; + assign m_axi.req.ar.len = s_axi_arlen; + assign m_axi.req.ar.size = s_axi_arsize; + assign m_axi.req.ar.burst = axi_pkg::axi_burst_t'(s_axi_arburst); + assign m_axi.req.ar.lock = s_axi_arlock; + assign m_axi.req.ar.cache = s_axi_arcache; + assign m_axi.req.ar.prot = s_axi_arprot; + assign m_axi.req.ar.qos = s_axi_arqos; + assign m_axi.req.ar.region = s_axi_arregion; + assign m_axi.req.ar.user = s_axi_aruser; + assign m_axi.req.ar.valid = s_axi_arvalid; + assign s_axi_arready = m_axi.resp.ar_ready; + assign s_axi_rid = m_axi.resp.r.id; + assign s_axi_rdata = m_axi.resp.r.data; + assign s_axi_rresp = m_axi.resp.r.resp; + assign s_axi_rlast = m_axi.resp.r.last; + assign s_axi_ruser = m_axi.resp.r.user; + assign s_axi_rvalid = m_axi.resp.r.valid; + assign m_axi.req.r_ready = s_axi_rready; +endmodule diff --git a/axi/axi4_if_to_flat.sv b/axi/axi4_if_to_flat.sv new file mode 100644 index 0000000..b6c8ec4 --- /dev/null +++ b/axi/axi4_if_to_flat.sv @@ -0,0 +1,97 @@ +module axi4_if_to_flat #( + parameter int unsigned ADDR_W = 32, + parameter int unsigned DATA_W = 64, + parameter int unsigned ID_W = 4, + parameter int unsigned USER_W = 1 +)( + axi4_if.slave s_axi, + output logic [ID_W-1:0] m_axi_awid, + output logic [ADDR_W-1:0] m_axi_awaddr, + output logic [7:0] m_axi_awlen, + output logic [2:0] m_axi_awsize, + output logic [1:0] m_axi_awburst, + output logic m_axi_awlock, + output logic [3:0] m_axi_awcache, + output logic [2:0] m_axi_awprot, + output logic [3:0] m_axi_awqos, + output logic [3:0] m_axi_awregion, + output logic [USER_W-1:0] m_axi_awuser, + output logic m_axi_awvalid, + input logic m_axi_awready, + output logic [DATA_W-1:0] m_axi_wdata, + output logic [DATA_W/8-1:0] m_axi_wstrb, + output logic m_axi_wlast, + output logic [USER_W-1:0] m_axi_wuser, + output logic m_axi_wvalid, + input logic m_axi_wready, + input logic [ID_W-1:0] m_axi_bid, + input logic [1:0] m_axi_bresp, + input logic [USER_W-1:0] m_axi_buser, + input logic m_axi_bvalid, + output logic m_axi_bready, + output logic [ID_W-1:0] m_axi_arid, + output logic [ADDR_W-1:0] m_axi_araddr, + output logic [7:0] m_axi_arlen, + output logic [2:0] m_axi_arsize, + output logic [1:0] m_axi_arburst, + output logic m_axi_arlock, + output logic [3:0] m_axi_arcache, + output logic [2:0] m_axi_arprot, + output logic [3:0] m_axi_arqos, + output logic [3:0] m_axi_arregion, + output logic [USER_W-1:0] m_axi_aruser, + output logic m_axi_arvalid, + input logic m_axi_arready, + input logic [ID_W-1:0] m_axi_rid, + input logic [DATA_W-1:0] m_axi_rdata, + input logic [1:0] m_axi_rresp, + input logic m_axi_rlast, + input logic [USER_W-1:0] m_axi_ruser, + input logic m_axi_rvalid, + output logic m_axi_rready +); + assign m_axi_awid = s_axi.req.aw.id; + assign m_axi_awaddr = s_axi.req.aw.addr; + assign m_axi_awlen = s_axi.req.aw.len; + assign m_axi_awsize = s_axi.req.aw.size; + assign m_axi_awburst = s_axi.req.aw.burst; + assign m_axi_awlock = s_axi.req.aw.lock; + assign m_axi_awcache = s_axi.req.aw.cache; + assign m_axi_awprot = s_axi.req.aw.prot; + assign m_axi_awqos = s_axi.req.aw.qos; + assign m_axi_awregion = s_axi.req.aw.region; + assign m_axi_awuser = s_axi.req.aw.user; + assign m_axi_awvalid = s_axi.req.aw.valid; + assign s_axi.resp.aw_ready = m_axi_awready; + assign m_axi_wdata = s_axi.req.w.data; + assign m_axi_wstrb = s_axi.req.w.strb; + assign m_axi_wlast = s_axi.req.w.last; + assign m_axi_wuser = s_axi.req.w.user; + assign m_axi_wvalid = s_axi.req.w.valid; + assign s_axi.resp.w_ready = m_axi_wready; + assign s_axi.resp.b.id = m_axi_bid; + assign s_axi.resp.b.resp = axi_pkg::axi_resp_t'(m_axi_bresp); + assign s_axi.resp.b.user = m_axi_buser; + assign s_axi.resp.b.valid= m_axi_bvalid; + assign m_axi_bready = s_axi.req.b_ready; + assign m_axi_arid = s_axi.req.ar.id; + assign m_axi_araddr = s_axi.req.ar.addr; + assign m_axi_arlen = s_axi.req.ar.len; + assign m_axi_arsize = s_axi.req.ar.size; + assign m_axi_arburst = s_axi.req.ar.burst; + assign m_axi_arlock = s_axi.req.ar.lock; + assign m_axi_arcache = s_axi.req.ar.cache; + assign m_axi_arprot = s_axi.req.ar.prot; + assign m_axi_arqos = s_axi.req.ar.qos; + assign m_axi_arregion = s_axi.req.ar.region; + assign m_axi_aruser = s_axi.req.ar.user; + assign m_axi_arvalid = s_axi.req.ar.valid; + assign s_axi.resp.ar_ready = m_axi_arready; + assign s_axi.resp.r.id = m_axi_rid; + assign s_axi.resp.r.data = m_axi_rdata; + assign s_axi.resp.r.resp = axi_pkg::axi_resp_t'(m_axi_rresp); + assign s_axi.resp.r.last = m_axi_rlast; + assign s_axi.resp.r.user = m_axi_ruser; + assign s_axi.resp.r.valid= m_axi_rvalid; + assign m_axi_rready = s_axi.req.r_ready; +endmodule diff --git a/axi/axi4l_flat_to_if.sv b/axi/axi4l_flat_to_if.sv new file mode 100644 index 0000000..982e915 --- /dev/null +++ b/axi/axi4l_flat_to_if.sv @@ -0,0 +1,58 @@ +module axi4l_flat_to_if #( + parameter int unsigned ADDR_W = 32, + parameter int unsigned DATA_W = 32, + parameter int unsigned USER_W = 1 +)( + input logic aclk, + input logic aresetn, + input logic [ADDR_W-1:0] s_axil_awaddr, + input logic [2:0] s_axil_awprot, + input logic [USER_W-1:0] s_axil_awuser, + input logic s_axil_awvalid, + output logic s_axil_awready, + input logic [DATA_W-1:0] s_axil_wdata, + input logic [DATA_W/8-1:0] s_axil_wstrb, + input logic [USER_W-1:0] s_axil_wuser, + input logic s_axil_wvalid, + output logic s_axil_wready, + output logic [1:0] s_axil_bresp, + output logic [USER_W-1:0] s_axil_buser, + output logic s_axil_bvalid, + input logic s_axil_bready, + input logic [ADDR_W-1:0] s_axil_araddr, + input logic [2:0] s_axil_arprot, + input logic [USER_W-1:0] s_axil_aruser, + input logic s_axil_arvalid, + output logic s_axil_arready, + output logic [DATA_W-1:0] s_axil_rdata, + output logic [1:0] s_axil_rresp, + output logic [USER_W-1:0] s_axil_ruser, + output logic s_axil_rvalid, + input logic s_axil_rready, + axi4l_if.master m_axil +); + assign m_axil.req.aw.addr = s_axil_awaddr; + assign m_axil.req.aw.prot = s_axil_awprot; + assign m_axil.req.aw.user = s_axil_awuser; + assign m_axil.req.aw.valid = s_axil_awvalid; + assign s_axil_awready = m_axil.resp.aw_ready; + assign m_axil.req.w.data = s_axil_wdata; + assign m_axil.req.w.strb = s_axil_wstrb; + assign m_axil.req.w.user = s_axil_wuser; + assign m_axil.req.w.valid = s_axil_wvalid; + assign s_axil_wready = m_axil.resp.w_ready; + assign s_axil_bresp = m_axil.resp.b.resp; + assign s_axil_buser = m_axil.resp.b.user; + assign s_axil_bvalid = m_axil.resp.b.valid; + assign m_axil.req.b_ready = s_axil_bready; + assign m_axil.req.ar.addr = s_axil_araddr; + assign m_axil.req.ar.prot = s_axil_arprot; + assign m_axil.req.ar.user = s_axil_aruser; + assign m_axil.req.ar.valid = s_axil_arvalid; + assign s_axil_arready = m_axil.resp.ar_ready; + assign s_axil_rdata = m_axil.resp.r.data; + assign s_axil_rresp = m_axil.resp.r.resp; + assign s_axil_ruser = m_axil.resp.r.user; + assign s_axil_rvalid = m_axil.resp.r.valid; + assign m_axil.req.r_ready = s_axil_rready; +endmodule diff --git a/axi/axi4l_if_to_flat.sv b/axi/axi4l_if_to_flat.sv new file mode 100644 index 0000000..6af2b1b --- /dev/null +++ b/axi/axi4l_if_to_flat.sv @@ -0,0 +1,56 @@ +module axi4l_if_to_flat #( + parameter int unsigned ADDR_W = 32, + parameter int unsigned DATA_W = 32, + parameter int unsigned USER_W = 1 +)( + axi4l_if.slave s_axil, + output logic [ADDR_W-1:0] m_axil_awaddr, + output logic [2:0] m_axil_awprot, + output logic [USER_W-1:0] m_axil_awuser, + output logic m_axil_awvalid, + input logic m_axil_awready, + output logic [DATA_W-1:0] m_axil_wdata, + output logic [DATA_W/8-1:0] m_axil_wstrb, + output logic [USER_W-1:0] m_axil_wuser, + output logic m_axil_wvalid, + input logic m_axil_wready, + input logic [1:0] m_axil_bresp, + input logic [USER_W-1:0] m_axil_buser, + input logic m_axil_bvalid, + output logic m_axil_bready, + output logic [ADDR_W-1:0] m_axil_araddr, + output logic [2:0] m_axil_arprot, + output logic [USER_W-1:0] m_axil_aruser, + output logic m_axil_arvalid, + input logic m_axil_arready, + input logic [DATA_W-1:0] m_axil_rdata, + input logic [1:0] m_axil_rresp, + input logic [USER_W-1:0] m_axil_ruser, + input logic m_axil_rvalid, + output logic m_axil_rready +); + assign m_axil_awaddr = s_axil.req.aw.addr; + assign m_axil_awprot = s_axil.req.aw.prot; + assign m_axil_awuser = s_axil.req.aw.user; + assign m_axil_awvalid = s_axil.req.aw.valid; + assign s_axil.resp.aw_ready = m_axil_awready; + assign m_axil_wdata = s_axil.req.w.data; + assign m_axil_wstrb = s_axil.req.w.strb; + assign m_axil_wuser = s_axil.req.w.user; + assign m_axil_wvalid = s_axil.req.w.valid; + assign s_axil.resp.w_ready = m_axil_wready; + assign s_axil.resp.b.resp = axi_pkg::axi_resp_t'(m_axil_bresp); + assign s_axil.resp.b.user = m_axil_buser; + assign s_axil.resp.b.valid = m_axil_bvalid; + assign m_axil_bready = s_axil.req.b_ready; + assign m_axil_araddr = s_axil.req.ar.addr; + assign m_axil_arprot = s_axil.req.ar.prot; + assign m_axil_aruser = s_axil.req.ar.user; + assign m_axil_arvalid = s_axil.req.ar.valid; + assign s_axil.resp.ar_ready = m_axil_arready; + assign s_axil.resp.r.data = m_axil_rdata; + assign s_axil.resp.r.resp = axi_pkg::axi_resp_t'(m_axil_rresp); + assign s_axil.resp.r.user = m_axil_ruser; + assign s_axil.resp.r.valid = m_axil_rvalid; + assign m_axil_rready = s_axil.req.r_ready; +endmodule diff --git a/axi/axi4l_reg_map.sv b/axi/axi4l_reg_map.sv new file mode 100644 index 0000000..36544a8 --- /dev/null +++ b/axi/axi4l_reg_map.sv @@ -0,0 +1,189 @@ +module axi4l_reg_map #( + parameter int unsigned ADDR_W = 16, + parameter int unsigned DATA_W = 32, + parameter int unsigned USER_W = 1, + parameter int unsigned N_REGS = 4, + + parameter logic [N_REGS-1:0][31:0][2:0] REG_MODE = '{default:'0}, + parameter logic [N_REGS-1:0][31:0] REG_RST = '{default:'0} +)( + input logic clk, + input logic rst_n, + axi4l_if.slave s_axil, + + input logic [N_REGS-1:0][31:0] reg_i, + output logic [N_REGS-1:0][31:0] reg_o +); + import axi_pkg::*; + + typedef enum logic [2:0] { + REG_BIT_RSVD = 3'd0, + REG_BIT_RO = 3'd1, + REG_BIT_RW = 3'd2, + REG_BIT_W1S = 3'd3, + REG_BIT_W1C = 3'd4 + } reg_bit_mode_t; + + localparam int unsigned STRB_W = DATA_W/8; + localparam int unsigned ADDR_LSB = $clog2(DATA_W/8); + localparam int unsigned REG_INDEX_W = (N_REGS <= 1) ? 1 : $clog2(N_REGS); + + logic [ADDR_W-1:0] awaddr_q; + logic aw_seen_q; + logic [DATA_W-1:0] wdata_q; + logic [STRB_W-1:0] wstrb_q; + logic w_seen_q; + + logic bvalid_q; + logic [1:0] bresp_q; + + logic rvalid_q; + logic [1:0] rresp_q; + logic [DATA_W-1:0] rdata_q; + + logic [REG_INDEX_W-1:0] wr_idx; + logic [REG_INDEX_W-1:0] rd_idx; + logic wr_addr_valid; + logic rd_addr_valid; + + integer b; + logic [31:0] wr_mask; + logic [31:0] wr_data32; + logic [31:0] rw_cur; + logic [31:0] rw_new; + logic [31:0] rd_word; + + always_comb begin + wr_idx = '0; + rd_idx = '0; + wr_addr_valid = 1'b0; + rd_addr_valid = 1'b0; + + if (awaddr_q[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W] < N_REGS) begin + wr_idx = awaddr_q[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W]; + wr_addr_valid = 1'b1; + end + + if (s_axil.req.ar.addr[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W] < N_REGS) begin + rd_idx = s_axil.req.ar.addr[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W]; + rd_addr_valid = 1'b1; + end + end + + always_comb begin + wr_mask = '0; + for (int k = 0; k < STRB_W; k++) begin + wr_mask[k*8 +: 8] = {8{wstrb_q[k]}}; + end + wr_data32 = wdata_q[31:0]; + end + + assign s_axil.resp.aw_ready = !aw_seen_q && !bvalid_q; + assign s_axil.resp.w_ready = !w_seen_q && !bvalid_q; + assign s_axil.resp.ar_ready = !rvalid_q; + + assign s_axil.resp.b.valid = bvalid_q; + assign s_axil.resp.b.resp = axi_resp_t'(bresp_q); + assign s_axil.resp.b.user = '0; + + assign s_axil.resp.r.valid = rvalid_q; + assign s_axil.resp.r.resp = axi_resp_t'(rresp_q); + assign s_axil.resp.r.data = rdata_q; + assign s_axil.resp.r.user = '0; + + always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + awaddr_q <= '0; + aw_seen_q <= 1'b0; + wdata_q <= '0; + wstrb_q <= '0; + w_seen_q <= 1'b0; + bvalid_q <= 1'b0; + bresp_q <= 2'b00; + rvalid_q <= 1'b0; + rresp_q <= 2'b00; + rdata_q <= '0; + reg_o <= REG_RST; + end else begin + for (int r = 0; r < N_REGS; r++) begin + for (int bit_idx = 0; bit_idx < 32; bit_idx++) begin + if (reg_bit_mode_t'(REG_MODE[r][bit_idx]) == REG_BIT_W1S) + reg_o[r][bit_idx] <= 1'b0; + end + end + + if (s_axil.req.aw.valid && s_axil.resp.aw_ready) begin + awaddr_q <= s_axil.req.aw.addr; + aw_seen_q <= 1'b1; + end + + if (s_axil.req.w.valid && s_axil.resp.w_ready) begin + wdata_q <= s_axil.req.w.data; + wstrb_q <= s_axil.req.w.strb; + w_seen_q <= 1'b1; + end + + if (aw_seen_q && w_seen_q && !bvalid_q) begin + bvalid_q <= 1'b1; + bresp_q <= 2'b00; + + if (!wr_addr_valid) begin + bresp_q <= 2'b10; + end else begin + rw_cur = reg_o[wr_idx]; + rw_new = rw_cur; + + for (b = 0; b < 32; b = b + 1) begin + if (wr_mask[b]) begin + unique case (reg_bit_mode_t'(REG_MODE[wr_idx][b])) + REG_BIT_RSVD: begin end + REG_BIT_RO : begin bresp_q <= 2'b10; end + REG_BIT_RW : rw_new[b] = wr_data32[b]; + REG_BIT_W1S : if (wr_data32[b]) rw_new[b] = 1'b1; + REG_BIT_W1C : if (wr_data32[b]) rw_new[b] = 1'b0; + default : begin end + endcase + end + end + + reg_o[wr_idx] <= rw_new; + end + + aw_seen_q <= 1'b0; + w_seen_q <= 1'b0; + end + + if (bvalid_q && s_axil.req.b_ready) begin + bvalid_q <= 1'b0; + end + + if (s_axil.req.ar.valid && s_axil.resp.ar_ready) begin + rvalid_q <= 1'b1; + rresp_q <= 2'b00; + rd_word = '0; + + if (!rd_addr_valid) begin + rresp_q <= 2'b10; + end else begin + for (b = 0; b < 32; b = b + 1) begin + unique case (reg_bit_mode_t'(REG_MODE[rd_idx][b])) + REG_BIT_RSVD: rd_word[b] = 1'b0; + REG_BIT_RO : rd_word[b] = reg_i[rd_idx][b]; + REG_BIT_RW : rd_word[b] = reg_o[rd_idx][b]; + REG_BIT_W1S : rd_word[b] = 1'b0; + REG_BIT_W1C : rd_word[b] = reg_o[rd_idx][b]; + default : rd_word[b] = 1'b0; + endcase + end + end + + rdata_q <= rd_word; + end + + if (rvalid_q && s_axil.req.r_ready) begin + rvalid_q <= 1'b0; + end + end + end + +endmodule diff --git a/axi/axi4l_to_axi4.sv b/axi/axi4l_to_axi4.sv new file mode 100644 index 0000000..05f295f --- /dev/null +++ b/axi/axi4l_to_axi4.sv @@ -0,0 +1,59 @@ +module axi4l_to_axi4 #( + parameter int unsigned ADDR_W = 32, + parameter int unsigned DATA_W = 32, + parameter int unsigned ID_W = 4, + parameter int unsigned USER_W = 1, + parameter logic [ID_W-1:0] AXI_ID_CONST = '0, + parameter logic [3:0] AXI_CACHE_CONST = 4'b0000, + parameter logic [3:0] AXI_QOS_CONST = 4'b0000, + parameter logic [3:0] AXI_REGION_CONST = 4'b0000 +)( + axi4l_if.slave s_axil, + axi4_if.master m_axi +); + assign m_axi.req.aw.id = AXI_ID_CONST; + assign m_axi.req.aw.addr = s_axil.req.aw.addr; + assign m_axi.req.aw.len = 8'd0; + assign m_axi.req.aw.size = axi_pkg::axi_size_from_bytes(DATA_W/8); + assign m_axi.req.aw.burst = axi_pkg::AXI_BURST_INCR; + assign m_axi.req.aw.lock = 1'b0; + assign m_axi.req.aw.cache = AXI_CACHE_CONST; + assign m_axi.req.aw.prot = s_axil.req.aw.prot; + assign m_axi.req.aw.qos = AXI_QOS_CONST; + assign m_axi.req.aw.region = AXI_REGION_CONST; + assign m_axi.req.aw.user = s_axil.req.aw.user; + assign m_axi.req.aw.valid = s_axil.req.aw.valid; + assign s_axil.resp.aw_ready = m_axi.resp.aw_ready; + + assign m_axi.req.w.data = s_axil.req.w.data; + assign m_axi.req.w.strb = s_axil.req.w.strb; + assign m_axi.req.w.last = 1'b1; + assign m_axi.req.w.user = s_axil.req.w.user; + assign m_axi.req.w.valid = s_axil.req.w.valid; + assign s_axil.resp.w_ready = m_axi.resp.w_ready; + + assign s_axil.resp.b.resp = m_axi.resp.b.resp; + assign s_axil.resp.b.user = m_axi.resp.b.user; + assign s_axil.resp.b.valid = m_axi.resp.b.valid; + assign m_axi.req.b_ready = s_axil.req.b_ready; + + assign m_axi.req.ar.id = AXI_ID_CONST; + assign m_axi.req.ar.addr = s_axil.req.ar.addr; + assign m_axi.req.ar.len = 8'd0; + assign m_axi.req.ar.size = axi_pkg::axi_size_from_bytes(DATA_W/8); + assign m_axi.req.ar.burst = axi_pkg::AXI_BURST_INCR; + assign m_axi.req.ar.lock = 1'b0; + assign m_axi.req.ar.cache = AXI_CACHE_CONST; + assign m_axi.req.ar.prot = s_axil.req.ar.prot; + assign m_axi.req.ar.qos = AXI_QOS_CONST; + assign m_axi.req.ar.region = AXI_REGION_CONST; + assign m_axi.req.ar.user = s_axil.req.ar.user; + assign m_axi.req.ar.valid = s_axil.req.ar.valid; + assign s_axil.resp.ar_ready = m_axi.resp.ar_ready; + + assign s_axil.resp.r.data = m_axi.resp.r.data; + assign s_axil.resp.r.resp = m_axi.resp.r.resp; + assign s_axil.resp.r.user = m_axi.resp.r.user; + assign s_axil.resp.r.valid = m_axi.resp.r.valid; + assign m_axi.req.r_ready = s_axil.req.r_ready; +endmodule diff --git a/axi/axi_crossbar_core_wrapper.sv b/axi/axi_crossbar_core_wrapper.sv new file mode 100644 index 0000000..d506db9 --- /dev/null +++ b/axi/axi_crossbar_core_wrapper.sv @@ -0,0 +1,654 @@ +/* + +Copyright (c) 2020 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 3x3 crossbar (wrapper) + */ +module axi_crossbar_core_wrapper # +( + // Width of data bus in bits + parameter DATA_WIDTH = 32, + // Width of address bus in bits + parameter ADDR_WIDTH = 32, + // Width of wstrb (width of data bus in words) + parameter STRB_WIDTH = (DATA_WIDTH/8), + // Input ID field width (from AXI masters) + parameter S_ID_WIDTH = 8, + // Output ID field width (towards AXI slaves) + // Additional bits required for response routing + parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT), + // Propagate awuser signal + parameter AWUSER_ENABLE = 0, + // Width of awuser signal + parameter AWUSER_WIDTH = 1, + // Propagate wuser signal + parameter WUSER_ENABLE = 0, + // Width of wuser signal + parameter WUSER_WIDTH = 1, + // Propagate buser signal + parameter BUSER_ENABLE = 0, + // Width of buser signal + parameter BUSER_WIDTH = 1, + // Propagate aruser signal + parameter ARUSER_ENABLE = 0, + // Width of aruser signal + parameter ARUSER_WIDTH = 1, + // Propagate ruser signal + parameter RUSER_ENABLE = 0, + // Width of ruser signal + parameter RUSER_WIDTH = 1, + // Number of concurrent unique IDs + parameter S00_THREADS = 2, + // Number of concurrent operations + parameter S00_ACCEPT = 16, + // Number of concurrent unique IDs + parameter S01_THREADS = 2, + // Number of concurrent operations + parameter S01_ACCEPT = 16, + // Number of concurrent unique IDs + parameter S02_THREADS = 2, + // Number of concurrent operations + parameter S02_ACCEPT = 16, + // Number of regions per master interface + parameter M_REGIONS = 1, + // Master interface base addresses + // M_REGIONS concatenated fields of ADDR_WIDTH bits + parameter M00_BASE_ADDR = 0, + // Master interface address widths + // M_REGIONS concatenated fields of 32 bits + parameter M00_ADDR_WIDTH = {M_REGIONS{32'd24}}, + // Read connections between interfaces + // S_COUNT bits + parameter M00_CONNECT_READ = 3'b111, + // Write connections between interfaces + // S_COUNT bits + parameter M00_CONNECT_WRITE = 3'b111, + // Number of concurrent operations for each master interface + parameter M00_ISSUE = 4, + // Secure master (fail operations based on awprot/arprot) + parameter M00_SECURE = 0, + // Master interface base addresses + // M_REGIONS concatenated fields of ADDR_WIDTH bits + parameter M01_BASE_ADDR = 0, + // Master interface address widths + // M_REGIONS concatenated fields of 32 bits + parameter M01_ADDR_WIDTH = {M_REGIONS{32'd24}}, + // Read connections between interfaces + // S_COUNT bits + parameter M01_CONNECT_READ = 3'b111, + // Write connections between interfaces + // S_COUNT bits + parameter M01_CONNECT_WRITE = 3'b111, + // Number of concurrent operations for each master interface + parameter M01_ISSUE = 4, + // Secure master (fail operations based on awprot/arprot) + parameter M01_SECURE = 0, + // Master interface base addresses + // M_REGIONS concatenated fields of ADDR_WIDTH bits + parameter M02_BASE_ADDR = 0, + // Master interface address widths + // M_REGIONS concatenated fields of 32 bits + parameter M02_ADDR_WIDTH = {M_REGIONS{32'd24}}, + // Read connections between interfaces + // S_COUNT bits + parameter M02_CONNECT_READ = 3'b111, + // Write connections between interfaces + // S_COUNT bits + parameter M02_CONNECT_WRITE = 3'b111, + // Number of concurrent operations for each master interface + parameter M02_ISSUE = 4, + // Secure master (fail operations based on awprot/arprot) + parameter M02_SECURE = 0, + // Slave interface AW channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S00_AW_REG_TYPE = 0, + // Slave interface W channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S00_W_REG_TYPE = 0, + // Slave interface B channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S00_B_REG_TYPE = 1, + // Slave interface AR channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S00_AR_REG_TYPE = 0, + // Slave interface R channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S00_R_REG_TYPE = 2, + // Slave interface AW channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S01_AW_REG_TYPE = 0, + // Slave interface W channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S01_W_REG_TYPE = 0, + // Slave interface B channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S01_B_REG_TYPE = 1, + // Slave interface AR channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S01_AR_REG_TYPE = 0, + // Slave interface R channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S01_R_REG_TYPE = 2, + // Slave interface AW channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S02_AW_REG_TYPE = 0, + // Slave interface W channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S02_W_REG_TYPE = 0, + // Slave interface B channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S02_B_REG_TYPE = 1, + // Slave interface AR channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S02_AR_REG_TYPE = 0, + // Slave interface R channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S02_R_REG_TYPE = 2, + // Master interface AW channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M00_AW_REG_TYPE = 1, + // Master interface W channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M00_W_REG_TYPE = 2, + // Master interface B channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M00_B_REG_TYPE = 0, + // Master interface AR channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M00_AR_REG_TYPE = 1, + // Master interface R channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M00_R_REG_TYPE = 0, + // Master interface AW channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M01_AW_REG_TYPE = 1, + // Master interface W channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M01_W_REG_TYPE = 2, + // Master interface B channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M01_B_REG_TYPE = 0, + // Master interface AR channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M01_AR_REG_TYPE = 1, + // Master interface R channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M01_R_REG_TYPE = 0, + // Master interface AW channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M02_AW_REG_TYPE = 1, + // Master interface W channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M02_W_REG_TYPE = 2, + // Master interface B channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M02_B_REG_TYPE = 0, + // Master interface AR channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M02_AR_REG_TYPE = 1, + // Master interface R channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M02_R_REG_TYPE = 0 +) +( + input wire clk, + input wire rst, + + /* + * AXI slave interface + */ + input wire [S_ID_WIDTH-1:0] s00_axi_awid, + input wire [ADDR_WIDTH-1:0] s00_axi_awaddr, + input wire [7:0] s00_axi_awlen, + input wire [2:0] s00_axi_awsize, + input wire [1:0] s00_axi_awburst, + input wire s00_axi_awlock, + input wire [3:0] s00_axi_awcache, + input wire [2:0] s00_axi_awprot, + input wire [3:0] s00_axi_awqos, + input wire [AWUSER_WIDTH-1:0] s00_axi_awuser, + input wire s00_axi_awvalid, + output wire s00_axi_awready, + input wire [DATA_WIDTH-1:0] s00_axi_wdata, + input wire [STRB_WIDTH-1:0] s00_axi_wstrb, + input wire s00_axi_wlast, + input wire [WUSER_WIDTH-1:0] s00_axi_wuser, + input wire s00_axi_wvalid, + output wire s00_axi_wready, + output wire [S_ID_WIDTH-1:0] s00_axi_bid, + output wire [1:0] s00_axi_bresp, + output wire [BUSER_WIDTH-1:0] s00_axi_buser, + output wire s00_axi_bvalid, + input wire s00_axi_bready, + input wire [S_ID_WIDTH-1:0] s00_axi_arid, + input wire [ADDR_WIDTH-1:0] s00_axi_araddr, + input wire [7:0] s00_axi_arlen, + input wire [2:0] s00_axi_arsize, + input wire [1:0] s00_axi_arburst, + input wire s00_axi_arlock, + input wire [3:0] s00_axi_arcache, + input wire [2:0] s00_axi_arprot, + input wire [3:0] s00_axi_arqos, + input wire [ARUSER_WIDTH-1:0] s00_axi_aruser, + input wire s00_axi_arvalid, + output wire s00_axi_arready, + output wire [S_ID_WIDTH-1:0] s00_axi_rid, + output wire [DATA_WIDTH-1:0] s00_axi_rdata, + output wire [1:0] s00_axi_rresp, + output wire s00_axi_rlast, + output wire [RUSER_WIDTH-1:0] s00_axi_ruser, + output wire s00_axi_rvalid, + input wire s00_axi_rready, + + input wire [S_ID_WIDTH-1:0] s01_axi_awid, + input wire [ADDR_WIDTH-1:0] s01_axi_awaddr, + input wire [7:0] s01_axi_awlen, + input wire [2:0] s01_axi_awsize, + input wire [1:0] s01_axi_awburst, + input wire s01_axi_awlock, + input wire [3:0] s01_axi_awcache, + input wire [2:0] s01_axi_awprot, + input wire [3:0] s01_axi_awqos, + input wire [AWUSER_WIDTH-1:0] s01_axi_awuser, + input wire s01_axi_awvalid, + output wire s01_axi_awready, + input wire [DATA_WIDTH-1:0] s01_axi_wdata, + input wire [STRB_WIDTH-1:0] s01_axi_wstrb, + input wire s01_axi_wlast, + input wire [WUSER_WIDTH-1:0] s01_axi_wuser, + input wire s01_axi_wvalid, + output wire s01_axi_wready, + output wire [S_ID_WIDTH-1:0] s01_axi_bid, + output wire [1:0] s01_axi_bresp, + output wire [BUSER_WIDTH-1:0] s01_axi_buser, + output wire s01_axi_bvalid, + input wire s01_axi_bready, + input wire [S_ID_WIDTH-1:0] s01_axi_arid, + input wire [ADDR_WIDTH-1:0] s01_axi_araddr, + input wire [7:0] s01_axi_arlen, + input wire [2:0] s01_axi_arsize, + input wire [1:0] s01_axi_arburst, + input wire s01_axi_arlock, + input wire [3:0] s01_axi_arcache, + input wire [2:0] s01_axi_arprot, + input wire [3:0] s01_axi_arqos, + input wire [ARUSER_WIDTH-1:0] s01_axi_aruser, + input wire s01_axi_arvalid, + output wire s01_axi_arready, + output wire [S_ID_WIDTH-1:0] s01_axi_rid, + output wire [DATA_WIDTH-1:0] s01_axi_rdata, + output wire [1:0] s01_axi_rresp, + output wire s01_axi_rlast, + output wire [RUSER_WIDTH-1:0] s01_axi_ruser, + output wire s01_axi_rvalid, + input wire s01_axi_rready, + + input wire [S_ID_WIDTH-1:0] s02_axi_awid, + input wire [ADDR_WIDTH-1:0] s02_axi_awaddr, + input wire [7:0] s02_axi_awlen, + input wire [2:0] s02_axi_awsize, + input wire [1:0] s02_axi_awburst, + input wire s02_axi_awlock, + input wire [3:0] s02_axi_awcache, + input wire [2:0] s02_axi_awprot, + input wire [3:0] s02_axi_awqos, + input wire [AWUSER_WIDTH-1:0] s02_axi_awuser, + input wire s02_axi_awvalid, + output wire s02_axi_awready, + input wire [DATA_WIDTH-1:0] s02_axi_wdata, + input wire [STRB_WIDTH-1:0] s02_axi_wstrb, + input wire s02_axi_wlast, + input wire [WUSER_WIDTH-1:0] s02_axi_wuser, + input wire s02_axi_wvalid, + output wire s02_axi_wready, + output wire [S_ID_WIDTH-1:0] s02_axi_bid, + output wire [1:0] s02_axi_bresp, + output wire [BUSER_WIDTH-1:0] s02_axi_buser, + output wire s02_axi_bvalid, + input wire s02_axi_bready, + input wire [S_ID_WIDTH-1:0] s02_axi_arid, + input wire [ADDR_WIDTH-1:0] s02_axi_araddr, + input wire [7:0] s02_axi_arlen, + input wire [2:0] s02_axi_arsize, + input wire [1:0] s02_axi_arburst, + input wire s02_axi_arlock, + input wire [3:0] s02_axi_arcache, + input wire [2:0] s02_axi_arprot, + input wire [3:0] s02_axi_arqos, + input wire [ARUSER_WIDTH-1:0] s02_axi_aruser, + input wire s02_axi_arvalid, + output wire s02_axi_arready, + output wire [S_ID_WIDTH-1:0] s02_axi_rid, + output wire [DATA_WIDTH-1:0] s02_axi_rdata, + output wire [1:0] s02_axi_rresp, + output wire s02_axi_rlast, + output wire [RUSER_WIDTH-1:0] s02_axi_ruser, + output wire s02_axi_rvalid, + input wire s02_axi_rready, + + /* + * AXI master interface + */ + output wire [M_ID_WIDTH-1:0] m00_axi_awid, + output wire [ADDR_WIDTH-1:0] m00_axi_awaddr, + output wire [7:0] m00_axi_awlen, + output wire [2:0] m00_axi_awsize, + output wire [1:0] m00_axi_awburst, + output wire m00_axi_awlock, + output wire [3:0] m00_axi_awcache, + output wire [2:0] m00_axi_awprot, + output wire [3:0] m00_axi_awqos, + output wire [3:0] m00_axi_awregion, + output wire [AWUSER_WIDTH-1:0] m00_axi_awuser, + output wire m00_axi_awvalid, + input wire m00_axi_awready, + output wire [DATA_WIDTH-1:0] m00_axi_wdata, + output wire [STRB_WIDTH-1:0] m00_axi_wstrb, + output wire m00_axi_wlast, + output wire [WUSER_WIDTH-1:0] m00_axi_wuser, + output wire m00_axi_wvalid, + input wire m00_axi_wready, + input wire [M_ID_WIDTH-1:0] m00_axi_bid, + input wire [1:0] m00_axi_bresp, + input wire [BUSER_WIDTH-1:0] m00_axi_buser, + input wire m00_axi_bvalid, + output wire m00_axi_bready, + output wire [M_ID_WIDTH-1:0] m00_axi_arid, + output wire [ADDR_WIDTH-1:0] m00_axi_araddr, + output wire [7:0] m00_axi_arlen, + output wire [2:0] m00_axi_arsize, + output wire [1:0] m00_axi_arburst, + output wire m00_axi_arlock, + output wire [3:0] m00_axi_arcache, + output wire [2:0] m00_axi_arprot, + output wire [3:0] m00_axi_arqos, + output wire [3:0] m00_axi_arregion, + output wire [ARUSER_WIDTH-1:0] m00_axi_aruser, + output wire m00_axi_arvalid, + input wire m00_axi_arready, + input wire [M_ID_WIDTH-1:0] m00_axi_rid, + input wire [DATA_WIDTH-1:0] m00_axi_rdata, + input wire [1:0] m00_axi_rresp, + input wire m00_axi_rlast, + input wire [RUSER_WIDTH-1:0] m00_axi_ruser, + input wire m00_axi_rvalid, + output wire m00_axi_rready, + + output wire [M_ID_WIDTH-1:0] m01_axi_awid, + output wire [ADDR_WIDTH-1:0] m01_axi_awaddr, + output wire [7:0] m01_axi_awlen, + output wire [2:0] m01_axi_awsize, + output wire [1:0] m01_axi_awburst, + output wire m01_axi_awlock, + output wire [3:0] m01_axi_awcache, + output wire [2:0] m01_axi_awprot, + output wire [3:0] m01_axi_awqos, + output wire [3:0] m01_axi_awregion, + output wire [AWUSER_WIDTH-1:0] m01_axi_awuser, + output wire m01_axi_awvalid, + input wire m01_axi_awready, + output wire [DATA_WIDTH-1:0] m01_axi_wdata, + output wire [STRB_WIDTH-1:0] m01_axi_wstrb, + output wire m01_axi_wlast, + output wire [WUSER_WIDTH-1:0] m01_axi_wuser, + output wire m01_axi_wvalid, + input wire m01_axi_wready, + input wire [M_ID_WIDTH-1:0] m01_axi_bid, + input wire [1:0] m01_axi_bresp, + input wire [BUSER_WIDTH-1:0] m01_axi_buser, + input wire m01_axi_bvalid, + output wire m01_axi_bready, + output wire [M_ID_WIDTH-1:0] m01_axi_arid, + output wire [ADDR_WIDTH-1:0] m01_axi_araddr, + output wire [7:0] m01_axi_arlen, + output wire [2:0] m01_axi_arsize, + output wire [1:0] m01_axi_arburst, + output wire m01_axi_arlock, + output wire [3:0] m01_axi_arcache, + output wire [2:0] m01_axi_arprot, + output wire [3:0] m01_axi_arqos, + output wire [3:0] m01_axi_arregion, + output wire [ARUSER_WIDTH-1:0] m01_axi_aruser, + output wire m01_axi_arvalid, + input wire m01_axi_arready, + input wire [M_ID_WIDTH-1:0] m01_axi_rid, + input wire [DATA_WIDTH-1:0] m01_axi_rdata, + input wire [1:0] m01_axi_rresp, + input wire m01_axi_rlast, + input wire [RUSER_WIDTH-1:0] m01_axi_ruser, + input wire m01_axi_rvalid, + output wire m01_axi_rready, + + output wire [M_ID_WIDTH-1:0] m02_axi_awid, + output wire [ADDR_WIDTH-1:0] m02_axi_awaddr, + output wire [7:0] m02_axi_awlen, + output wire [2:0] m02_axi_awsize, + output wire [1:0] m02_axi_awburst, + output wire m02_axi_awlock, + output wire [3:0] m02_axi_awcache, + output wire [2:0] m02_axi_awprot, + output wire [3:0] m02_axi_awqos, + output wire [3:0] m02_axi_awregion, + output wire [AWUSER_WIDTH-1:0] m02_axi_awuser, + output wire m02_axi_awvalid, + input wire m02_axi_awready, + output wire [DATA_WIDTH-1:0] m02_axi_wdata, + output wire [STRB_WIDTH-1:0] m02_axi_wstrb, + output wire m02_axi_wlast, + output wire [WUSER_WIDTH-1:0] m02_axi_wuser, + output wire m02_axi_wvalid, + input wire m02_axi_wready, + input wire [M_ID_WIDTH-1:0] m02_axi_bid, + input wire [1:0] m02_axi_bresp, + input wire [BUSER_WIDTH-1:0] m02_axi_buser, + input wire m02_axi_bvalid, + output wire m02_axi_bready, + output wire [M_ID_WIDTH-1:0] m02_axi_arid, + output wire [ADDR_WIDTH-1:0] m02_axi_araddr, + output wire [7:0] m02_axi_arlen, + output wire [2:0] m02_axi_arsize, + output wire [1:0] m02_axi_arburst, + output wire m02_axi_arlock, + output wire [3:0] m02_axi_arcache, + output wire [2:0] m02_axi_arprot, + output wire [3:0] m02_axi_arqos, + output wire [3:0] m02_axi_arregion, + output wire [ARUSER_WIDTH-1:0] m02_axi_aruser, + output wire m02_axi_arvalid, + input wire m02_axi_arready, + input wire [M_ID_WIDTH-1:0] m02_axi_rid, + input wire [DATA_WIDTH-1:0] m02_axi_rdata, + input wire [1:0] m02_axi_rresp, + input wire m02_axi_rlast, + input wire [RUSER_WIDTH-1:0] m02_axi_ruser, + input wire m02_axi_rvalid, + output wire m02_axi_rready +); + +localparam S_COUNT = 3; +localparam M_COUNT = 3; + +// parameter sizing helpers +function [ADDR_WIDTH*M_REGIONS-1:0] w_a_r(input [ADDR_WIDTH*M_REGIONS-1:0] val); + w_a_r = val; +endfunction + +function [32*M_REGIONS-1:0] w_32_r(input [32*M_REGIONS-1:0] val); + w_32_r = val; +endfunction + +function [S_COUNT-1:0] w_s(input [S_COUNT-1:0] val); + w_s = val; +endfunction + +function [31:0] w_32(input [31:0] val); + w_32 = val; +endfunction + +function [1:0] w_2(input [1:0] val); + w_2 = val; +endfunction + +function w_1(input val); + w_1 = val; +endfunction + +axi_crossbar #( + .S_COUNT(S_COUNT), + .M_COUNT(M_COUNT), + .DATA_WIDTH(DATA_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .STRB_WIDTH(STRB_WIDTH), + .S_ID_WIDTH(S_ID_WIDTH), + .M_ID_WIDTH(M_ID_WIDTH), + .AWUSER_ENABLE(AWUSER_ENABLE), + .AWUSER_WIDTH(AWUSER_WIDTH), + .WUSER_ENABLE(WUSER_ENABLE), + .WUSER_WIDTH(WUSER_WIDTH), + .BUSER_ENABLE(BUSER_ENABLE), + .BUSER_WIDTH(BUSER_WIDTH), + .ARUSER_ENABLE(ARUSER_ENABLE), + .ARUSER_WIDTH(ARUSER_WIDTH), + .RUSER_ENABLE(RUSER_ENABLE), + .RUSER_WIDTH(RUSER_WIDTH), + .S_THREADS({ w_32(S02_THREADS), w_32(S01_THREADS), w_32(S00_THREADS) }), + .S_ACCEPT({ w_32(S02_ACCEPT), w_32(S01_ACCEPT), w_32(S00_ACCEPT) }), + .M_REGIONS(M_REGIONS), + .M_BASE_ADDR({ w_a_r(M02_BASE_ADDR), w_a_r(M01_BASE_ADDR), w_a_r(M00_BASE_ADDR) }), + .M_ADDR_WIDTH({ w_32_r(M02_ADDR_WIDTH), w_32_r(M01_ADDR_WIDTH), w_32_r(M00_ADDR_WIDTH) }), + .M_CONNECT_READ({ w_s(M02_CONNECT_READ), w_s(M01_CONNECT_READ), w_s(M00_CONNECT_READ) }), + .M_CONNECT_WRITE({ w_s(M02_CONNECT_WRITE), w_s(M01_CONNECT_WRITE), w_s(M00_CONNECT_WRITE) }), + .M_ISSUE({ w_32(M02_ISSUE), w_32(M01_ISSUE), w_32(M00_ISSUE) }), + .M_SECURE({ w_1(M02_SECURE), w_1(M01_SECURE), w_1(M00_SECURE) }), + .S_AR_REG_TYPE({ w_2(S02_AR_REG_TYPE), w_2(S01_AR_REG_TYPE), w_2(S00_AR_REG_TYPE) }), + .S_R_REG_TYPE({ w_2(S02_R_REG_TYPE), w_2(S01_R_REG_TYPE), w_2(S00_R_REG_TYPE) }), + .S_AW_REG_TYPE({ w_2(S02_AW_REG_TYPE), w_2(S01_AW_REG_TYPE), w_2(S00_AW_REG_TYPE) }), + .S_W_REG_TYPE({ w_2(S02_W_REG_TYPE), w_2(S01_W_REG_TYPE), w_2(S00_W_REG_TYPE) }), + .S_B_REG_TYPE({ w_2(S02_B_REG_TYPE), w_2(S01_B_REG_TYPE), w_2(S00_B_REG_TYPE) }), + .M_AR_REG_TYPE({ w_2(M02_AR_REG_TYPE), w_2(M01_AR_REG_TYPE), w_2(M00_AR_REG_TYPE) }), + .M_R_REG_TYPE({ w_2(M02_R_REG_TYPE), w_2(M01_R_REG_TYPE), w_2(M00_R_REG_TYPE) }), + .M_AW_REG_TYPE({ w_2(M02_AW_REG_TYPE), w_2(M01_AW_REG_TYPE), w_2(M00_AW_REG_TYPE) }), + .M_W_REG_TYPE({ w_2(M02_W_REG_TYPE), w_2(M01_W_REG_TYPE), w_2(M00_W_REG_TYPE) }), + .M_B_REG_TYPE({ w_2(M02_B_REG_TYPE), w_2(M01_B_REG_TYPE), w_2(M00_B_REG_TYPE) }) +) +axi_crossbar_inst ( + .clk(clk), + .rst(rst), + .s_axi_awid({ s02_axi_awid, s01_axi_awid, s00_axi_awid }), + .s_axi_awaddr({ s02_axi_awaddr, s01_axi_awaddr, s00_axi_awaddr }), + .s_axi_awlen({ s02_axi_awlen, s01_axi_awlen, s00_axi_awlen }), + .s_axi_awsize({ s02_axi_awsize, s01_axi_awsize, s00_axi_awsize }), + .s_axi_awburst({ s02_axi_awburst, s01_axi_awburst, s00_axi_awburst }), + .s_axi_awlock({ s02_axi_awlock, s01_axi_awlock, s00_axi_awlock }), + .s_axi_awcache({ s02_axi_awcache, s01_axi_awcache, s00_axi_awcache }), + .s_axi_awprot({ s02_axi_awprot, s01_axi_awprot, s00_axi_awprot }), + .s_axi_awqos({ s02_axi_awqos, s01_axi_awqos, s00_axi_awqos }), + .s_axi_awuser({ s02_axi_awuser, s01_axi_awuser, s00_axi_awuser }), + .s_axi_awvalid({ s02_axi_awvalid, s01_axi_awvalid, s00_axi_awvalid }), + .s_axi_awready({ s02_axi_awready, s01_axi_awready, s00_axi_awready }), + .s_axi_wdata({ s02_axi_wdata, s01_axi_wdata, s00_axi_wdata }), + .s_axi_wstrb({ s02_axi_wstrb, s01_axi_wstrb, s00_axi_wstrb }), + .s_axi_wlast({ s02_axi_wlast, s01_axi_wlast, s00_axi_wlast }), + .s_axi_wuser({ s02_axi_wuser, s01_axi_wuser, s00_axi_wuser }), + .s_axi_wvalid({ s02_axi_wvalid, s01_axi_wvalid, s00_axi_wvalid }), + .s_axi_wready({ s02_axi_wready, s01_axi_wready, s00_axi_wready }), + .s_axi_bid({ s02_axi_bid, s01_axi_bid, s00_axi_bid }), + .s_axi_bresp({ s02_axi_bresp, s01_axi_bresp, s00_axi_bresp }), + .s_axi_buser({ s02_axi_buser, s01_axi_buser, s00_axi_buser }), + .s_axi_bvalid({ s02_axi_bvalid, s01_axi_bvalid, s00_axi_bvalid }), + .s_axi_bready({ s02_axi_bready, s01_axi_bready, s00_axi_bready }), + .s_axi_arid({ s02_axi_arid, s01_axi_arid, s00_axi_arid }), + .s_axi_araddr({ s02_axi_araddr, s01_axi_araddr, s00_axi_araddr }), + .s_axi_arlen({ s02_axi_arlen, s01_axi_arlen, s00_axi_arlen }), + .s_axi_arsize({ s02_axi_arsize, s01_axi_arsize, s00_axi_arsize }), + .s_axi_arburst({ s02_axi_arburst, s01_axi_arburst, s00_axi_arburst }), + .s_axi_arlock({ s02_axi_arlock, s01_axi_arlock, s00_axi_arlock }), + .s_axi_arcache({ s02_axi_arcache, s01_axi_arcache, s00_axi_arcache }), + .s_axi_arprot({ s02_axi_arprot, s01_axi_arprot, s00_axi_arprot }), + .s_axi_arqos({ s02_axi_arqos, s01_axi_arqos, s00_axi_arqos }), + .s_axi_aruser({ s02_axi_aruser, s01_axi_aruser, s00_axi_aruser }), + .s_axi_arvalid({ s02_axi_arvalid, s01_axi_arvalid, s00_axi_arvalid }), + .s_axi_arready({ s02_axi_arready, s01_axi_arready, s00_axi_arready }), + .s_axi_rid({ s02_axi_rid, s01_axi_rid, s00_axi_rid }), + .s_axi_rdata({ s02_axi_rdata, s01_axi_rdata, s00_axi_rdata }), + .s_axi_rresp({ s02_axi_rresp, s01_axi_rresp, s00_axi_rresp }), + .s_axi_rlast({ s02_axi_rlast, s01_axi_rlast, s00_axi_rlast }), + .s_axi_ruser({ s02_axi_ruser, s01_axi_ruser, s00_axi_ruser }), + .s_axi_rvalid({ s02_axi_rvalid, s01_axi_rvalid, s00_axi_rvalid }), + .s_axi_rready({ s02_axi_rready, s01_axi_rready, s00_axi_rready }), + .m_axi_awid({ m02_axi_awid, m01_axi_awid, m00_axi_awid }), + .m_axi_awaddr({ m02_axi_awaddr, m01_axi_awaddr, m00_axi_awaddr }), + .m_axi_awlen({ m02_axi_awlen, m01_axi_awlen, m00_axi_awlen }), + .m_axi_awsize({ m02_axi_awsize, m01_axi_awsize, m00_axi_awsize }), + .m_axi_awburst({ m02_axi_awburst, m01_axi_awburst, m00_axi_awburst }), + .m_axi_awlock({ m02_axi_awlock, m01_axi_awlock, m00_axi_awlock }), + .m_axi_awcache({ m02_axi_awcache, m01_axi_awcache, m00_axi_awcache }), + .m_axi_awprot({ m02_axi_awprot, m01_axi_awprot, m00_axi_awprot }), + .m_axi_awqos({ m02_axi_awqos, m01_axi_awqos, m00_axi_awqos }), + .m_axi_awregion({ m02_axi_awregion, m01_axi_awregion, m00_axi_awregion }), + .m_axi_awuser({ m02_axi_awuser, m01_axi_awuser, m00_axi_awuser }), + .m_axi_awvalid({ m02_axi_awvalid, m01_axi_awvalid, m00_axi_awvalid }), + .m_axi_awready({ m02_axi_awready, m01_axi_awready, m00_axi_awready }), + .m_axi_wdata({ m02_axi_wdata, m01_axi_wdata, m00_axi_wdata }), + .m_axi_wstrb({ m02_axi_wstrb, m01_axi_wstrb, m00_axi_wstrb }), + .m_axi_wlast({ m02_axi_wlast, m01_axi_wlast, m00_axi_wlast }), + .m_axi_wuser({ m02_axi_wuser, m01_axi_wuser, m00_axi_wuser }), + .m_axi_wvalid({ m02_axi_wvalid, m01_axi_wvalid, m00_axi_wvalid }), + .m_axi_wready({ m02_axi_wready, m01_axi_wready, m00_axi_wready }), + .m_axi_bid({ m02_axi_bid, m01_axi_bid, m00_axi_bid }), + .m_axi_bresp({ m02_axi_bresp, m01_axi_bresp, m00_axi_bresp }), + .m_axi_buser({ m02_axi_buser, m01_axi_buser, m00_axi_buser }), + .m_axi_bvalid({ m02_axi_bvalid, m01_axi_bvalid, m00_axi_bvalid }), + .m_axi_bready({ m02_axi_bready, m01_axi_bready, m00_axi_bready }), + .m_axi_arid({ m02_axi_arid, m01_axi_arid, m00_axi_arid }), + .m_axi_araddr({ m02_axi_araddr, m01_axi_araddr, m00_axi_araddr }), + .m_axi_arlen({ m02_axi_arlen, m01_axi_arlen, m00_axi_arlen }), + .m_axi_arsize({ m02_axi_arsize, m01_axi_arsize, m00_axi_arsize }), + .m_axi_arburst({ m02_axi_arburst, m01_axi_arburst, m00_axi_arburst }), + .m_axi_arlock({ m02_axi_arlock, m01_axi_arlock, m00_axi_arlock }), + .m_axi_arcache({ m02_axi_arcache, m01_axi_arcache, m00_axi_arcache }), + .m_axi_arprot({ m02_axi_arprot, m01_axi_arprot, m00_axi_arprot }), + .m_axi_arqos({ m02_axi_arqos, m01_axi_arqos, m00_axi_arqos }), + .m_axi_arregion({ m02_axi_arregion, m01_axi_arregion, m00_axi_arregion }), + .m_axi_aruser({ m02_axi_aruser, m01_axi_aruser, m00_axi_aruser }), + .m_axi_arvalid({ m02_axi_arvalid, m01_axi_arvalid, m00_axi_arvalid }), + .m_axi_arready({ m02_axi_arready, m01_axi_arready, m00_axi_arready }), + .m_axi_rid({ m02_axi_rid, m01_axi_rid, m00_axi_rid }), + .m_axi_rdata({ m02_axi_rdata, m01_axi_rdata, m00_axi_rdata }), + .m_axi_rresp({ m02_axi_rresp, m01_axi_rresp, m00_axi_rresp }), + .m_axi_rlast({ m02_axi_rlast, m01_axi_rlast, m00_axi_rlast }), + .m_axi_ruser({ m02_axi_ruser, m01_axi_ruser, m00_axi_ruser }), + .m_axi_rvalid({ m02_axi_rvalid, m01_axi_rvalid, m00_axi_rvalid }), + .m_axi_rready({ m02_axi_rready, m01_axi_rready, m00_axi_rready }) +); + +endmodule + +`resetall diff --git a/axi/axi_crossbar_wrapper.sv b/axi/axi_crossbar_wrapper.sv new file mode 100644 index 0000000..25adeac --- /dev/null +++ b/axi/axi_crossbar_wrapper.sv @@ -0,0 +1,1045 @@ +module axi_crossbar_wrapper #( + parameter int SLAVE_QTY = 3, + parameter int MASTER_QTY = 3, + parameter int ADDR_WIDTH = 32, + parameter int DATA_WIDTH = 32 + parameter int STRB_WIDTH = (DATA_WIDTH/8) +)( + input wire clk, + input wire rst, + + axi4_if.slave s_axi [SLAVE_QTY], + axi4_if.master m_axi [MASTER_QTY] +); + + localparam CROSSBAR_DATA_WIDTH = DATA_WIDTH; + localparam CROSSBAR_ADDR_WIDTH = ADDR_WIDTH; + localparam CROSSBAR_STRB_WIDTH = (CROSSBAR_DATA_WIDTH/8); + localparam CROSSBAR_S_ID_WIDTH = 8; + localparam CROSSBAR_M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT); + localparam CROSSBAR_AWUSER_ENABLE = 0; + localparam CROSSBAR_AWUSER_WIDTH = 1; + localparam CROSSBAR_WUSER_ENABLE = 0; + localparam CROSSBAR_WUSER_WIDTH = 1; + localparam CROSSBAR_BUSER_ENABLE = 0; + localparam CROSSBAR_BUSER_WIDTH = 1; + localparam CROSSBAR_ARUSER_ENABLE = 0; + localparam CROSSBAR_ARUSER_WIDTH = 1; + localparam CROSSBAR_RUSER_ENABLE = 0; + localparam CROSSBAR_RUSER_WIDTH = 1; + localparam CROSSBAR_S00_THREADS = 2; + localparam CROSSBAR_S00_ACCEPT = 16; + localparam CROSSBAR_S01_THREADS = 2; + localparam CROSSBAR_S01_ACCEPT = 16; + localparam CROSSBAR_S02_THREADS = 2; + localparam CROSSBAR_S02_ACCEPT = 16; + localparam CROSSBAR_M_REGIONS = 1; + localparam CROSSBAR_M00_BASE_ADDR = 0; + localparam CROSSBAR_M00_ADDR_WIDTH = {M_REGIONS{32'd24}}; + localparam CROSSBAR_M00_CONNECT_READ = 3'b111; + localparam CROSSBAR_M00_CONNECT_WRITE = 3'b111; + localparam CROSSBAR_M00_ISSUE = 4; + localparam CROSSBAR_M00_SECURE = 0; + localparam CROSSBAR_M01_BASE_ADDR = 32'h00001000; + localparam CROSSBAR_M01_ADDR_WIDTH = {M_REGIONS{32'd24}}; + localparam CROSSBAR_M01_CONNECT_READ = 3'b111; + localparam CROSSBAR_M01_CONNECT_WRITE = 3'b111; + localparam CROSSBAR_M01_ISSUE = 4; + localparam CROSSBAR_M01_SECURE = 0; + localparam CROSSBAR_M02_BASE_ADDR = 32'h00002000; + localparam CROSSBAR_M02_ADDR_WIDTH = {M_REGIONS{32'd24}}; + localparam CROSSBAR_M02_CONNECT_READ = 3'b111; + localparam CROSSBAR_M02_CONNECT_WRITE = 3'b111; + localparam CROSSBAR_M02_ISSUE = 4; + localparam CROSSBAR_M02_SECURE = 0; + localparam CROSSBAR_S00_AW_REG_TYPE = 0; + localparam CROSSBAR_S00_W_REG_TYPE = 0; + localparam CROSSBAR_S00_B_REG_TYPE = 1; + localparam CROSSBAR_S00_AR_REG_TYPE = 0; + localparam CROSSBAR_S00_R_REG_TYPE = 2; + localparam CROSSBAR_S01_AW_REG_TYPE = 0; + localparam CROSSBAR_S01_W_REG_TYPE = 0; + localparam CROSSBAR_S01_B_REG_TYPE = 1; + localparam CROSSBAR_S01_AR_REG_TYPE = 0; + localparam CROSSBAR_S01_R_REG_TYPE = 2; + localparam CROSSBAR_S02_AW_REG_TYPE = 0; + localparam CROSSBAR_S02_W_REG_TYPE = 0; + localparam CROSSBAR_S02_B_REG_TYPE = 1; + localparam CROSSBAR_S02_AR_REG_TYPE = 0; + localparam CROSSBAR_S02_R_REG_TYPE = 2; + localparam CROSSBAR_M00_AW_REG_TYPE = 1; + localparam CROSSBAR_M00_W_REG_TYPE = 2; + localparam CROSSBAR_M00_B_REG_TYPE = 0; + localparam CROSSBAR_M00_AR_REG_TYPE = 1; + localparam CROSSBAR_M00_R_REG_TYPE = 0; + localparam CROSSBAR_M01_AW_REG_TYPE = 1; + localparam CROSSBAR_M01_W_REG_TYPE = 2; + localparam CROSSBAR_M01_B_REG_TYPE = 0; + localparam CROSSBAR_M01_AR_REG_TYPE = 1; + localparam CROSSBAR_M01_R_REG_TYPE = 0; + localparam CROSSBAR_M02_AW_REG_TYPE = 1; + localparam CROSSBAR_M02_W_REG_TYPE = 2; + localparam CROSSBAR_M02_B_REG_TYPE = 0; + localparam CROSSBAR_M02_AR_REG_TYPE = 1; + localparam CROSSBAR_M02_R_REG_TYPE = 0; + + wire crossbar_clk; + wire crossbar_rst; + wire [CROSSBAR_S_ID_WIDTH-1:0] crossbar_s00_axi_awid; + wire [CROSSBAR_ADDR_WIDTH-1:0] crossbar_s00_axi_awaddr; + wire [7:0] crossbar_s00_axi_awlen; + wire [2:0] crossbar_s00_axi_awsize; + wire [1:0] crossbar_s00_axi_awburst; + wire crossbar_s00_axi_awlock; + wire [3:0] crossbar_s00_axi_awcache; + wire [2:0] crossbar_s00_axi_awprot; + wire [3:0] crossbar_s00_axi_awqos; + wire [CROSSBAR_AWUSER_WIDTH-1:0] crossbar_s00_axi_awuser; + wire crossbar_s00_axi_awvalid; + wire crossbar_s00_axi_awready; + wire [CROSSBAR_DATA_WIDTH-1:0] crossbar_s00_axi_wdata; + wire [CROSSBAR_STRB_WIDTH-1:0] crossbar_s00_axi_wstrb; + wire crossbar_s00_axi_wlast; + wire [CROSSBAR_WUSER_WIDTH-1:0] crossbar_s00_axi_wuser; + wire crossbar_s00_axi_wvalid; + wire crossbar_s00_axi_wready; + wire [CROSSBAR_S_ID_WIDTH-1:0] crossbar_s00_axi_bid; + wire [1:0] crossbar_s00_axi_bresp; + wire [CROSSBAR_BUSER_WIDTH-1:0] crossbar_s00_axi_buser; + wire crossbar_s00_axi_bvalid; + wire crossbar_s00_axi_bready; + wire [CROSSBAR_S_ID_WIDTH-1:0] crossbar_s00_axi_arid; + wire [CROSSBAR_ADDR_WIDTH-1:0] crossbar_s00_axi_araddr; + wire [7:0] crossbar_s00_axi_arlen; + wire [2:0] crossbar_s00_axi_arsize; + wire [1:0] crossbar_s00_axi_arburst; + wire crossbar_s00_axi_arlock; + wire [3:0] crossbar_s00_axi_arcache; + wire [2:0] crossbar_s00_axi_arprot; + wire [3:0] crossbar_s00_axi_arqos; + wire [CROSSBAR_ARUSER_WIDTH-1:0] crossbar_s00_axi_aruser; + wire crossbar_s00_axi_arvalid; + wire crossbar_s00_axi_arready; + wire [CROSSBAR_S_ID_WIDTH-1:0] crossbar_s00_axi_rid; + wire [CROSSBAR_DATA_WIDTH-1:0] crossbar_s00_axi_rdata; + wire [1:0] crossbar_s00_axi_rresp; + wire crossbar_s00_axi_rlast; + wire [CROSSBAR_RUSER_WIDTH-1:0] crossbar_s00_axi_ruser; + wire crossbar_s00_axi_rvalid; + wire crossbar_s00_axi_rready; + wire [CROSSBAR_S_ID_WIDTH-1:0] crossbar_s01_axi_awid; + wire [CROSSBAR_ADDR_WIDTH-1:0] crossbar_s01_axi_awaddr; + wire [7:0] crossbar_s01_axi_awlen; + wire [2:0] crossbar_s01_axi_awsize; + wire [1:0] crossbar_s01_axi_awburst; + wire crossbar_s01_axi_awlock; + wire [3:0] crossbar_s01_axi_awcache; + wire [2:0] crossbar_s01_axi_awprot; + wire [3:0] crossbar_s01_axi_awqos; + wire [CROSSBAR_AWUSER_WIDTH-1:0] crossbar_s01_axi_awuser; + wire crossbar_s01_axi_awvalid; + wire crossbar_s01_axi_awready; + wire [CROSSBAR_DATA_WIDTH-1:0] crossbar_s01_axi_wdata; + wire [CROSSBAR_STRB_WIDTH-1:0] crossbar_s01_axi_wstrb; + wire crossbar_s01_axi_wlast; + wire [CROSSBAR_WUSER_WIDTH-1:0] crossbar_s01_axi_wuser; + wire crossbar_s01_axi_wvalid; + wire crossbar_s01_axi_wready; + wire [CROSSBAR_S_ID_WIDTH-1:0] crossbar_s01_axi_bid; + wire [1:0] crossbar_s01_axi_bresp; + wire [CROSSBAR_BUSER_WIDTH-1:0] crossbar_s01_axi_buser; + wire crossbar_s01_axi_bvalid; + wire crossbar_s01_axi_bready; + wire [CROSSBAR_S_ID_WIDTH-1:0] crossbar_s01_axi_arid; + wire [CROSSBAR_ADDR_WIDTH-1:0] crossbar_s01_axi_araddr; + wire [7:0] crossbar_s01_axi_arlen; + wire [2:0] crossbar_s01_axi_arsize; + wire [1:0] crossbar_s01_axi_arburst; + wire crossbar_s01_axi_arlock; + wire [3:0] crossbar_s01_axi_arcache; + wire [2:0] crossbar_s01_axi_arprot; + wire [3:0] crossbar_s01_axi_arqos; + wire [CROSSBAR_ARUSER_WIDTH-1:0] crossbar_s01_axi_aruser; + wire crossbar_s01_axi_arvalid; + wire crossbar_s01_axi_arready; + wire [CROSSBAR_S_ID_WIDTH-1:0] crossbar_s01_axi_rid; + wire [CROSSBAR_DATA_WIDTH-1:0] crossbar_s01_axi_rdata; + wire [1:0] crossbar_s01_axi_rresp; + wire crossbar_s01_axi_rlast; + wire [CROSSBAR_RUSER_WIDTH-1:0] crossbar_s01_axi_ruser; + wire crossbar_s01_axi_rvalid; + wire crossbar_s01_axi_rready; + wire [CROSSBAR_S_ID_WIDTH-1:0] crossbar_s02_axi_awid; + wire [CROSSBAR_ADDR_WIDTH-1:0] crossbar_s02_axi_awaddr; + wire [7:0] crossbar_s02_axi_awlen; + wire [2:0] crossbar_s02_axi_awsize; + wire [1:0] crossbar_s02_axi_awburst; + wire crossbar_s02_axi_awlock; + wire [3:0] crossbar_s02_axi_awcache; + wire [2:0] crossbar_s02_axi_awprot; + wire [3:0] crossbar_s02_axi_awqos; + wire [CROSSBAR_AWUSER_WIDTH-1:0] crossbar_s02_axi_awuser; + wire crossbar_s02_axi_awvalid; + wire crossbar_s02_axi_awready; + wire [CROSSBAR_DATA_WIDTH-1:0] crossbar_s02_axi_wdata; + wire [CROSSBAR_STRB_WIDTH-1:0] crossbar_s02_axi_wstrb; + wire crossbar_s02_axi_wlast; + wire [CROSSBAR_WUSER_WIDTH-1:0] crossbar_s02_axi_wuser; + wire crossbar_s02_axi_wvalid; + wire crossbar_s02_axi_wready; + wire [CROSSBAR_S_ID_WIDTH-1:0] crossbar_s02_axi_bid; + wire [1:0] crossbar_s02_axi_bresp; + wire [CROSSBAR_BUSER_WIDTH-1:0] crossbar_s02_axi_buser; + wire crossbar_s02_axi_bvalid; + wire crossbar_s02_axi_bready; + wire [CROSSBAR_S_ID_WIDTH-1:0] crossbar_s02_axi_arid; + wire [CROSSBAR_ADDR_WIDTH-1:0] crossbar_s02_axi_araddr; + wire [7:0] crossbar_s02_axi_arlen; + wire [2:0] crossbar_s02_axi_arsize; + wire [1:0] crossbar_s02_axi_arburst; + wire crossbar_s02_axi_arlock; + wire [3:0] crossbar_s02_axi_arcache; + wire [2:0] crossbar_s02_axi_arprot; + wire [3:0] crossbar_s02_axi_arqos; + wire [CROSSBAR_ARUSER_WIDTH-1:0] crossbar_s02_axi_aruser; + wire crossbar_s02_axi_arvalid; + wire crossbar_s02_axi_arready; + wire [CROSSBAR_S_ID_WIDTH-1:0] crossbar_s02_axi_rid; + wire [CROSSBAR_DATA_WIDTH-1:0] crossbar_s02_axi_rdata; + wire [1:0] crossbar_s02_axi_rresp; + wire crossbar_s02_axi_rlast; + wire [CROSSBAR_RUSER_WIDTH-1:0] crossbar_s02_axi_ruser; + wire crossbar_s02_axi_rvalid; + wire crossbar_s02_axi_rready; + wire [CROSSBAR_M_ID_WIDTH-1:0] crossbar_m00_axi_awid; + wire [CROSSBAR_ADDR_WIDTH-1:0] crossbar_m00_axi_awaddr; + wire [7:0] crossbar_m00_axi_awlen; + wire [2:0] crossbar_m00_axi_awsize; + wire [1:0] crossbar_m00_axi_awburst; + wire crossbar_m00_axi_awlock; + wire [3:0] crossbar_m00_axi_awcache; + wire [2:0] crossbar_m00_axi_awprot; + wire [3:0] crossbar_m00_axi_awqos; + wire [3:0] crossbar_m00_axi_awregion; + wire [CROSSBAR_AWUSER_WIDTH-1:0] crossbar_m00_axi_awuser; + wire crossbar_m00_axi_awvalid; + wire crossbar_m00_axi_awready; + wire [CROSSBAR_DATA_WIDTH-1:0] crossbar_m00_axi_wdata; + wire [CROSSBAR_STRB_WIDTH-1:0] crossbar_m00_axi_wstrb; + wire crossbar_m00_axi_wlast; + wire [CROSSBAR_WUSER_WIDTH-1:0] crossbar_m00_axi_wuser; + wire crossbar_m00_axi_wvalid; + wire crossbar_m00_axi_wready; + wire [CROSSBAR_M_ID_WIDTH-1:0] crossbar_m00_axi_bid; + wire [1:0] crossbar_m00_axi_bresp; + wire [CROSSBAR_BUSER_WIDTH-1:0] crossbar_m00_axi_buser; + wire crossbar_m00_axi_bvalid; + wire crossbar_m00_axi_bready; + wire [CROSSBAR_M_ID_WIDTH-1:0] crossbar_m00_axi_arid; + wire [CROSSBAR_ADDR_WIDTH-1:0] crossbar_m00_axi_araddr; + wire [7:0] crossbar_m00_axi_arlen; + wire [2:0] crossbar_m00_axi_arsize; + wire [1:0] crossbar_m00_axi_arburst; + wire crossbar_m00_axi_arlock; + wire [3:0] crossbar_m00_axi_arcache; + wire [2:0] crossbar_m00_axi_arprot; + wire [3:0] crossbar_m00_axi_arqos; + wire [3:0] crossbar_m00_axi_arregion; + wire [CROSSBAR_ARUSER_WIDTH-1:0] crossbar_m00_axi_aruser; + wire crossbar_m00_axi_arvalid; + wire crossbar_m00_axi_arready; + wire [CROSSBAR_M_ID_WIDTH-1:0] crossbar_m00_axi_rid; + wire [CROSSBAR_DATA_WIDTH-1:0] crossbar_m00_axi_rdata; + wire [1:0] crossbar_m00_axi_rresp; + wire crossbar_m00_axi_rlast; + wire [CROSSBAR_RUSER_WIDTH-1:0] crossbar_m00_axi_ruser; + wire crossbar_m00_axi_rvalid; + wire crossbar_m00_axi_rready; + wire [CROSSBAR_M_ID_WIDTH-1:0] crossbar_m01_axi_awid; + wire [CROSSBAR_ADDR_WIDTH-1:0] crossbar_m01_axi_awaddr; + wire [7:0] crossbar_m01_axi_awlen; + wire [2:0] crossbar_m01_axi_awsize; + wire [1:0] crossbar_m01_axi_awburst; + wire crossbar_m01_axi_awlock; + wire [3:0] crossbar_m01_axi_awcache; + wire [2:0] crossbar_m01_axi_awprot; + wire [3:0] crossbar_m01_axi_awqos; + wire [3:0] crossbar_m01_axi_awregion; + wire [CROSSBAR_AWUSER_WIDTH-1:0] crossbar_m01_axi_awuser; + wire crossbar_m01_axi_awvalid; + wire crossbar_m01_axi_awready; + wire [CROSSBAR_DATA_WIDTH-1:0] crossbar_m01_axi_wdata; + wire [CROSSBAR_STRB_WIDTH-1:0] crossbar_m01_axi_wstrb; + wire crossbar_m01_axi_wlast; + wire [CROSSBAR_WUSER_WIDTH-1:0] crossbar_m01_axi_wuser; + wire crossbar_m01_axi_wvalid; + wire crossbar_m01_axi_wready; + wire [CROSSBAR_M_ID_WIDTH-1:0] crossbar_m01_axi_bid; + wire [1:0] crossbar_m01_axi_bresp; + wire [CROSSBAR_BUSER_WIDTH-1:0] crossbar_m01_axi_buser; + wire crossbar_m01_axi_bvalid; + wire crossbar_m01_axi_bready; + wire [CROSSBAR_M_ID_WIDTH-1:0] crossbar_m01_axi_arid; + wire [CROSSBAR_ADDR_WIDTH-1:0] crossbar_m01_axi_araddr; + wire [7:0] crossbar_m01_axi_arlen; + wire [2:0] crossbar_m01_axi_arsize; + wire [1:0] crossbar_m01_axi_arburst; + wire crossbar_m01_axi_arlock; + wire [3:0] crossbar_m01_axi_arcache; + wire [2:0] crossbar_m01_axi_arprot; + wire [3:0] crossbar_m01_axi_arqos; + wire [3:0] crossbar_m01_axi_arregion; + wire [CROSSBAR_ARUSER_WIDTH-1:0] crossbar_m01_axi_aruser; + wire crossbar_m01_axi_arvalid; + wire crossbar_m01_axi_arready; + wire [CROSSBAR_M_ID_WIDTH-1:0] crossbar_m01_axi_rid; + wire [CROSSBAR_DATA_WIDTH-1:0] crossbar_m01_axi_rdata; + wire [1:0] crossbar_m01_axi_rresp; + wire crossbar_m01_axi_rlast; + wire [CROSSBAR_RUSER_WIDTH-1:0] crossbar_m01_axi_ruser; + wire crossbar_m01_axi_rvalid; + wire crossbar_m01_axi_rready; + wire [CROSSBAR_M_ID_WIDTH-1:0] crossbar_m02_axi_awid; + wire [CROSSBAR_ADDR_WIDTH-1:0] crossbar_m02_axi_awaddr; + wire [7:0] crossbar_m02_axi_awlen; + wire [2:0] crossbar_m02_axi_awsize; + wire [1:0] crossbar_m02_axi_awburst; + wire crossbar_m02_axi_awlock; + wire [3:0] crossbar_m02_axi_awcache; + wire [2:0] crossbar_m02_axi_awprot; + wire [3:0] crossbar_m02_axi_awqos; + wire [3:0] crossbar_m02_axi_awregion; + wire [CROSSBAR_AWUSER_WIDTH-1:0] crossbar_m02_axi_awuser; + wire crossbar_m02_axi_awvalid; + wire crossbar_m02_axi_awready; + wire [CROSSBAR_DATA_WIDTH-1:0] crossbar_m02_axi_wdata; + wire [CROSSBAR_STRB_WIDTH-1:0] crossbar_m02_axi_wstrb; + wire crossbar_m02_axi_wlast; + wire [CROSSBAR_WUSER_WIDTH-1:0] crossbar_m02_axi_wuser; + wire crossbar_m02_axi_wvalid; + wire crossbar_m02_axi_wready; + wire [CROSSBAR_M_ID_WIDTH-1:0] crossbar_m02_axi_bid; + wire [1:0] crossbar_m02_axi_bresp; + wire [CROSSBAR_BUSER_WIDTH-1:0] crossbar_m02_axi_buser; + wire crossbar_m02_axi_bvalid; + wire crossbar_m02_axi_bready; + wire [CROSSBAR_M_ID_WIDTH-1:0] crossbar_m02_axi_arid; + wire [CROSSBAR_ADDR_WIDTH-1:0] crossbar_m02_axi_araddr; + wire [7:0] crossbar_m02_axi_arlen; + wire [2:0] crossbar_m02_axi_arsize; + wire [1:0] crossbar_m02_axi_arburst; + wire crossbar_m02_axi_arlock; + wire [3:0] crossbar_m02_axi_arcache; + wire [2:0] crossbar_m02_axi_arprot; + wire [3:0] crossbar_m02_axi_arqos; + wire [3:0] crossbar_m02_axi_arregion; + wire [CROSSBAR_ARUSER_WIDTH-1:0] crossbar_m02_axi_aruser; + wire crossbar_m02_axi_arvalid; + wire crossbar_m02_axi_arready; + wire [CROSSBAR_M_ID_WIDTH-1:0] crossbar_m02_axi_rid; + wire [CROSSBAR_DATA_WIDTH-1:0] crossbar_m02_axi_rdata; + wire [1:0] crossbar_m02_axi_rresp; + wire crossbar_m02_axi_rlast; + wire [CROSSBAR_RUSER_WIDTH-1:0] crossbar_m02_axi_ruser; + wire crossbar_m02_axi_rvalid; + wire crossbar_m02_axi_rready; + + + assign crossbar_clk = clk; + assign crossbar_rst = rst; + + axi4_if_to_flat #( + .ADDR_W (ADDR_WIDTH), + .DATA_W (DATA_WIDTH) + ) i_axi4_if_to_flat_00 ( + .axi (s_axi[0]), + .m_axi_awid (crossbar_s00_axi_awid), + .m_axi_awaddr (crossbar_s00_axi_awaddr), + .m_axi_awlen (crossbar_s00_axi_awlen), + .m_axi_awsize (crossbar_s00_axi_awsize), + .m_axi_awburst (crossbar_s00_axi_awburst), + .m_axi_awlock (crossbar_s00_axi_awlock), + .m_axi_awcache (crossbar_s00_axi_awcache), + .m_axi_awprot (crossbar_s00_axi_awprot), + .m_axi_awqos (crossbar_s00_axi_awqos), + .m_axi_awregion (crossbar_s00_axi_awregion), + .m_axi_awuser (crossbar_s00_axi_awuser), + .m_axi_awvalid (crossbar_s00_axi_awvalid), + .m_axi_awready (crossbar_s00_axi_awready), + .m_axi_wdata (crossbar_s00_axi_wdata), + .m_axi_wstrb (crossbar_s00_axi_wstrb), + .m_axi_wlast (crossbar_s00_axi_wlast), + .m_axi_wuser (crossbar_s00_axi_wuser), + .m_axi_wvalid (crossbar_s00_axi_wvalid), + .m_axi_wready (crossbar_s00_axi_wready), + .m_axi_bid (crossbar_s00_axi_bid), + .m_axi_bresp (crossbar_s00_axi_bresp), + .m_axi_buser (crossbar_s00_axi_buser), + .m_axi_bvalid (crossbar_s00_axi_bvalid), + .m_axi_bready (crossbar_s00_axi_bready), + .m_axi_arid (crossbar_s00_axi_arid), + .m_axi_araddr (crossbar_s00_axi_araddr), + .m_axi_arlen (crossbar_s00_axi_arlen), + .m_axi_arsize (crossbar_s00_axi_arsize), + .m_axi_arburst (crossbar_s00_axi_arburst), + .m_axi_arlock (crossbar_s00_axi_arlock), + .m_axi_arcache (crossbar_s00_axi_arcache), + .m_axi_arprot (crossbar_s00_axi_arprot), + .m_axi_arqos (crossbar_s00_axi_arqos), + .m_axi_arregion (crossbar_s00_axi_arregion), + .m_axi_aruser (crossbar_s00_axi_aruser), + .m_axi_arvalid (crossbar_s00_axi_arvalid), + .m_axi_arready (crossbar_s00_axi_arready), + .m_axi_rid (crossbar_s00_axi_rid), + .m_axi_rdata (crossbar_s00_axi_rdata), + .m_axi_rresp (crossbar_s00_axi_rresp), + .m_axi_rlast (crossbar_s00_axi_rlast), + .m_axi_ruser (crossbar_s00_axi_ruser), + .m_axi_rvalid (crossbar_s00_axi_rvalid), + .m_axi_rready (crossbar_s00_axi_rready) + ); + + axi4_if_to_flat #( + .ADDR_W (ADDR_WIDTH), + .DATA_W (DATA_WIDTH) + ) i_axi4_if_to_flat_01 ( + .axi (s_axi[1]), + .m_axi_awid (crossbar_s01_axi_awid), + .m_axi_awaddr (crossbar_s01_axi_awaddr), + .m_axi_awlen (crossbar_s01_axi_awlen), + .m_axi_awsize (crossbar_s01_axi_awsize), + .m_axi_awburst (crossbar_s01_axi_awburst), + .m_axi_awlock (crossbar_s01_axi_awlock), + .m_axi_awcache (crossbar_s01_axi_awcache), + .m_axi_awprot (crossbar_s01_axi_awprot), + .m_axi_awqos (crossbar_s01_axi_awqos), + .m_axi_awregion (crossbar_s01_axi_awregion), + .m_axi_awuser (crossbar_s01_axi_awuser), + .m_axi_awvalid (crossbar_s01_axi_awvalid), + .m_axi_awready (crossbar_s01_axi_awready), + .m_axi_wdata (crossbar_s01_axi_wdata), + .m_axi_wstrb (crossbar_s01_axi_wstrb), + .m_axi_wlast (crossbar_s01_axi_wlast), + .m_axi_wuser (crossbar_s01_axi_wuser), + .m_axi_wvalid (crossbar_s01_axi_wvalid), + .m_axi_wready (crossbar_s01_axi_wready), + .m_axi_bid (crossbar_s01_axi_bid), + .m_axi_bresp (crossbar_s01_axi_bresp), + .m_axi_buser (crossbar_s01_axi_buser), + .m_axi_bvalid (crossbar_s01_axi_bvalid), + .m_axi_bready (crossbar_s01_axi_bready), + .m_axi_arid (crossbar_s01_axi_arid), + .m_axi_araddr (crossbar_s01_axi_araddr), + .m_axi_arlen (crossbar_s01_axi_arlen), + .m_axi_arsize (crossbar_s01_axi_arsize), + .m_axi_arburst (crossbar_s01_axi_arburst), + .m_axi_arlock (crossbar_s01_axi_arlock), + .m_axi_arcache (crossbar_s01_axi_arcache), + .m_axi_arprot (crossbar_s01_axi_arprot), + .m_axi_arqos (crossbar_s01_axi_arqos), + .m_axi_arregion (crossbar_s01_axi_arregion), + .m_axi_aruser (crossbar_s01_axi_aruser), + .m_axi_arvalid (crossbar_s01_axi_arvalid), + .m_axi_arready (crossbar_s01_axi_arready), + .m_axi_rid (crossbar_s01_axi_rid), + .m_axi_rdata (crossbar_s01_axi_rdata), + .m_axi_rresp (crossbar_s01_axi_rresp), + .m_axi_rlast (crossbar_s01_axi_rlast), + .m_axi_ruser (crossbar_s01_axi_ruser), + .m_axi_rvalid (crossbar_s01_axi_rvalid), + .m_axi_rready (crossbar_s01_axi_rready) + ); + + axi4_if_to_flat #( + .ADDR_W (ADDR_WIDTH), + .DATA_W (DATA_WIDTH) + ) i_axi4_if_to_flat_00 ( + .axi (s_axi[2]), + .m_axi_awid (crossbar_s02_axi_awid), + .m_axi_awaddr (crossbar_s02_axi_awaddr), + .m_axi_awlen (crossbar_s02_axi_awlen), + .m_axi_awsize (crossbar_s02_axi_awsize), + .m_axi_awburst (crossbar_s02_axi_awburst), + .m_axi_awlock (crossbar_s02_axi_awlock), + .m_axi_awcache (crossbar_s02_axi_awcache), + .m_axi_awprot (crossbar_s02_axi_awprot), + .m_axi_awqos (crossbar_s02_axi_awqos), + .m_axi_awregion (crossbar_s02_axi_awregion), + .m_axi_awuser (crossbar_s02_axi_awuser), + .m_axi_awvalid (crossbar_s02_axi_awvalid), + .m_axi_awready (crossbar_s02_axi_awready), + .m_axi_wdata (crossbar_s02_axi_wdata), + .m_axi_wstrb (crossbar_s02_axi_wstrb), + .m_axi_wlast (crossbar_s02_axi_wlast), + .m_axi_wuser (crossbar_s02_axi_wuser), + .m_axi_wvalid (crossbar_s02_axi_wvalid), + .m_axi_wready (crossbar_s02_axi_wready), + .m_axi_bid (crossbar_s02_axi_bid), + .m_axi_bresp (crossbar_s02_axi_bresp), + .m_axi_buser (crossbar_s02_axi_buser), + .m_axi_bvalid (crossbar_s02_axi_bvalid), + .m_axi_bready (crossbar_s02_axi_bready), + .m_axi_arid (crossbar_s02_axi_arid), + .m_axi_araddr (crossbar_s02_axi_araddr), + .m_axi_arlen (crossbar_s02_axi_arlen), + .m_axi_arsize (crossbar_s02_axi_arsize), + .m_axi_arburst (crossbar_s02_axi_arburst), + .m_axi_arlock (crossbar_s02_axi_arlock), + .m_axi_arcache (crossbar_s02_axi_arcache), + .m_axi_arprot (crossbar_s02_axi_arprot), + .m_axi_arqos (crossbar_s02_axi_arqos), + .m_axi_arregion (crossbar_s02_axi_arregion), + .m_axi_aruser (crossbar_s02_axi_aruser), + .m_axi_arvalid (crossbar_s02_axi_arvalid), + .m_axi_arready (crossbar_s02_axi_arready), + .m_axi_rid (crossbar_s02_axi_rid), + .m_axi_rdata (crossbar_s02_axi_rdata), + .m_axi_rresp (crossbar_s02_axi_rresp), + .m_axi_rlast (crossbar_s02_axi_rlast), + .m_axi_ruser (crossbar_s02_axi_ruser), + .m_axi_rvalid (crossbar_s02_axi_rvalid), + .m_axi_rready (crossbar_s02_axi_rready) + ); + + axi4_flat_to_if_slave #( + .ADDR_W (ADDR_WIDTH), + .DATA_W (DATA_WIDTH) + ) i_axi4_if_to_flat_master_00 ( + .axi (s_axi[0]), + .m_axi_awid (crossbar_s00_axi_awid), + .m_axi_awaddr (crossbar_s00_axi_awaddr), + .m_axi_awlen (crossbar_s00_axi_awlen), + .m_axi_awsize (crossbar_s00_axi_awsize), + .m_axi_awburst (crossbar_s00_axi_awburst), + .m_axi_awlock (crossbar_s00_axi_awlock), + .m_axi_awcache (crossbar_s00_axi_awcache), + .m_axi_awprot (crossbar_s00_axi_awprot), + .m_axi_awqos (crossbar_s00_axi_awqos), + .m_axi_awregion (crossbar_s00_axi_awregion), + .m_axi_awuser (crossbar_s00_axi_awuser), + .m_axi_awvalid (crossbar_s00_axi_awvalid), + .m_axi_awready (crossbar_s00_axi_awready), + .m_axi_wdata (crossbar_s00_axi_wdata), + .m_axi_wstrb (crossbar_s00_axi_wstrb), + .m_axi_wlast (crossbar_s00_axi_wlast), + .m_axi_wuser (crossbar_s00_axi_wuser), + .m_axi_wvalid (crossbar_s00_axi_wvalid), + .m_axi_wready (crossbar_s00_axi_wready), + .m_axi_bid (crossbar_s00_axi_bid), + .m_axi_bresp (crossbar_s00_axi_bresp), + .m_axi_buser (crossbar_s00_axi_buser), + .m_axi_bvalid (crossbar_s00_axi_bvalid), + .m_axi_bready (crossbar_s00_axi_bready), + .m_axi_arid (crossbar_s00_axi_arid), + .m_axi_araddr (crossbar_s00_axi_araddr), + .m_axi_arlen (crossbar_s00_axi_arlen), + .m_axi_arsize (crossbar_s00_axi_arsize), + .m_axi_arburst (crossbar_s00_axi_arburst), + .m_axi_arlock (crossbar_s00_axi_arlock), + .m_axi_arcache (crossbar_s00_axi_arcache), + .m_axi_arprot (crossbar_s00_axi_arprot), + .m_axi_arqos (crossbar_s00_axi_arqos), + .m_axi_arregion (crossbar_s00_axi_arregion), + .m_axi_aruser (crossbar_s00_axi_aruser), + .m_axi_arvalid (crossbar_s00_axi_arvalid), + .m_axi_arready (crossbar_s00_axi_arready), + .m_axi_rid (crossbar_s00_axi_rid), + .m_axi_rdata (crossbar_s00_axi_rdata), + .m_axi_rresp (crossbar_s00_axi_rresp), + .m_axi_rlast (crossbar_s00_axi_rlast), + .m_axi_ruser (crossbar_s00_axi_ruser), + .m_axi_rvalid (crossbar_s00_axi_rvalid), + .m_axi_rready (crossbar_s00_axi_rready) + ); + + axi_crossbar_core_wrapper # + ( + .DATA_WIDTH = (CROSSBAR_DATA_WIDTH), + .ADDR_WIDTH = (CROSSBAR_ADDR_WIDTH), + .STRB_WIDTH = (CROSSBAR_STRB_WIDTH), + .S_ID_WIDTH = (CROSSBAR_S_ID_WIDTH), + .M_ID_WIDTH = (CROSSBAR_M_ID_WIDTH), + .AWUSER_ENABLE = (CROSSBAR_AWUSER_ENABLE), + .AWUSER_WIDTH = (CROSSBAR_AWUSER_WIDTH), + .WUSER_ENABLE = (CROSSBAR_WUSER_ENABLE), + .WUSER_WIDTH = (CROSSBAR_WUSER_WIDTH), + .BUSER_ENABLE = (CROSSBAR_BUSER_ENABLE), + .BUSER_WIDTH = (CROSSBAR_BUSER_WIDTH), + .ARUSER_ENABLE = (CROSSBAR_ARUSER_ENABLE), + .ARUSER_WIDTH = (CROSSBAR_ARUSER_WIDTH), + .RUSER_ENABLE = (CROSSBAR_RUSER_ENABLE), + .RUSER_WIDTH = (CROSSBAR_RUSER_WIDTH), + .S00_THREADS = (CROSSBAR_S00_THREADS), + .S00_ACCEPT = (CROSSBAR_S00_ACCEPT), + .S01_THREADS = (CROSSBAR_S01_THREADS), + .S01_ACCEPT = (CROSSBAR_S01_ACCEPT), + .S02_THREADS = (CROSSBAR_S02_THREADS), + .S02_ACCEPT = (CROSSBAR_S02_ACCEPT), + .M_REGIONS = (CROSSBAR_M_REGIONS), + .M00_BASE_ADDR = (CROSSBAR_M00_BASE_ADDR), + .M00_ADDR_WIDTH = (CROSSBAR_M00_ADDR_WIDTH), + .M00_CONNECT_READ = (CROSSBAR_M00_CONNECT_READ), + .M00_CONNECT_WRITE = (CROSSBAR_M00_CONNECT_WRITE), + .M00_ISSUE = (CROSSBAR_M00_ISSUE), + .M00_SECURE = (CROSSBAR_M00_SECURE), + .M01_BASE_ADDR = (CROSSBAR_M01_BASE_ADDR), + .M01_ADDR_WIDTH = (CROSSBAR_M01_ADDR_WIDTH), + .M01_CONNECT_READ = (CROSSBAR_M01_CONNECT_READ), + .M01_CONNECT_WRITE = (CROSSBAR_M01_CONNECT_WRITE), + .M01_ISSUE = (CROSSBAR_M01_ISSUE), + .M01_SECURE = (CROSSBAR_M01_SECURE), + .M02_BASE_ADDR = (CROSSBAR_M02_BASE_ADDR), + .M02_ADDR_WIDTH = (CROSSBAR_M02_ADDR_WIDTH), + .M02_CONNECT_READ = (CROSSBAR_M02_CONNECT_READ), + .M02_CONNECT_WRITE = (CROSSBAR_M02_CONNECT_WRITE), + .M02_ISSUE = (CROSSBAR_M02_ISSUE), + .M02_SECURE = (CROSSBAR_M02_SECURE), + .S00_AW_REG_TYPE = (CROSSBAR_S00_AW_REG_TYPE), + .S00_W_REG_TYPE = (CROSSBAR_S00_W_REG_TYPE), + .S00_B_REG_TYPE = (CROSSBAR_S00_B_REG_TYPE), + .S00_AR_REG_TYPE = (CROSSBAR_S00_AR_REG_TYPE), + .S00_R_REG_TYPE = (CROSSBAR_S00_R_REG_TYPE), + .S01_AW_REG_TYPE = (CROSSBAR_S01_AW_REG_TYPE), + .S01_W_REG_TYPE = (CROSSBAR_S01_W_REG_TYPE), + .S01_B_REG_TYPE = (CROSSBAR_S01_B_REG_TYPE), + .S01_AR_REG_TYPE = (CROSSBAR_S01_AR_REG_TYPE), + .S01_R_REG_TYPE = (CROSSBAR_S01_R_REG_TYPE), + .S02_AW_REG_TYPE = (CROSSBAR_S02_AW_REG_TYPE), + .S02_W_REG_TYPE = (CROSSBAR_S02_W_REG_TYPE), + .S02_B_REG_TYPE = (CROSSBAR_S02_B_REG_TYPE), + .S02_AR_REG_TYPE = (CROSSBAR_S02_AR_REG_TYPE), + .S02_R_REG_TYPE = (CROSSBAR_S02_R_REG_TYPE), + .M00_AW_REG_TYPE = (CROSSBAR_M00_AW_REG_TYPE), + .M00_W_REG_TYPE = (CROSSBAR_M00_W_REG_TYPE), + .M00_B_REG_TYPE = (CROSSBAR_M00_B_REG_TYPE), + .M00_AR_REG_TYPE = (CROSSBAR_M00_AR_REG_TYPE), + .M00_R_REG_TYPE = (CROSSBAR_M00_R_REG_TYPE), + .M01_AW_REG_TYPE = (CROSSBAR_M01_AW_REG_TYPE), + .M01_W_REG_TYPE = (CROSSBAR_M01_W_REG_TYPE), + .M01_B_REG_TYPE = (CROSSBAR_M01_B_REG_TYPE), + .M01_AR_REG_TYPE = (CROSSBAR_M01_AR_REG_TYPE), + .M01_R_REG_TYPE = (CROSSBAR_M01_R_REG_TYPE), + .M02_AW_REG_TYPE = (CROSSBAR_M02_AW_REG_TYPE), + .M02_W_REG_TYPE = (CROSSBAR_M02_W_REG_TYPE), + .M02_B_REG_TYPE = (CROSSBAR_M02_B_REG_TYPE), + .M02_AR_REG_TYPE = (CROSSBAR_M02_AR_REG_TYPE), + .M02_R_REG_TYPE = (CROSSBAR_M02_R_REG_TYPE) + + ) i_axi_crossbar_core_wrapper ( + .clk (crossbar_clk), + .rst (crossbar_rst), + .s00_axi_awid (crossbar_s00_axi_awid), + .s00_axi_awaddr (crossbar_s00_axi_awaddr), + .s00_axi_awlen (crossbar_s00_axi_awlen), + .s00_axi_awsize (crossbar_s00_axi_awsize), + .s00_axi_awburst (crossbar_s00_axi_awburst), + .s00_axi_awlock (crossbar_s00_axi_awlock), + .s00_axi_awcache (crossbar_s00_axi_awcache), + .s00_axi_awprot (crossbar_s00_axi_awprot), + .s00_axi_awqos (crossbar_s00_axi_awqos), + .s00_axi_awuser (crossbar_s00_axi_awuser), + .s00_axi_awvalid (crossbar_s00_axi_awvalid), + .s00_axi_awready (crossbar_s00_axi_awready), + .s00_axi_wdata (crossbar_s00_axi_wdata), + .s00_axi_wstrb (crossbar_s00_axi_wstrb), + .s00_axi_wlast (crossbar_s00_axi_wlast), + .s00_axi_wuser (crossbar_s00_axi_wuser), + .s00_axi_wvalid (crossbar_s00_axi_wvalid), + .s00_axi_wready (crossbar_s00_axi_wready), + .s00_axi_bid (crossbar_s00_axi_bid), + .s00_axi_bresp (crossbar_s00_axi_bresp), + .s00_axi_buser (crossbar_s00_axi_buser), + .s00_axi_bvalid (crossbar_s00_axi_bvalid), + .s00_axi_bready (crossbar_s00_axi_bready), + .s00_axi_arid (crossbar_s00_axi_arid), + .s00_axi_araddr (crossbar_s00_axi_araddr), + .s00_axi_arlen (crossbar_s00_axi_arlen), + .s00_axi_arsize (crossbar_s00_axi_arsize), + .s00_axi_arburst (crossbar_s00_axi_arburst), + .s00_axi_arlock (crossbar_s00_axi_arlock), + .s00_axi_arcache (crossbar_s00_axi_arcache), + .s00_axi_arprot (crossbar_s00_axi_arprot), + .s00_axi_arqos (crossbar_s00_axi_arqos), + .s00_axi_aruser (crossbar_s00_axi_aruser), + .s00_axi_arvalid (crossbar_s00_axi_arvalid), + .s00_axi_arready (crossbar_s00_axi_arready), + .s00_axi_rid (crossbar_s00_axi_rid), + .s00_axi_rdata (crossbar_s00_axi_rdata), + .s00_axi_rresp (crossbar_s00_axi_rresp), + .s00_axi_rlast (crossbar_s00_axi_rlast), + .s00_axi_ruser (crossbar_s00_axi_ruser), + .s00_axi_rvalid (crossbar_s00_axi_rvalid), + .s00_axi_rready (crossbar_s00_axi_rready), + .s01_axi_awid (crossbar_s01_axi_awid), + .s01_axi_awaddr (crossbar_s01_axi_awaddr), + .s01_axi_awlen (crossbar_s01_axi_awlen), + .s01_axi_awsize (crossbar_s01_axi_awsize), + .s01_axi_awburst (crossbar_s01_axi_awburst), + .s01_axi_awlock (crossbar_s01_axi_awlock), + .s01_axi_awcache (crossbar_s01_axi_awcache), + .s01_axi_awprot (crossbar_s01_axi_awprot), + .s01_axi_awqos (crossbar_s01_axi_awqos), + .s01_axi_awuser (crossbar_s01_axi_awuser), + .s01_axi_awvalid (crossbar_s01_axi_awvalid), + .s01_axi_awready (crossbar_s01_axi_awready), + .s01_axi_wdata (crossbar_s01_axi_wdata), + .s01_axi_wstrb (crossbar_s01_axi_wstrb), + .s01_axi_wlast (crossbar_s01_axi_wlast), + .s01_axi_wuser (crossbar_s01_axi_wuser), + .s01_axi_wvalid (crossbar_s01_axi_wvalid), + .s01_axi_wready (crossbar_s01_axi_wready), + .s01_axi_bid (crossbar_s01_axi_bid), + .s01_axi_bresp (crossbar_s01_axi_bresp), + .s01_axi_buser (crossbar_s01_axi_buser), + .s01_axi_bvalid (crossbar_s01_axi_bvalid), + .s01_axi_bready (crossbar_s01_axi_bready), + .s01_axi_arid (crossbar_s01_axi_arid), + .s01_axi_araddr (crossbar_s01_axi_araddr), + .s01_axi_arlen (crossbar_s01_axi_arlen), + .s01_axi_arsize (crossbar_s01_axi_arsize), + .s01_axi_arburst (crossbar_s01_axi_arburst), + .s01_axi_arlock (crossbar_s01_axi_arlock), + .s01_axi_arcache (crossbar_s01_axi_arcache), + .s01_axi_arprot (crossbar_s01_axi_arprot), + .s01_axi_arqos (crossbar_s01_axi_arqos), + .s01_axi_aruser (crossbar_s01_axi_aruser), + .s01_axi_arvalid (crossbar_s01_axi_arvalid), + .s01_axi_arready (crossbar_s01_axi_arready), + .s01_axi_rid (crossbar_s01_axi_rid), + .s01_axi_rdata (crossbar_s01_axi_rdata), + .s01_axi_rresp (crossbar_s01_axi_rresp), + .s01_axi_rlast (crossbar_s01_axi_rlast), + .s01_axi_ruser (crossbar_s01_axi_ruser), + .s01_axi_rvalid (crossbar_s01_axi_rvalid), + .s01_axi_rready (crossbar_s01_axi_rready), + .s02_axi_awid (crossbar_s02_axi_awid), + .s02_axi_awaddr (crossbar_s02_axi_awaddr), + .s02_axi_awlen (crossbar_s02_axi_awlen), + .s02_axi_awsize (crossbar_s02_axi_awsize), + .s02_axi_awburst (crossbar_s02_axi_awburst), + .s02_axi_awlock (crossbar_s02_axi_awlock), + .s02_axi_awcache (crossbar_s02_axi_awcache), + .s02_axi_awprot (crossbar_s02_axi_awprot), + .s02_axi_awqos (crossbar_s02_axi_awqos), + .s02_axi_awuser (crossbar_s02_axi_awuser), + .s02_axi_awvalid (crossbar_s02_axi_awvalid), + .s02_axi_awready (crossbar_s02_axi_awready), + .s02_axi_wdata (crossbar_s02_axi_wdata), + .s02_axi_wstrb (crossbar_s02_axi_wstrb), + .s02_axi_wlast (crossbar_s02_axi_wlast), + .s02_axi_wuser (crossbar_s02_axi_wuser), + .s02_axi_wvalid (crossbar_s02_axi_wvalid), + .s02_axi_wready (crossbar_s02_axi_wready), + .s02_axi_bid (crossbar_s02_axi_bid), + .s02_axi_bresp (crossbar_s02_axi_bresp), + .s02_axi_buser (crossbar_s02_axi_buser), + .s02_axi_bvalid (crossbar_s02_axi_bvalid), + .s02_axi_bready (crossbar_s02_axi_bready), + .s02_axi_arid (crossbar_s02_axi_arid), + .s02_axi_araddr (crossbar_s02_axi_araddr), + .s02_axi_arlen (crossbar_s02_axi_arlen), + .s02_axi_arsize (crossbar_s02_axi_arsize), + .s02_axi_arburst (crossbar_s02_axi_arburst), + .s02_axi_arlock (crossbar_s02_axi_arlock), + .s02_axi_arcache (crossbar_s02_axi_arcache), + .s02_axi_arprot (crossbar_s02_axi_arprot), + .s02_axi_arqos (crossbar_s02_axi_arqos), + .s02_axi_aruser (crossbar_s02_axi_aruser), + .s02_axi_arvalid (crossbar_s02_axi_arvalid), + .s02_axi_arready (crossbar_s02_axi_arready), + .s02_axi_rid (crossbar_s02_axi_rid), + .s02_axi_rdata (crossbar_s02_axi_rdata), + .s02_axi_rresp (crossbar_s02_axi_rresp), + .s02_axi_rlast (crossbar_s02_axi_rlast), + .s02_axi_ruser (crossbar_s02_axi_ruser), + .s02_axi_rvalid (crossbar_s02_axi_rvalid), + .s02_axi_rready (crossbar_s02_axi_rready), + .m00_axi_awid (crossbar_m00_axi_awid), + .m00_axi_awaddr (crossbar_m00_axi_awaddr), + .m00_axi_awlen (crossbar_m00_axi_awlen), + .m00_axi_awsize (crossbar_m00_axi_awsize), + .m00_axi_awburst (crossbar_m00_axi_awburst), + .m00_axi_awlock (crossbar_m00_axi_awlock), + .m00_axi_awcache (crossbar_m00_axi_awcache), + .m00_axi_awprot (crossbar_m00_axi_awprot), + .m00_axi_awqos (crossbar_m00_axi_awqos), + .m00_axi_awregion (crossbar_m00_axi_awregion), + .m00_axi_awuser (crossbar_m00_axi_awuser), + .m00_axi_awvalid (crossbar_m00_axi_awvalid), + .m00_axi_awready (crossbar_m00_axi_awready), + .m00_axi_wdata (crossbar_m00_axi_wdata), + .m00_axi_wstrb (crossbar_m00_axi_wstrb), + .m00_axi_wlast (crossbar_m00_axi_wlast), + .m00_axi_wuser (crossbar_m00_axi_wuser), + .m00_axi_wvalid (crossbar_m00_axi_wvalid), + .m00_axi_wready (crossbar_m00_axi_wready), + .m00_axi_bid (crossbar_m00_axi_bid), + .m00_axi_bresp (crossbar_m00_axi_bresp), + .m00_axi_buser (crossbar_m00_axi_buser), + .m00_axi_bvalid (crossbar_m00_axi_bvalid), + .m00_axi_bready (crossbar_m00_axi_bready), + .m00_axi_arid (crossbar_m00_axi_arid), + .m00_axi_araddr (crossbar_m00_axi_araddr), + .m00_axi_arlen (crossbar_m00_axi_arlen), + .m00_axi_arsize (crossbar_m00_axi_arsize), + .m00_axi_arburst (crossbar_m00_axi_arburst), + .m00_axi_arlock (crossbar_m00_axi_arlock), + .m00_axi_arcache (crossbar_m00_axi_arcache), + .m00_axi_arprot (crossbar_m00_axi_arprot), + .m00_axi_arqos (crossbar_m00_axi_arqos), + .m00_axi_arregion (crossbar_m00_axi_arregion), + .m00_axi_aruser (crossbar_m00_axi_aruser), + .m00_axi_arvalid (crossbar_m00_axi_arvalid), + .m00_axi_arready (crossbar_m00_axi_arready), + .m00_axi_rid (crossbar_m00_axi_rid), + .m00_axi_rdata (crossbar_m00_axi_rdata), + .m00_axi_rresp (crossbar_m00_axi_rresp), + .m00_axi_rlast (crossbar_m00_axi_rlast), + .m00_axi_ruser (crossbar_m00_axi_ruser), + .m00_axi_rvalid (crossbar_m00_axi_rvalid), + .m00_axi_rready (crossbar_m00_axi_rready), + .m01_axi_awid (crossbar_m01_axi_awid), + .m01_axi_awaddr (crossbar_m01_axi_awaddr), + .m01_axi_awlen (crossbar_m01_axi_awlen), + .m01_axi_awsize (crossbar_m01_axi_awsize), + .m01_axi_awburst (crossbar_m01_axi_awburst), + .m01_axi_awlock (crossbar_m01_axi_awlock), + .m01_axi_awcache (crossbar_m01_axi_awcache), + .m01_axi_awprot (crossbar_m01_axi_awprot), + .m01_axi_awqos (crossbar_m01_axi_awqos), + .m01_axi_awregion (crossbar_m01_axi_awregion), + .m01_axi_awuser (crossbar_m01_axi_awuser), + .m01_axi_awvalid (crossbar_m01_axi_awvalid), + .m01_axi_awready (crossbar_m01_axi_awready), + .m01_axi_wdata (crossbar_m01_axi_wdata), + .m01_axi_wstrb (crossbar_m01_axi_wstrb), + .m01_axi_wlast (crossbar_m01_axi_wlast), + .m01_axi_wuser (crossbar_m01_axi_wuser), + .m01_axi_wvalid (crossbar_m01_axi_wvalid), + .m01_axi_wready (crossbar_m01_axi_wready), + .m01_axi_bid (crossbar_m01_axi_bid), + .m01_axi_bresp (crossbar_m01_axi_bresp), + .m01_axi_buser (crossbar_m01_axi_buser), + .m01_axi_bvalid (crossbar_m01_axi_bvalid), + .m01_axi_bready (crossbar_m01_axi_bready), + .m01_axi_arid (crossbar_m01_axi_arid), + .m01_axi_araddr (crossbar_m01_axi_araddr), + .m01_axi_arlen (crossbar_m01_axi_arlen), + .m01_axi_arsize (crossbar_m01_axi_arsize), + .m01_axi_arburst (crossbar_m01_axi_arburst), + .m01_axi_arlock (crossbar_m01_axi_arlock), + .m01_axi_arcache (crossbar_m01_axi_arcache), + .m01_axi_arprot (crossbar_m01_axi_arprot), + .m01_axi_arqos (crossbar_m01_axi_arqos), + .m01_axi_arregion (crossbar_m01_axi_arregion), + .m01_axi_aruser (crossbar_m01_axi_aruser), + .m01_axi_arvalid (crossbar_m01_axi_arvalid), + .m01_axi_arready (crossbar_m01_axi_arready), + .m01_axi_rid (crossbar_m01_axi_rid), + .m01_axi_rdata (crossbar_m01_axi_rdata), + .m01_axi_rresp (crossbar_m01_axi_rresp), + .m01_axi_rlast (crossbar_m01_axi_rlast), + .m01_axi_ruser (crossbar_m01_axi_ruser), + .m01_axi_rvalid (crossbar_m01_axi_rvalid), + .m01_axi_rready (crossbar_m01_axi_rready), + .m02_axi_awid (crossbar_m02_axi_awid), + .m02_axi_awaddr (crossbar_m02_axi_awaddr), + .m02_axi_awlen (crossbar_m02_axi_awlen), + .m02_axi_awsize (crossbar_m02_axi_awsize), + .m02_axi_awburst (crossbar_m02_axi_awburst), + .m02_axi_awlock (crossbar_m02_axi_awlock), + .m02_axi_awcache (crossbar_m02_axi_awcache), + .m02_axi_awprot (crossbar_m02_axi_awprot), + .m02_axi_awqos (crossbar_m02_axi_awqos), + .m02_axi_awregion (crossbar_m02_axi_awregion), + .m02_axi_awuser (crossbar_m02_axi_awuser), + .m02_axi_awvalid (crossbar_m02_axi_awvalid), + .m02_axi_awready (crossbar_m02_axi_awready), + .m02_axi_wdata (crossbar_m02_axi_wdata), + .m02_axi_wstrb (crossbar_m02_axi_wstrb), + .m02_axi_wlast (crossbar_m02_axi_wlast), + .m02_axi_wuser (crossbar_m02_axi_wuser), + .m02_axi_wvalid (crossbar_m02_axi_wvalid), + .m02_axi_wready (crossbar_m02_axi_wready), + .m02_axi_bid (crossbar_m02_axi_bid), + .m02_axi_bresp (crossbar_m02_axi_bresp), + .m02_axi_buser (crossbar_m02_axi_buser), + .m02_axi_bvalid (crossbar_m02_axi_bvalid), + .m02_axi_bready (crossbar_m02_axi_bready), + .m02_axi_arid (crossbar_m02_axi_arid), + .m02_axi_araddr (crossbar_m02_axi_araddr), + .m02_axi_arlen (crossbar_m02_axi_arlen), + .m02_axi_arsize (crossbar_m02_axi_arsize), + .m02_axi_arburst (crossbar_m02_axi_arburst), + .m02_axi_arlock (crossbar_m02_axi_arlock), + .m02_axi_arcache (crossbar_m02_axi_arcache), + .m02_axi_arprot (crossbar_m02_axi_arprot), + .m02_axi_arqos (crossbar_m02_axi_arqos), + .m02_axi_arregion (crossbar_m02_axi_arregion), + .m02_axi_aruser (crossbar_m02_axi_aruser), + .m02_axi_arvalid (crossbar_m02_axi_arvalid), + .m02_axi_arready (crossbar_m02_axi_arready), + .m02_axi_rid (crossbar_m02_axi_rid), + .m02_axi_rdata (crossbar_m02_axi_rdata), + .m02_axi_rresp (crossbar_m02_axi_rresp), + .m02_axi_rlast (crossbar_m02_axi_rlast), + .m02_axi_ruser (crossbar_m02_axi_ruser), + .m02_axi_rvalid (crossbar_m02_axi_rvalid), + .m02_axi_rready (crossbar_m02_axi_rready) + ); + + axi4_flat_to_if #( + .ADDR_W (ADDR_WIDTH), + .DATA_W (DATA_WIDTH) + ) i_axi4_flat_to_if_00( + .s_axi_awid (crossbar_m00_axi_awid), + .s_axi_awaddr (crossbar_m00_axi_awaddr), + .s_axi_awlen (crossbar_m00_axi_awlen), + .s_axi_awsize (crossbar_m00_axi_awsize), + .s_axi_awburst (crossbar_m00_axi_awburst), + .s_axi_awlock (crossbar_m00_axi_awlock), + .s_axi_awcache (crossbar_m00_axi_awcache), + .s_axi_awprot (crossbar_m00_axi_awprot), + .s_axi_awqos (crossbar_m00_axi_awqos), + .s_axi_awregion (crossbar_m00_axi_awregion), + .s_axi_awuser (crossbar_m00_axi_awuser), + .s_axi_awvalid (crossbar_m00_axi_awvalid), + .s_axi_awready (crossbar_m00_axi_awready), + .s_axi_wdata (crossbar_m00_axi_wdata), + .s_axi_wstrb (crossbar_m00_axi_wstrb), + .s_axi_wlast (crossbar_m00_axi_wlast), + .s_axi_wuser (crossbar_m00_axi_wuser), + .s_axi_wvalid (crossbar_m00_axi_wvalid), + .s_axi_wready (crossbar_m00_axi_wready), + .s_axi_bid (crossbar_m00_axi_bid), + .s_axi_bresp (crossbar_m00_axi_bresp), + .s_axi_buser (crossbar_m00_axi_buser), + .s_axi_bvalid (crossbar_m00_axi_bvalid), + .s_axi_bready (crossbar_m00_axi_bready), + .s_axi_arid (crossbar_m00_axi_arid), + .s_axi_araddr (crossbar_m00_axi_araddr), + .s_axi_arlen (crossbar_m00_axi_arlen), + .s_axi_arsize (crossbar_m00_axi_arsize), + .s_axi_arburst (crossbar_m00_axi_arburst), + .s_axi_arlock (crossbar_m00_axi_arlock), + .s_axi_arcache (crossbar_m00_axi_arcache), + .s_axi_arprot (crossbar_m00_axi_arprot), + .s_axi_arqos (crossbar_m00_axi_arqos), + .s_axi_arregion (crossbar_m00_axi_arregion), + .s_axi_aruser (crossbar_m00_axi_aruser), + .s_axi_arvalid (crossbar_m00_axi_arvalid), + .s_axi_arready (crossbar_m00_axi_arready), + .s_axi_rid (crossbar_m00_axi_rid), + .s_axi_rdata (crossbar_m00_axi_rdata), + .s_axi_rresp (crossbar_m00_axi_rresp), + .s_axi_rlast (crossbar_m00_axi_rlast), + .s_axi_ruser (crossbar_m00_axi_ruser), + .s_axi_rvalid (crossbar_m00_axi_rvalid), + .s_axi_rready (crossbar_m00_axi_rready), + .m_axi (m_axi[0]) + ); + + axi4_flat_to_if #( + .ADDR_W (ADDR_WIDTH), + .DATA_W (DATA_WIDTH) + ) i_axi4_flat_to_if_01( + .s_axi_awid (crossbar_m01_axi_awid), + .s_axi_awaddr (crossbar_m01_axi_awaddr), + .s_axi_awlen (crossbar_m01_axi_awlen), + .s_axi_awsize (crossbar_m01_axi_awsize), + .s_axi_awburst (crossbar_m01_axi_awburst), + .s_axi_awlock (crossbar_m01_axi_awlock), + .s_axi_awcache (crossbar_m01_axi_awcache), + .s_axi_awprot (crossbar_m01_axi_awprot), + .s_axi_awqos (crossbar_m01_axi_awqos), + .s_axi_awregion (crossbar_m01_axi_awregion), + .s_axi_awuser (crossbar_m01_axi_awuser), + .s_axi_awvalid (crossbar_m01_axi_awvalid), + .s_axi_awready (crossbar_m01_axi_awready), + .s_axi_wdata (crossbar_m01_axi_wdata), + .s_axi_wstrb (crossbar_m01_axi_wstrb), + .s_axi_wlast (crossbar_m01_axi_wlast), + .s_axi_wuser (crossbar_m01_axi_wuser), + .s_axi_wvalid (crossbar_m01_axi_wvalid), + .s_axi_wready (crossbar_m01_axi_wready), + .s_axi_bid (crossbar_m01_axi_bid), + .s_axi_bresp (crossbar_m01_axi_bresp), + .s_axi_buser (crossbar_m01_axi_buser), + .s_axi_bvalid (crossbar_m01_axi_bvalid), + .s_axi_bready (crossbar_m01_axi_bready), + .s_axi_arid (crossbar_m01_axi_arid), + .s_axi_araddr (crossbar_m01_axi_araddr), + .s_axi_arlen (crossbar_m01_axi_arlen), + .s_axi_arsize (crossbar_m01_axi_arsize), + .s_axi_arburst (crossbar_m01_axi_arburst), + .s_axi_arlock (crossbar_m01_axi_arlock), + .s_axi_arcache (crossbar_m01_axi_arcache), + .s_axi_arprot (crossbar_m01_axi_arprot), + .s_axi_arqos (crossbar_m01_axi_arqos), + .s_axi_arregion (crossbar_m01_axi_arregion), + .s_axi_aruser (crossbar_m01_axi_aruser), + .s_axi_arvalid (crossbar_m01_axi_arvalid), + .s_axi_arready (crossbar_m01_axi_arready), + .s_axi_rid (crossbar_m01_axi_rid), + .s_axi_rdata (crossbar_m01_axi_rdata), + .s_axi_rresp (crossbar_m01_axi_rresp), + .s_axi_rlast (crossbar_m01_axi_rlast), + .s_axi_ruser (crossbar_m01_axi_ruser), + .s_axi_rvalid (crossbar_m01_axi_rvalid), + .s_axi_rready (crossbar_m01_axi_rready), + .m_axi (m_axi[1]) + ); + + axi4_flat_to_if #( + .ADDR_W (ADDR_WIDTH), + .DATA_W (DATA_WIDTH) + ) i_axi4_flat_to_if_02( + .s_axi_awid (crossbar_m02_axi_awid), + .s_axi_awaddr (crossbar_m02_axi_awaddr), + .s_axi_awlen (crossbar_m02_axi_awlen), + .s_axi_awsize (crossbar_m02_axi_awsize), + .s_axi_awburst (crossbar_m02_axi_awburst), + .s_axi_awlock (crossbar_m02_axi_awlock), + .s_axi_awcache (crossbar_m02_axi_awcache), + .s_axi_awprot (crossbar_m02_axi_awprot), + .s_axi_awqos (crossbar_m02_axi_awqos), + .s_axi_awregion (crossbar_m02_axi_awregion), + .s_axi_awuser (crossbar_m02_axi_awuser), + .s_axi_awvalid (crossbar_m02_axi_awvalid), + .s_axi_awready (crossbar_m02_axi_awready), + .s_axi_wdata (crossbar_m02_axi_wdata), + .s_axi_wstrb (crossbar_m02_axi_wstrb), + .s_axi_wlast (crossbar_m02_axi_wlast), + .s_axi_wuser (crossbar_m02_axi_wuser), + .s_axi_wvalid (crossbar_m02_axi_wvalid), + .s_axi_wready (crossbar_m02_axi_wready), + .s_axi_bid (crossbar_m02_axi_bid), + .s_axi_bresp (crossbar_m02_axi_bresp), + .s_axi_buser (crossbar_m02_axi_buser), + .s_axi_bvalid (crossbar_m02_axi_bvalid), + .s_axi_bready (crossbar_m02_axi_bready), + .s_axi_arid (crossbar_m02_axi_arid), + .s_axi_araddr (crossbar_m02_axi_araddr), + .s_axi_arlen (crossbar_m02_axi_arlen), + .s_axi_arsize (crossbar_m02_axi_arsize), + .s_axi_arburst (crossbar_m02_axi_arburst), + .s_axi_arlock (crossbar_m02_axi_arlock), + .s_axi_arcache (crossbar_m02_axi_arcache), + .s_axi_arprot (crossbar_m02_axi_arprot), + .s_axi_arqos (crossbar_m02_axi_arqos), + .s_axi_arregion (crossbar_m02_axi_arregion), + .s_axi_aruser (crossbar_m02_axi_aruser), + .s_axi_arvalid (crossbar_m02_axi_arvalid), + .s_axi_arready (crossbar_m02_axi_arready), + .s_axi_rid (crossbar_m02_axi_rid), + .s_axi_rdata (crossbar_m02_axi_rdata), + .s_axi_rresp (crossbar_m02_axi_rresp), + .s_axi_rlast (crossbar_m02_axi_rlast), + .s_axi_ruser (crossbar_m02_axi_ruser), + .s_axi_rvalid (crossbar_m02_axi_rvalid), + .s_axi_rready (crossbar_m02_axi_rready), + .m_axi (m_axi[2]) + ); + + +endmodule diff --git a/axi/axi_dma_wrapper.sv b/axi/axi_dma_wrapper.sv new file mode 100644 index 0000000..29fb143 --- /dev/null +++ b/axi/axi_dma_wrapper.sv @@ -0,0 +1,309 @@ +module axi_dma_wrapper #( + parameter AXI_DATA_WIDTH = 32, + parameter AXI_ADDR_WIDTH = 16, + parameter AXI_ID_WIDTH = 8, + parameter AXI_MAX_BURST_LEN = 16, + parameter AXIS_LAST_ENABLE = 1, + parameter AXIS_ID_ENABLE = 0, + parameter AXIS_ID_WIDTH = 8, + parameter AXIS_DEST_ENABLE = 0, + parameter AXIS_DEST_WIDTH = 8, + parameter AXIS_USER_ENABLE = 1, + parameter AXIS_USER_WIDTH = 1, + parameter LEN_WIDTH = 20, + parameter TAG_WIDTH = 8, + parameter ENABLE_SG = 0, + parameter ENABLE_UNALIGNED = 0 +)( + input wire crossbar_clk, + input wire crossbar_rst, + + input wire dma_clk, + input wire dma_rst, + + axi4l_if.slave s_axil_control, + axi4_if.master m_axi_data, + + output wire [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata, + output wire [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep, + output wire m_axis_read_data_tvalid, + input wire m_axis_read_data_tready, + output wire m_axis_read_data_tlast, + output wire [AXIS_ID_WIDTH-1:0] m_axis_read_data_tid, + output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest, + output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser, + + input wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata, + input wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep, + input wire s_axis_write_data_tvalid, + output wire s_axis_write_data_tready, + input wire s_axis_write_data_tlast, + input wire [AXIS_ID_WIDTH-1:0] s_axis_write_data_tid, + input wire [AXIS_DEST_WIDTH-1:0] s_axis_write_data_tdest, + input wire [AXIS_USER_WIDTH-1:0] s_axis_write_data_tuser +); + + wire [AXI_ADDR_WIDTH-1:0] dma_s_axis_read_desc_addr; + wire [LEN_WIDTH-1:0] dma_s_axis_read_desc_len; + wire [TAG_WIDTH-1:0] dma_s_axis_read_desc_tag; + wire [AXIS_ID_WIDTH-1:0] dma_s_axis_read_desc_id; + wire [AXIS_DEST_WIDTH-1:0] dma_s_axis_read_desc_dest; + wire [AXIS_USER_WIDTH-1:0] dma_s_axis_read_desc_user; + wire dma_s_axis_read_desc_valid; + wire dma_s_axis_read_desc_ready; + + wire [TAG_WIDTH-1:0] dma_m_axis_read_desc_status_tag; + wire [3:0] dma_m_axis_read_desc_status_error; + wire dma_m_axis_read_desc_status_valid; + + wire [AXI_ID_WIDTH-1:0] dma_m_axi_awid; + wire [AXI_ADDR_WIDTH-1:0] dma_m_axi_awaddr; + wire [7:0] dma_m_axi_awlen; + wire [2:0] dma_m_axi_awsize; + wire [1:0] dma_m_axi_awburst; + wire dma_m_axi_awlock; + wire [3:0] dma_m_axi_awcache; + wire [2:0] dma_m_axi_awprot; + wire dma_m_axi_awvalid; + wire dma_m_axi_awready; + wire [AXI_DATA_WIDTH-1:0] dma_m_axi_wdata; + wire [AXI_STRB_WIDTH-1:0] dma_m_axi_wstrb; + wire dma_m_axi_wlast; + wire dma_m_axi_wvalid; + wire dma_m_axi_wready; + wire [AXI_ID_WIDTH-1:0] dma_m_axi_bid; + wire [1:0] dma_m_axi_bresp; + wire dma_m_axi_bvalid; + wire dma_m_axi_bready; + wire [AXI_ID_WIDTH-1:0] dma_m_axi_arid; + wire [AXI_ADDR_WIDTH-1:0] dma_m_axi_araddr; + wire [7:0] dma_m_axi_arlen; + wire [2:0] dma_m_axi_arsize; + wire [1:0] dma_m_axi_arburst; + wire dma_m_axi_arlock; + wire [3:0] dma_m_axi_arcache; + wire [2:0] dma_m_axi_arprot; + wire dma_m_axi_arvalid; + wire dma_m_axi_arready; + wire [AXI_ID_WIDTH-1:0] dma_m_axi_rid; + wire [AXI_DATA_WIDTH-1:0] dma_m_axi_rdata; + wire [1:0] dma_m_axi_rresp; + wire dma_m_axi_rlast; + wire dma_m_axi_rvalid; + wire dma_m_axi_rready; + + wire [AXI_ADDR_WIDTH-1:0] dma_s_axis_write_desc_addr; + wire [LEN_WIDTH-1:0] dma_s_axis_write_desc_len; + wire [TAG_WIDTH-1:0] dma_s_axis_write_desc_tag; + wire dma_s_axis_write_desc_valid; + wire dma_s_axis_write_desc_ready; + + wire [LEN_WIDTH-1:0] dma_m_axis_write_desc_status_len; + wire [TAG_WIDTH-1:0] dma_m_axis_write_desc_status_tag; + wire [AXIS_ID_WIDTH-1:0] dma_m_axis_write_desc_status_id; + wire [AXIS_DEST_WIDTH-1:0] dma_m_axis_write_desc_status_dest; + wire [AXIS_USER_WIDTH-1:0] dma_m_axis_write_desc_status_user; + wire [3:0] dma_m_axis_write_desc_status_error; + wire dma_m_axis_write_desc_status_valid; + + wire dma_read_enable; + wire dma_write_enable; + wire dma_write_abort; + + + axi4l_if #(.ADDR_W(AXI_ADDR_WIDTH), .DATA_W(AXI_DATA_WIDTH)) axi4_if_cdc (); + + axil_cdc_wrapper #( + .ADDR_WIDTH (AXI_ADDR_WIDTH), + .DATA_WIDTH (AXI_DATA_WIDTH) + ) i_dma_ctrl_cdc ( + .s_clk (crossbar_clk), + .s_rst (crossbar_rst), + .s_axi (s_axil_control), + + .m_clk (dma_clk), + .m_rst (dma_rst), + .m_axi (axi4_if_cdc) + ); + + wire [N_REGS-1:0][31:0] reg_i; + wire [N_REGS-1:0][31:0] reg_o; + + import dma_axil_reg_map_pkg::*; + axi4l_reg_map #( + .ADDR_W (AXI_ADDR_WIDTH), + .DATA_W (AXI_DATA_WIDTH), + .USER_W (0), + .N_REGS (DMA_AXIL_REG_MAP_N_REGS), + .REG_MODE (DMA_AXIL_REG_MAP_REG_MODE), + .REG_RST (DMA_AXIL_REG_MAP_REG_RST) + ) i_axi4l_dma_reg_map ( + .clk (dma_clk), + .rst_n (!dma_rst), + .s_axil (axi4_if_cdc), + .reg_i (reg_i), + .reg_o (reg_o) + ); + + always_comb begin + dma_s_axis_write_desc_valid = reg_o[DMA_WRITE_DESC_CONTROL_REG][0]; + dma_s_axis_write_desc_addr = reg_o[DMA_WRITE_DESC_ADDR_REG][31:0]; + dma_s_axis_write_desc_len = reg_o[DMA_WRITE_DESC_LEN_REG][31:0]; + reg_i[DMA_WRITE_DESC_CONTROL_REG][1] = dma_s_axis_write_desc_ready; + + dma_s_axis_read_desc_valid = reg_o[DMA_READ_DESC_CONTROL_REG][0]; + dma_s_axis_read_desc_addr = reg_o[DMA_READ_DESC_ADDR_REG][31:0]; + dma_s_axis_read_desc_len = reg_o[DMA_READ_DESC_LEN_REG][31:0]; + reg_i[DMA_READ_DESC_CONTROL_REG][1] = dma_s_axis_read_desc_ready; + end + + axi4_flat_to_if #( + .ADDR_W (AXI_ADDR_WIDTH), + .DATA_W (AXI_DATA_WIDTH) + ) i_axi4_flat_to_if ( + .s_axi_awid (dma_m_axi_awid), + .s_axi_awaddr (dma_m_axi_awaddr), + .s_axi_awlen (dma_m_axi_awlen), + .s_axi_awsize (dma_m_axi_awsize), + .s_axi_awburst (dma_m_axi_awburst), + .s_axi_awlock (dma_m_axi_awlock), + .s_axi_awcache (dma_m_axi_awcache), + .s_axi_awprot (dma_m_axi_awprot), + .s_axi_awqos (dma_m_axi_awqos), + .s_axi_awregion (dma_m_axi_awregion), + .s_axi_awuser (dma_m_axi_awuser), + .s_axi_awvalid (dma_m_axi_awvalid), + .s_axi_awready (dma_m_axi_awready), + .s_axi_wdata (dma_m_axi_wdata), + .s_axi_wstrb (dma_m_axi_wstrb), + .s_axi_wlast (dma_m_axi_wlast), + .s_axi_wuser (dma_m_axi_wuser), + .s_axi_wvalid (dma_m_axi_wvalid), + .s_axi_wready (dma_m_axi_wready), + .s_axi_bid (dma_m_axi_bid), + .s_axi_bresp (dma_m_axi_bresp), + .s_axi_buser (dma_m_axi_buser), + .s_axi_bvalid (dma_m_axi_bvalid), + .s_axi_bready (dma_m_axi_bready), + .s_axi_arid (dma_m_axi_arid), + .s_axi_araddr (dma_m_axi_araddr), + .s_axi_arlen (dma_m_axi_arlen), + .s_axi_arsize (dma_m_axi_arsize), + .s_axi_arburst (dma_m_axi_arburst), + .s_axi_arlock (dma_m_axi_arlock), + .s_axi_arcache (dma_m_axi_arcache), + .s_axi_arprot (dma_m_axi_arprot), + .s_axi_arqos (dma_m_axi_arqos), + .s_axi_arregion (dma_m_axi_arregion), + .s_axi_aruser (dma_m_axi_aruser), + .s_axi_arvalid (dma_m_axi_arvalid), + .s_axi_arready (dma_m_axi_arready), + .s_axi_rid (dma_m_axi_rid), + .s_axi_rdata (dma_m_axi_rdata), + .s_axi_rresp (dma_m_axi_rresp), + .s_axi_rlast (dma_m_axi_rlast), + .s_axi_ruser (dma_m_axi_ruser), + .s_axi_rvalid (dma_m_axi_rvalid), + .s_axi_rready (dma_m_axi_rready), + .m_axi (m_axi_data) + ); + + axi_dma #( + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH), + .AXI_ID_WIDTH (AXI_ID_WIDTH), + .AXI_MAX_BURST_LEN (AXI_MAX_BURST_LEN), + .AXIS_LAST_ENABLE (AXIS_LAST_ENABLE), + .AXIS_ID_ENABLE (AXIS_ID_ENABLE), + .AXIS_ID_WIDTH (AXIS_ID_WIDTH), + .AXIS_DEST_ENABLE (AXIS_DEST_ENABLE), + .AXIS_DEST_WIDTH (AXIS_DEST_WIDTH), + .AXIS_USER_ENABLE (AXIS_USER_ENABLE), + .AXIS_USER_WIDTH (AXIS_USER_WIDTH), + .LEN_WIDTH (LEN_WIDTH), + .TAG_WIDTH (TAG_WIDTH), + .ENABLE_SG (ENABLE_SG), + .ENABLE_UNALIGNED (ENABLE_UNALIGNED) + ) i_axi_dma ( + .clk (dma_clk), + .rst (dma_rst), + .s_axis_read_desc_addr (dma_s_axis_read_desc_addr), + .s_axis_read_desc_len (dma_s_axis_read_desc_len), + .s_axis_read_desc_tag (dma_s_axis_read_desc_tag), + .s_axis_read_desc_id (dma_s_axis_read_desc_id), + .s_axis_read_desc_dest (dma_s_axis_read_desc_dest), + .s_axis_read_desc_user (dma_s_axis_read_desc_user), + .s_axis_read_desc_valid (dma_s_axis_read_desc_valid), + .s_axis_read_desc_ready (dma_s_axis_read_desc_ready), + .m_axis_read_desc_status_tag (dma_m_axis_read_desc_status_tag), + .m_axis_read_desc_status_error (dma_m_axis_read_desc_status_error), + .m_axis_read_desc_status_valid (dma_m_axis_read_desc_status_valid), + .m_axis_read_data_tdata (m_axis_read_data_tdata), + .m_axis_read_data_tkeep (m_axis_read_data_tkeep), + .m_axis_read_data_tvalid (m_axis_read_data_tvalid), + .m_axis_read_data_tready (m_axis_read_data_tready), + .m_axis_read_data_tlast (m_axis_read_data_tlast), + .m_axis_read_data_tid (m_axis_read_data_tid), + .m_axis_read_data_tdest (m_axis_read_data_tdest), + .m_axis_read_data_tuser (m_axis_read_data_tuser), + .s_axis_write_desc_addr (dma_s_axis_write_desc_addr), + .s_axis_write_desc_len (dma_s_axis_write_desc_len), + .s_axis_write_desc_tag (dma_s_axis_write_desc_tag), + .s_axis_write_desc_valid (dma_s_axis_write_desc_valid), + .s_axis_write_desc_ready (dma_s_axis_write_desc_ready), + .m_axis_write_desc_status_len (dma_m_axis_write_desc_status_len), + .m_axis_write_desc_status_tag (dma_m_axis_write_desc_status_tag), + .m_axis_write_desc_status_id (dma_m_axis_write_desc_status_id), + .m_axis_write_desc_status_dest (dma_m_axis_write_desc_status_dest), + .m_axis_write_desc_status_user (dma_m_axis_write_desc_status_user), + .m_axis_write_desc_status_error (dma_m_axis_write_desc_status_error), + .m_axis_write_desc_status_valid (dma_m_axis_write_desc_status_valid), + .s_axis_write_data_tdata (s_axis_write_data_tdata), + .s_axis_write_data_tkeep (s_axis_write_data_tkeep), + .s_axis_write_data_tvalid (s_axis_write_data_tvalid), + .s_axis_write_data_tready (s_axis_write_data_tready), + .s_axis_write_data_tlast (s_axis_write_data_tlast), + .s_axis_write_data_tid (s_axis_write_data_tid), + .s_axis_write_data_tdest (s_axis_write_data_tdest), + .s_axis_write_data_tuser (s_axis_write_data_tuser), + .m_axi_awid (dma_m_axi_awid), + .m_axi_awaddr (dma_m_axi_awaddr), + .m_axi_awlen (dma_m_axi_awlen), + .m_axi_awsize (dma_m_axi_awsize), + .m_axi_awburst (dma_m_axi_awburst), + .m_axi_awlock (dma_m_axi_awlock), + .m_axi_awcache (dma_m_axi_awcache), + .m_axi_awprot (dma_m_axi_awprot), + .m_axi_awvalid (dma_m_axi_awvalid), + .m_axi_awready (dma_m_axi_awready), + .m_axi_wdata (dma_m_axi_wdata), + .m_axi_wstrb (dma_m_axi_wstrb), + .m_axi_wlast (dma_m_axi_wlast), + .m_axi_wvalid (dma_m_axi_wvalid), + .m_axi_wready (dma_m_axi_wready), + .m_axi_bid (dma_m_axi_bid), + .m_axi_bresp (dma_m_axi_bresp), + .m_axi_bvalid (dma_m_axi_bvalid), + .m_axi_bready (dma_m_axi_bready), + .m_axi_arid (dma_m_axi_arid), + .m_axi_araddr (dma_m_axi_araddr), + .m_axi_arlen (dma_m_axi_arlen), + .m_axi_arsize (dma_m_axi_arsize), + .m_axi_arburst (dma_m_axi_arburst), + .m_axi_arlock (dma_m_axi_arlock), + .m_axi_arcache (dma_m_axi_arcache), + .m_axi_arprot (dma_m_axi_arprot), + .m_axi_arvalid (dma_m_axi_arvalid), + .m_axi_arready (dma_m_axi_arready), + .m_axi_rid (dma_m_axi_rid), + .m_axi_rdata (dma_m_axi_rdata), + .m_axi_rresp (dma_m_axi_rresp), + .m_axi_rlast (dma_m_axi_rlast), + .m_axi_rvalid (dma_m_axi_rvalid), + .m_axi_rready (dma_m_axi_rready), + .read_enable (dma_read_enable), + .write_enable (dma_write_enable), + .write_abort (dma_write_abort) + ); + +endmodule \ No newline at end of file diff --git a/axi/axi_if.sv b/axi/axi_if.sv new file mode 100644 index 0000000..66af213 --- /dev/null +++ b/axi/axi_if.sv @@ -0,0 +1,43 @@ +interface axi4_if #( + parameter int unsigned ADDR_W = 32, + parameter int unsigned DATA_W = 32, + parameter int unsigned ID_W = 4, + parameter int unsigned USER_W = 1 +)( + input logic aclk, + input logic aresetn +); + import axi_pkg::*; + typedef logic [ADDR_W-1:0] addr_t; + typedef logic [DATA_W-1:0] data_t; + typedef logic [DATA_W/8-1:0] strb_t; + typedef logic [ID_W-1:0] id_t; + typedef logic [USER_W-1:0] user_t; + `AXI4_TYPEDEF_ALL(axi, addr_t, data_t, strb_t, id_t, user_t) + axi_req_t req; + axi_resp_t resp; + modport master (input aclk, aresetn, output req, input resp); + modport slave (input aclk, aresetn, input req, output resp); + modport monitor(input aclk, aresetn, input req, input resp); +endinterface : axi4_if + +interface axi4l_if #( + parameter int unsigned ADDR_W = 32, + parameter int unsigned DATA_W = 32, + parameter int unsigned USER_W = 1 +)( + input logic aclk, + input logic aresetn +); + import axi_pkg::*; + typedef logic [ADDR_W-1:0] addr_t; + typedef logic [DATA_W-1:0] data_t; + typedef logic [DATA_W/8-1:0] strb_t; + typedef logic [USER_W-1:0] user_t; + `AXI4L_TYPEDEF_ALL(axil, addr_t, data_t, strb_t, user_t) + axil_req_t req; + axil_resp_t resp; + modport master (input aclk, aresetn, output req, input resp); + modport slave (input aclk, aresetn, input req, output resp); + modport monitor(input aclk, aresetn, input req, input resp); +endinterface : axi4l_if diff --git a/axi/axi_pkg.sv b/axi/axi_pkg.sv new file mode 100644 index 0000000..d542cde --- /dev/null +++ b/axi/axi_pkg.sv @@ -0,0 +1,140 @@ +package axi_pkg; + + typedef enum logic [1:0] { + AXI_BURST_FIXED = 2'b00, + AXI_BURST_INCR = 2'b01, + AXI_BURST_WRAP = 2'b10 + } axi_burst_t; + + typedef enum logic [1:0] { + AXI_RESP_OKAY = 2'b00, + AXI_RESP_EXOKAY = 2'b01, + AXI_RESP_SLVERR = 2'b10, + AXI_RESP_DECERR = 2'b11 + } axi_resp_t; + + function automatic logic [2:0] axi_size_from_bytes(input int unsigned nbytes); + case (nbytes) + 1 : return 3'd0; + 2 : return 3'd1; + 4 : return 3'd2; + 8 : return 3'd3; + 16 : return 3'd4; + 32 : return 3'd5; + 64 : return 3'd6; + 128 : return 3'd7; + default: return 3'd0; + endcase + endfunction + +endpackage : axi_pkg + +`define AXI4_TYPEDEF_ALL(__name, __addr_t, __data_t, __strb_t, __id_t, __user_t) \ + typedef struct packed { \ + __id_t id; \ + __addr_t addr; \ + logic [7:0] len; \ + logic [2:0] size; \ + axi_pkg::axi_burst_t burst; \ + logic lock; \ + logic [3:0] cache; \ + logic [2:0] prot; \ + logic [3:0] qos; \ + logic [3:0] region; \ + __user_t user; \ + logic valid; \ + } __name``_aw_chan_t; \ + typedef struct packed { \ + __data_t data; \ + __strb_t strb; \ + logic last; \ + __user_t user; \ + logic valid; \ + } __name``_w_chan_t; \ + typedef struct packed { \ + __id_t id; \ + axi_pkg::axi_resp_t resp; \ + __user_t user; \ + logic valid; \ + } __name``_b_chan_t; \ + typedef struct packed { \ + __id_t id; \ + __addr_t addr; \ + logic [7:0] len; \ + logic [2:0] size; \ + axi_pkg::axi_burst_t burst; \ + logic lock; \ + logic [3:0] cache; \ + logic [2:0] prot; \ + logic [3:0] qos; \ + logic [3:0] region; \ + __user_t user; \ + logic valid; \ + } __name``_ar_chan_t; \ + typedef struct packed { \ + __id_t id; \ + __data_t data; \ + axi_pkg::axi_resp_t resp; \ + logic last; \ + __user_t user; \ + logic valid; \ + } __name``_r_chan_t; \ + typedef struct packed { \ + __name``_aw_chan_t aw; \ + __name``_w_chan_t w; \ + logic b_ready; \ + __name``_ar_chan_t ar; \ + logic r_ready; \ + } __name``_req_t; \ + typedef struct packed { \ + logic aw_ready; \ + logic w_ready; \ + __name``_b_chan_t b; \ + logic ar_ready; \ + __name``_r_chan_t r; \ + } __name``_resp_t + +`define AXI4L_TYPEDEF_ALL(__name, __addr_t, __data_t, __strb_t, __user_t) \ + typedef struct packed { \ + __addr_t addr; \ + logic [2:0] prot; \ + __user_t user; \ + logic valid; \ + } __name``_aw_chan_t; \ + typedef struct packed { \ + __data_t data; \ + __strb_t strb; \ + __user_t user; \ + logic valid; \ + } __name``_w_chan_t; \ + typedef struct packed { \ + axi_pkg::axi_resp_t resp; \ + __user_t user; \ + logic valid; \ + } __name``_b_chan_t; \ + typedef struct packed { \ + __addr_t addr; \ + logic [2:0] prot; \ + __user_t user; \ + logic valid; \ + } __name``_ar_chan_t; \ + typedef struct packed { \ + __data_t data; \ + axi_pkg::axi_resp_t resp; \ + __user_t user; \ + logic valid; \ + } __name``_r_chan_t; \ + typedef struct packed { \ + __name``_aw_chan_t aw; \ + __name``_w_chan_t w; \ + logic b_ready; \ + __name``_ar_chan_t ar; \ + logic r_ready; \ + } __name``_req_t; \ + typedef struct packed { \ + logic aw_ready; \ + logic w_ready; \ + __name``_b_chan_t b; \ + logic ar_ready; \ + __name``_r_chan_t r; \ + } __name``_resp_t diff --git a/axi/axi_ram_wrapper.sv b/axi/axi_ram_wrapper.sv new file mode 100644 index 0000000..8e5e459 --- /dev/null +++ b/axi/axi_ram_wrapper.sv @@ -0,0 +1,146 @@ +module axi_ram_wrapper #( + parameter DATA_WIDTH = 32, + parameter ADDR_WIDTH = 16, + parameter ID_WIDTH = 8, + parameter PIPELINE_OUTPUT = 0 +)( + input wire clk, + input wire rst, + + axi4_if.slaver s_axi +); + + wire [ID_WIDTH-1:0] ram_s_axi_awid; + wire [ADDR_WIDTH-1:0] ram_s_axi_awaddr; + wire [7:0] ram_s_axi_awlen; + wire [2:0] ram_s_axi_awsize; + wire [1:0] ram_s_axi_awburst; + wire ram_s_axi_awlock; + wire [3:0] ram_s_axi_awcache; + wire [2:0] ram_s_axi_awprot; + wire ram_s_axi_awvalid; + wire ram_s_axi_awready; + wire [DATA_WIDTH-1:0] ram_s_axi_wdata; + wire [STRB_WIDTH-1:0] ram_s_axi_wstrb; + wire ram_s_axi_wlast; + wire ram_s_axi_wvalid; + wire ram_s_axi_wready; + wire [ID_WIDTH-1:0] ram_s_axi_bid; + wire [1:0] ram_s_axi_bresp; + wire ram_s_axi_bvalid; + wire ram_s_axi_bready; + wire [ID_WIDTH-1:0] ram_s_axi_arid; + wire [ADDR_WIDTH-1:0] ram_s_axi_araddr; + wire [7:0] ram_s_axi_arlen; + wire [2:0] ram_s_axi_arsize; + wire [1:0] ram_s_axi_arburst; + wire ram_s_axi_arlock; + wire [3:0] ram_s_axi_arcache; + wire [2:0] ram_s_axi_arprot; + wire ram_s_axi_arvalid; + wire ram_s_axi_arready; + wire [ID_WIDTH-1:0] ram_s_axi_rid; + wire [DATA_WIDTH-1:0] ram_s_axi_rdata; + wire [1:0] ram_s_axi_rresp; + wire ram_s_axi_rlast; + wire ram_s_axi_rvalid; + wire ram_s_axi_rready; + + axi4_if_to_flat #( + .ADDR_W (ADDR_WIDTH), + .DATA_W (DATA_WIDTH) + ) i_axi4_if_to_flat ( + .s_axi (s_axi), + .m_axi_awid (ram_s_axi_awid), + .m_axi_awaddr (ram_s_axi_awaddr), + .m_axi_awlen (ram_s_axi_awlen), + .m_axi_awsize (ram_s_axi_awsize), + .m_axi_awburst (ram_s_axi_awburst), + .m_axi_awlock (ram_s_axi_awlock), + .m_axi_awcache (ram_s_axi_awcache), + .m_axi_awprot (ram_s_axi_awprot), + .m_axi_awqos (ram_s_axi_awqos), + .m_axi_awregion (ram_s_axi_awregion), + .m_axi_awuser (ram_s_axi_awuser), + .m_axi_awvalid (ram_s_axi_awvalid), + .m_axi_awready (ram_s_axi_awready), + .m_axi_wdata (ram_s_axi_wdata), + .m_axi_wstrb (ram_s_axi_wstrb), + .m_axi_wlast (ram_s_axi_wlast), + .m_axi_wuser (ram_s_axi_wuser), + .m_axi_wvalid (ram_s_axi_wvalid), + .m_axi_wready (ram_s_axi_wready), + .m_axi_bid (ram_s_axi_bid), + .m_axi_bresp (ram_s_axi_bresp), + .m_axi_buser (ram_s_axi_buser), + .m_axi_bvalid (ram_s_axi_bvalid), + .m_axi_bready (ram_s_axi_bready), + .m_axi_arid (ram_s_axi_arid), + .m_axi_araddr (ram_s_axi_araddr), + .m_axi_arlen (ram_s_axi_arlen), + .m_axi_arsize (ram_s_axi_arsize), + .m_axi_arburst (ram_s_axi_arburst), + .m_axi_arlock (ram_s_axi_arlock), + .m_axi_arcache (ram_s_axi_arcache), + .m_axi_arprot (ram_s_axi_arprot), + .m_axi_arqos (ram_s_axi_arqos), + .m_axi_arregion (ram_s_axi_arregion), + .m_axi_aruser (ram_s_axi_aruser), + .m_axi_arvalid (ram_s_axi_arvalid), + .m_axi_arready (ram_s_axi_arready), + .m_axi_rid (ram_s_axi_rid), + .m_axi_rdata (ram_s_axi_rdata), + .m_axi_rresp (ram_s_axi_rresp), + .m_axi_rlast (ram_s_axi_rlast), + .m_axi_ruser (ram_s_axi_ruser), + .m_axi_rvalid (ram_s_axi_rvalid), + .m_axi_rready (ram_s_axi_rready) + ); + + axi_ram # + ( + .DATA_WIDTH (DATA_WIDTH), + .ADDR_WIDTH (ADDR_WIDTH), + .ID_WIDTH (ID_WIDTH), + .PIPELINE_OUTPUT (PIPELINE_OUTPUT) + ) i_axi_ram ( + .clk (clk), + .rst (rst), + .s_axi_awid (ram_s_axi_awid), + .s_axi_awaddr (ram_s_axi_awaddr), + .s_axi_awlen (ram_s_axi_awlen), + .s_axi_awsize (ram_s_axi_awsize), + .s_axi_awburst (ram_s_axi_awburst), + .s_axi_awlock (ram_s_axi_awlock), + .s_axi_awcache (ram_s_axi_awcache), + .s_axi_awprot (ram_s_axi_awprot), + .s_axi_awvalid (ram_s_axi_awvalid), + .s_axi_awready (ram_s_axi_awready), + .s_axi_wdata (ram_s_axi_wdata), + .s_axi_wstrb (ram_s_axi_wstrb), + .s_axi_wlast (ram_s_axi_wlast), + .s_axi_wvalid (ram_s_axi_wvalid), + .s_axi_wready (ram_s_axi_wready), + .s_axi_bid (ram_s_axi_bid), + .s_axi_bresp (ram_s_axi_bresp), + .s_axi_bvalid (ram_s_axi_bvalid), + .s_axi_bready (ram_s_axi_bready), + .s_axi_arid (ram_s_axi_arid), + .s_axi_araddr (ram_s_axi_araddr), + .s_axi_arlen (ram_s_axi_arlen), + .s_axi_arsize (ram_s_axi_arsize), + .s_axi_arburst (ram_s_axi_arburst), + .s_axi_arlock (ram_s_axi_arlock), + .s_axi_arcache (ram_s_axi_arcache), + .s_axi_arprot (ram_s_axi_arprot), + .s_axi_arvalid (ram_s_axi_arvalid), + .s_axi_arready (ram_s_axi_arready), + .s_axi_rid (ram_s_axi_rid), + .s_axi_rdata (ram_s_axi_rdata), + .s_axi_rresp (ram_s_axi_rresp), + .s_axi_rlast (ram_s_axi_rlast), + .s_axi_rvalid (ram_s_axi_rvalid), + .s_axi_rready (ram_s_axi_rready) + ); + +endmodule \ No newline at end of file diff --git a/axi/axi_reg/axi4l_reg_map.sv b/axi/axi_reg/axi4l_reg_map.sv new file mode 100644 index 0000000..36544a8 --- /dev/null +++ b/axi/axi_reg/axi4l_reg_map.sv @@ -0,0 +1,189 @@ +module axi4l_reg_map #( + parameter int unsigned ADDR_W = 16, + parameter int unsigned DATA_W = 32, + parameter int unsigned USER_W = 1, + parameter int unsigned N_REGS = 4, + + parameter logic [N_REGS-1:0][31:0][2:0] REG_MODE = '{default:'0}, + parameter logic [N_REGS-1:0][31:0] REG_RST = '{default:'0} +)( + input logic clk, + input logic rst_n, + axi4l_if.slave s_axil, + + input logic [N_REGS-1:0][31:0] reg_i, + output logic [N_REGS-1:0][31:0] reg_o +); + import axi_pkg::*; + + typedef enum logic [2:0] { + REG_BIT_RSVD = 3'd0, + REG_BIT_RO = 3'd1, + REG_BIT_RW = 3'd2, + REG_BIT_W1S = 3'd3, + REG_BIT_W1C = 3'd4 + } reg_bit_mode_t; + + localparam int unsigned STRB_W = DATA_W/8; + localparam int unsigned ADDR_LSB = $clog2(DATA_W/8); + localparam int unsigned REG_INDEX_W = (N_REGS <= 1) ? 1 : $clog2(N_REGS); + + logic [ADDR_W-1:0] awaddr_q; + logic aw_seen_q; + logic [DATA_W-1:0] wdata_q; + logic [STRB_W-1:0] wstrb_q; + logic w_seen_q; + + logic bvalid_q; + logic [1:0] bresp_q; + + logic rvalid_q; + logic [1:0] rresp_q; + logic [DATA_W-1:0] rdata_q; + + logic [REG_INDEX_W-1:0] wr_idx; + logic [REG_INDEX_W-1:0] rd_idx; + logic wr_addr_valid; + logic rd_addr_valid; + + integer b; + logic [31:0] wr_mask; + logic [31:0] wr_data32; + logic [31:0] rw_cur; + logic [31:0] rw_new; + logic [31:0] rd_word; + + always_comb begin + wr_idx = '0; + rd_idx = '0; + wr_addr_valid = 1'b0; + rd_addr_valid = 1'b0; + + if (awaddr_q[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W] < N_REGS) begin + wr_idx = awaddr_q[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W]; + wr_addr_valid = 1'b1; + end + + if (s_axil.req.ar.addr[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W] < N_REGS) begin + rd_idx = s_axil.req.ar.addr[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W]; + rd_addr_valid = 1'b1; + end + end + + always_comb begin + wr_mask = '0; + for (int k = 0; k < STRB_W; k++) begin + wr_mask[k*8 +: 8] = {8{wstrb_q[k]}}; + end + wr_data32 = wdata_q[31:0]; + end + + assign s_axil.resp.aw_ready = !aw_seen_q && !bvalid_q; + assign s_axil.resp.w_ready = !w_seen_q && !bvalid_q; + assign s_axil.resp.ar_ready = !rvalid_q; + + assign s_axil.resp.b.valid = bvalid_q; + assign s_axil.resp.b.resp = axi_resp_t'(bresp_q); + assign s_axil.resp.b.user = '0; + + assign s_axil.resp.r.valid = rvalid_q; + assign s_axil.resp.r.resp = axi_resp_t'(rresp_q); + assign s_axil.resp.r.data = rdata_q; + assign s_axil.resp.r.user = '0; + + always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + awaddr_q <= '0; + aw_seen_q <= 1'b0; + wdata_q <= '0; + wstrb_q <= '0; + w_seen_q <= 1'b0; + bvalid_q <= 1'b0; + bresp_q <= 2'b00; + rvalid_q <= 1'b0; + rresp_q <= 2'b00; + rdata_q <= '0; + reg_o <= REG_RST; + end else begin + for (int r = 0; r < N_REGS; r++) begin + for (int bit_idx = 0; bit_idx < 32; bit_idx++) begin + if (reg_bit_mode_t'(REG_MODE[r][bit_idx]) == REG_BIT_W1S) + reg_o[r][bit_idx] <= 1'b0; + end + end + + if (s_axil.req.aw.valid && s_axil.resp.aw_ready) begin + awaddr_q <= s_axil.req.aw.addr; + aw_seen_q <= 1'b1; + end + + if (s_axil.req.w.valid && s_axil.resp.w_ready) begin + wdata_q <= s_axil.req.w.data; + wstrb_q <= s_axil.req.w.strb; + w_seen_q <= 1'b1; + end + + if (aw_seen_q && w_seen_q && !bvalid_q) begin + bvalid_q <= 1'b1; + bresp_q <= 2'b00; + + if (!wr_addr_valid) begin + bresp_q <= 2'b10; + end else begin + rw_cur = reg_o[wr_idx]; + rw_new = rw_cur; + + for (b = 0; b < 32; b = b + 1) begin + if (wr_mask[b]) begin + unique case (reg_bit_mode_t'(REG_MODE[wr_idx][b])) + REG_BIT_RSVD: begin end + REG_BIT_RO : begin bresp_q <= 2'b10; end + REG_BIT_RW : rw_new[b] = wr_data32[b]; + REG_BIT_W1S : if (wr_data32[b]) rw_new[b] = 1'b1; + REG_BIT_W1C : if (wr_data32[b]) rw_new[b] = 1'b0; + default : begin end + endcase + end + end + + reg_o[wr_idx] <= rw_new; + end + + aw_seen_q <= 1'b0; + w_seen_q <= 1'b0; + end + + if (bvalid_q && s_axil.req.b_ready) begin + bvalid_q <= 1'b0; + end + + if (s_axil.req.ar.valid && s_axil.resp.ar_ready) begin + rvalid_q <= 1'b1; + rresp_q <= 2'b00; + rd_word = '0; + + if (!rd_addr_valid) begin + rresp_q <= 2'b10; + end else begin + for (b = 0; b < 32; b = b + 1) begin + unique case (reg_bit_mode_t'(REG_MODE[rd_idx][b])) + REG_BIT_RSVD: rd_word[b] = 1'b0; + REG_BIT_RO : rd_word[b] = reg_i[rd_idx][b]; + REG_BIT_RW : rd_word[b] = reg_o[rd_idx][b]; + REG_BIT_W1S : rd_word[b] = 1'b0; + REG_BIT_W1C : rd_word[b] = reg_o[rd_idx][b]; + default : rd_word[b] = 1'b0; + endcase + end + end + + rdata_q <= rd_word; + end + + if (rvalid_q && s_axil.req.r_ready) begin + rvalid_q <= 1'b0; + end + end + end + +endmodule diff --git a/axi/axi_reg/axi4l_reg_map_example.sv b/axi/axi_reg/axi4l_reg_map_example.sv new file mode 100644 index 0000000..b1b6dd3 --- /dev/null +++ b/axi/axi_reg/axi4l_reg_map_example.sv @@ -0,0 +1,60 @@ +module axi4l_reg_map_example #( + parameter int unsigned ADDR_W = 16, + parameter int unsigned DATA_W = 32, + parameter int unsigned USER_W = 1 +)( + input logic clk, + input logic rst_n, + axi4l_if.slave s_axil, + + output logic start_o, + output logic enable_o, + input logic busy_i, + input logic [7:0] error_code_i +); + import axi4l_reg_map_example_pkg::*; + + localparam int unsigned N_REGS = AXI4L_REG_MAP_EXAMPLE_N_REGS; + + logic [N_REGS-1:0][31:0] reg_i; + logic [N_REGS-1:0][31:0] reg_o; + logic [N_REGS-1:0][31:0] reg_pulse; + + axi4l_reg_map #( + .ADDR_W (ADDR_W), + .DATA_W (DATA_W), + .USER_W (USER_W), + .N_REGS (N_REGS), + .REG_MODE(AXI4L_REG_MAP_EXAMPLE_REG_MODE), + .REG_RST (AXI4L_REG_MAP_EXAMPLE_REG_RST) + ) u_reg_map ( + .clk (clk), + .rst_n (rst_n), + .s_axil (s_axil), + .reg_i (reg_i), + .reg_o (reg_o), + .reg_pulse(reg_pulse) + ); + + always_comb begin + reg_i = '0; + + // REG1 @ 0x04: status register + // bit 0 : busy (RO) + reg_i[1][0] = busy_i; + + // REG2 @ 0x08: error register + // bits 7:0: error_code (RO) + reg_i[2][7:0] = error_code_i; + end + + // REG0 @ 0x00: control register + // bit 0 : start (W1S pulse) + // bit 1 : enable (RW) + assign start_o = reg_pulse[0][0]; + assign enable_o = reg_o[0][1]; + + // REG3 @ 0x0C: generic configuration register (RW) + // reg_o[3] can be manually connected later if needed. + +endmodule diff --git a/axi/axi_reg/axi4l_reg_map_example_pkg.sv b/axi/axi_reg/axi4l_reg_map_example_pkg.sv new file mode 100644 index 0000000..9f9816f --- /dev/null +++ b/axi/axi_reg/axi4l_reg_map_example_pkg.sv @@ -0,0 +1,35 @@ +package axi4l_reg_map_example_pkg; + + localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 4; + + localparam logic [2:0] REG_BIT_RSVD = 3'd0; + localparam logic [2:0] REG_BIT_RO = 3'd1; + localparam logic [2:0] REG_BIT_RW = 3'd2; + localparam logic [2:0] REG_BIT_W1S = 3'd3; + + localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0][2:0] AXI4L_REG_MAP_EXAMPLE_REG_MODE = '{ + '{ + REG_BIT_W1S, + REG_BIT_RW, + default: REG_BIT_RSVD + }, + '{ + REG_BIT_RO, + default: REG_BIT_RSVD + }, + '{ + REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, + REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, + default: REG_BIT_RSVD + }, + '{default: REG_BIT_RW} + }; + + localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0] AXI4L_REG_MAP_EXAMPLE_REG_RST = '{ + 32'h0000_0000, + 32'h0000_0000, + 32'h0000_0000, + 32'h0000_0001 + }; + +endpackage diff --git a/axi/axi_reg/dma_axil_reg_map_pkg.sv b/axi/axi_reg/dma_axil_reg_map_pkg.sv new file mode 100644 index 0000000..554d74d --- /dev/null +++ b/axi/axi_reg/dma_axil_reg_map_pkg.sv @@ -0,0 +1,37 @@ +package dma_axil_reg_map_pkg; + + localparam int unsigned DMA_AXIL_REG_MAP_N_REGS = 4; + + localparam logic [2:0] REG_BIT_RSVD = 3'd0; + localparam logic [2:0] REG_BIT_RO = 3'd1; + localparam logic [2:0] REG_BIT_RW = 3'd2; + localparam logic [2:0] REG_BIT_W1S = 3'd3; + localparam logic [2:0] REG_BIT_W1C = 3'd4; + + localparam DMA_WRITE_DESC_CONTROL_REG = 0; + localparam DMA_WRITE_DESC_ADDR_REG = 1; + localparam DMA_WRITE_DESC_LEN_REG = 2; + localparam DMA_READ_DESC_CONTROL_REG = 3; + localparam DMA_READ_DESC_ADDR_REG = 4; + localparam DMA_READ_DESC_LEN_REG = 5; + + localparam logic [DMA_AXIL_REG_MAP_N_REGS-1:0][31:0][2:0] DMA_AXIL_REG_MAP_REG_MODE = '{ + + '{REG_BIT_RO, REG_BIT_W1S, default: REG_BIT_RSVD}, + '{32{REG_BIT_RW}, default: REG_BIT_RSVD}, + '{32{REG_BIT_RW}, default: REG_BIT_RSVD}, + '{REG_BIT_RO, REG_BIT_W1S, default: REG_BIT_RSVD}, + '{32{REG_BIT_RW}, default: REG_BIT_RSVD}, + '{32{REG_BIT_RW}, default: REG_BIT_RSVD} + }; + + localparam logic [DMA_AXIL_REG_MAP_N_REGS-1:0][31:0] DMA_AXIL_REG_MAP_REG_RST = '{ + 32'h0000_0000, + 32'h0000_0000, + 32'h0000_0000, + 32'h0000_0000, + 32'h0000_0000, + 32'h0000_0000 + }; + +endpackage \ No newline at end of file diff --git a/axi/axil_cdc_wrapper.sv b/axi/axil_cdc_wrapper.sv new file mode 100644 index 0000000..09a547c --- /dev/null +++ b/axi/axil_cdc_wrapper.sv @@ -0,0 +1,165 @@ +module axil_cdc_wrapper #( + parameter int ADDR_WIDTH = 32 + parameter int DATA_WIDTH = 32, +)( + input wire s_clk, + input wire s_rst, + axi4l_if.slave s_axi, + + input wire m_clk, + input wire m_rst, + axi4l_if.master m_axi +); + + localparam int STRB_WIDTH = (DATA_WIDTH/8); + wire [ADDR_WIDTH-1:0] cdc_s_axil_awaddr; + wire [2:0] cdc_s_axil_awprot; + wire cdc_s_axil_awvalid; + wire cdc_s_axil_awready; + wire [DATA_WIDTH-1:0] cdc_s_axil_wdata; + wire [STRB_WIDTH-1:0] cdc_s_axil_wstrb; + wire cdc_s_axil_wvalid; + wire cdc_s_axil_wready; + wire [1:0] cdc_s_axil_bresp; + wire cdc_s_axil_bvalid; + wire cdc_s_axil_bready; + wire [ADDR_WIDTH-1:0] cdc_s_axil_araddr; + wire [2:0] cdc_s_axil_arprot; + wire cdc_s_axil_arvalid; + wire cdc_s_axil_arready; + wire [DATA_WIDTH-1:0] cdc_s_axil_rdata; + wire [1:0] cdc_s_axil_rresp; + wire cdc_s_axil_rvalid; + wire cdc_s_axil_rready; + wire [ADDR_WIDTH-1:0] cdc_m_axil_awaddr; + wire [2:0] cdc_m_axil_awprot; + wire cdc_m_axil_awvalid; + wire cdc_m_axil_awready; + wire [DATA_WIDTH-1:0] cdc_m_axil_wdata; + wire [STRB_WIDTH-1:0] cdc_m_axil_wstrb; + wire cdc_m_axil_wvalid; + wire cdc_m_axil_wready; + wire [1:0] cdc_m_axil_bresp; + wire cdc_m_axil_bvalid; + wire cdc_m_axil_bready; + wire [ADDR_WIDTH-1:0] cdc_m_axil_araddr; + wire [2:0] cdc_m_axil_arprot; + wire cdc_m_axil_arvalid; + wire cdc_m_axil_arready; + wire [DATA_WIDTH-1:0] cdc_m_axil_rdata; + wire [1:0] cdc_m_axil_rresp; + wire cdc_m_axil_rvalid; + wire cdc_m_axil_rready; + + axi4l_if_to_flat #( + .ADDR_W (ADDR_WIDTH), + .DATA_W (DATA_WIDTH) + ) i_axi4l_if_to_flat ( + .s_axil (s_axi), + .m_axil_awaddr (cdc_m_axil_awaddr), + .m_axil_awprot (cdc_m_axil_awprot), + .m_axil_awuser (cdc_m_axil_awuser), + .m_axil_awvalid (cdc_m_axil_awvalid), + .m_axil_awready (cdc_m_axil_awready), + .m_axil_wdata (cdc_m_axil_wdata), + .m_axil_wstrb (cdc_m_axil_wstrb), + .m_axil_wuser (cdc_m_axil_wuser), + .m_axil_wvalid (cdc_m_axil_wvalid), + .m_axil_wready (cdc_m_axil_wready), + .m_axil_bresp (cdc_m_axil_bresp), + .m_axil_buser (cdc_m_axil_buser), + .m_axil_bvalid (cdc_m_axil_bvalid), + .m_axil_bready (cdc_m_axil_bready), + .m_axil_araddr (cdc_m_axil_araddr), + .m_axil_arprot (cdc_m_axil_arprot), + .m_axil_aruser (cdc_m_axil_aruser), + .m_axil_arvalid (cdc_m_axil_arvalid), + .m_axil_arready (cdc_m_axil_arready), + .m_axil_rdata (cdc_m_axil_rdata), + .m_axil_rresp (cdc_m_axil_rresp), + .m_axil_ruser (cdc_m_axil_ruser), + .m_axil_rvalid (cdc_m_axil_rvalid), + .m_axil_rready (cdc_m_axil_rready) + ); + + axil_cdc #( + .ADDR_WIDTH (ADDR_WIDTH) + .DATA_WIDTH (DATA_WIDTH), + ) i_axil_cdc ( + .s_clk (s_clk), + .s_rst (s_rst), + .s_axil_awaddr (cdc_m_axil_awaddr), + .s_axil_awprot (cdc_m_axil_awprot), + .s_axil_awvalid (cdc_m_axil_awvalid), + .s_axil_awready (cdc_m_axil_awready), + .s_axil_wdata (cdc_m_axil_wdata), + .s_axil_wstrb (cdc_m_axil_wstrb), + .s_axil_wvalid (cdc_m_axil_wvalid), + .s_axil_wready (cdc_m_axil_wready), + .s_axil_bresp (cdc_m_axil_bresp), + .s_axil_bvalid (cdc_m_axil_bvalid), + .s_axil_bready (cdc_m_axil_bready), + .s_axil_araddr (cdc_m_axil_araddr), + .s_axil_arprot (cdc_m_axil_arprot), + .s_axil_arvalid (cdc_m_axil_arvalid), + .s_axil_arready (cdc_m_axil_arready), + .s_axil_rdata (cdc_m_axil_rdata), + .s_axil_rresp (cdc_m_axil_rresp), + .s_axil_rvalid (cdc_m_axil_rvalid), + .s_axil_rready (cdc_m_axil_rready), + + .m_clk (m_clk), + .m_rst (m_rst), + .m_axil_awaddr (cdc_s_axil_awaddr), + .m_axil_awprot (cdc_s_axil_awprot), + .m_axil_awvalid (cdc_s_axil_awvalid), + .m_axil_awready (cdc_s_axil_awready), + .m_axil_wdata (cdc_s_axil_wdata), + .m_axil_wstrb (cdc_s_axil_wstrb), + .m_axil_wvalid (cdc_s_axil_wvalid), + .m_axil_wready (cdc_s_axil_wready), + .m_axil_bresp (cdc_s_axil_bresp), + .m_axil_bvalid (cdc_s_axil_bvalid), + .m_axil_bready (cdc_s_axil_bready), + .m_axil_araddr (cdc_s_axil_araddr), + .m_axil_arprot (cdc_s_axil_arprot), + .m_axil_arvalid (cdc_s_axil_arvalid), + .m_axil_arready (cdc_s_axil_arready), + .m_axil_rdata (cdc_s_axil_rdata), + .m_axil_rresp (cdc_s_axil_rresp), + .m_axil_rvalid (cdc_s_axil_rvalid), + .m_axil_rready (cdc_s_axil_rready) + ); + + axi4l_flat_to_if #( + .ADDR_W (ADDR_WIDTH), + .DATA_W (DATA_WIDTH) + ) i_axi4l_flat_to_if ( + .s_axil_awaddr (cdc_s_axil_awaddr), + .s_axil_awprot (cdc_s_axil_awprot), + .s_axil_awuser (cdc_s_axil_awuser), + .s_axil_awvalid (cdc_s_axil_awvalid), + .s_axil_awready (cdc_s_axil_awready), + .s_axil_wdata (cdc_s_axil_wdata), + .s_axil_wstrb (cdc_s_axil_wstrb), + .s_axil_wuser (cdc_s_axil_wuser), + .s_axil_wvalid (cdc_s_axil_wvalid), + .s_axil_wready (cdc_s_axil_wready), + .s_axil_bresp (cdc_s_axil_bresp), + .s_axil_buser (cdc_s_axil_buser), + .s_axil_bvalid (cdc_s_axil_bvalid), + .s_axil_bready (cdc_s_axil_bready), + .s_axil_araddr (cdc_s_axil_araddr), + .s_axil_arprot (cdc_s_axil_arprot), + .s_axil_aruser (cdc_s_axil_aruser), + .s_axil_arvalid (cdc_s_axil_arvalid), + .s_axil_arready (cdc_s_axil_arready), + .s_axil_rdata (cdc_s_axil_rdata), + .s_axil_rresp (cdc_s_axil_rresp), + .s_axil_ruser (cdc_s_axil_ruser), + .s_axil_rvalid (cdc_s_axil_rvalid), + .s_axil_rready (cdc_s_axil_rready), + .m_axil (m_axil) + ); + +endmodule \ No newline at end of file