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Phil 3261b66aaa fix: syntax errors
2026-05-29 15:30:24 +03:00
axi
fix: syntax errors
2026-05-29 15:30:24 +03:00
README.md
chore: first commit
2026-05-28 16:40:47 +03:00

README.md

RTL Libs

AXI Defines

Description
universal components for FPGA development
Readme 98 KiB
Languages
SystemVerilog 100%