diff --git a/axi/axi_crossbar_wrapper.sv b/axi/axi_crossbar_wrapper.sv
index 25adeac..c3212bd 100644
--- a/axi/axi_crossbar_wrapper.sv
+++ b/axi/axi_crossbar_wrapper.sv
@@ -2,7 +2,7 @@ module axi_crossbar_wrapper #(
     parameter int SLAVE_QTY = 3,
     parameter int MASTER_QTY = 3,
     parameter int ADDR_WIDTH = 32,
-    parameter int DATA_WIDTH = 32
+    parameter int DATA_WIDTH = 32,
     parameter int STRB_WIDTH = (DATA_WIDTH/8)
 )(
     input  wire clk,
diff --git a/axi/axi_if.sv b/axi/axi_if.sv
index 66af213..af8cb7e 100644
--- a/axi/axi_if.sv
+++ b/axi/axi_if.sv
@@ -13,7 +13,7 @@ interface axi4_if #(
   typedef logic [DATA_W/8-1:0] strb_t;
   typedef logic [ID_W-1:0]     id_t;
   typedef logic [USER_W-1:0]   user_t;
-  `AXI4_TYPEDEF_ALL(axi, addr_t, data_t, strb_t, id_t, user_t)
+  `AXI4_TYPEDEF_ALL(axi, addr_t, data_t, strb_t, id_t, user_t);
   axi_req_t  req;
   axi_resp_t resp;
   modport master (input aclk, aresetn, output req, input resp);
@@ -34,7 +34,7 @@ interface axi4l_if #(
   typedef logic [DATA_W-1:0]   data_t;
   typedef logic [DATA_W/8-1:0] strb_t;
   typedef logic [USER_W-1:0]   user_t;
-  `AXI4L_TYPEDEF_ALL(axil, addr_t, data_t, strb_t, user_t)
+  `AXI4L_TYPEDEF_ALL(axil, addr_t, data_t, strb_t, user_t);
   axil_req_t  req;
   axil_resp_t resp;
   modport master (input aclk, aresetn, output req, input resp);
diff --git a/axi/axil_cdc_wrapper.sv b/axi/axil_cdc_wrapper.sv
index 09a547c..e6012c9 100644
--- a/axi/axil_cdc_wrapper.sv
+++ b/axi/axil_cdc_wrapper.sv
@@ -1,6 +1,6 @@
 module axil_cdc_wrapper #(
-    parameter int ADDR_WIDTH = 32
-    parameter int DATA_WIDTH = 32,
+    parameter int ADDR_WIDTH = 32,
+    parameter int DATA_WIDTH = 32
 )(
     input wire s_clk,
     input wire s_rst,
@@ -83,8 +83,8 @@ module axil_cdc_wrapper #(
     );
 
     axil_cdc #(
-        .ADDR_WIDTH (ADDR_WIDTH)
-        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (ADDR_WIDTH),
+        .DATA_WIDTH (DATA_WIDTH)
     ) i_axil_cdc (
         .s_clk          (s_clk),
         .s_rst          (s_rst),