rtl: sampler synchronization work, not totally ready

README.md

@@ -1,3 +1,10 @@
 # reflectometer_fpga_project
 
-Проект по разработке аппаратной вычислительной части для отпического рефлектометра для обнаружения утечек.
+Проект по разработке аппаратной вычислительной части для оптического рефлектометра для обнаружения утечек.
+
+## Структура
+- constaints: констрейны под ПЛИСы
+- designs: разные сборные дизайны, включая полный проект
+- rtl: код блоков, в каждой папке есть src и tests
+- scripts: скрипты для сборки 
+- software: программные скрипты

designs/README.md

@@ -1,5 +1,5 @@
 # Директория с тестовыми проектами под ПЛИСу
 
-- eth_ctrl_debug: проект с ethernet и контроллером. Позволяет через ILA проверить, что пакет правильно принимается и что значения правильно выставляются.
+- adc_dac_synchronizer: проект для тестирования и отладки связки сэмплер + контроллер + генератор, проверки синхронизации между импульсами.
-
+- reflectometer_base: базовый проект рефлектометра без внешних интерфейсов, только I/O через AXI Stream.
-- eth_generator: проект на базе eth_ctrl_debug, в который включен генератор импульсов. В паре с ЦАП можно через консольку по Ethernet запускать генерацию разных импульсов.
+- reflectometer_prototype: тестовый проект под AX7102 с управлением и отправкой данных по ethernet.

designs/adc_dac_synchoronizer/Makefile

@@ -7,7 +7,7 @@
 #
 
 # FPGA settings
-FPGA_PART = xc7a35tfgg484-1
+FPGA_PART = xc7a100tfgg484-2
 FPGA_TOP = sync_top
 FPGA_ARCH = artix7
 
@@ -16,13 +16,19 @@ RTL_DIR = ../../rtl
 
 include ../../scripts/vivado.mk
 
+
+SYN_FILES += $(sort $(shell find ../../rtl/sampler/src -type f -name '*.sv'))
+SYN_FILES += $(sort $(shell find ../../rtl/generator/src -type f -name '*.sv'))
 SYN_FILES += sync_top.sv
-SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
 
+XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
 
-XDC_FILES += ../../constraints/ax7a035b.xdc
+XDC_FILES += ../../constraints/ax7102.xdc
 XDC_FILES += debug.xdc
 
+SYN_FILES += tb_sync_top.sv
+SIM_TOP = tb_top
+
 
 
 program: $(PROJECT).bit

designs/eth_ctrl_debug/Makefile

@@ -1,52 +0,0 @@
-# SPDX-License-Identifier: MIT
-#
-# Copyright (c) 2025 FPGA Ninja, LLC
-#
-# Authors:
-# - Alex Forencich
-#
-
-# FPGA settings
-FPGA_PART = xc7a35tfgg484-1
-FPGA_TOP = eth_ctrl_debug_top
-FPGA_ARCH = artix7
-
-RTL_DIR = ../../rtl
-
-
-include ../../scripts/vivado.mk
-
-SYN_FILES += eth_ctrl_debug.sv
-SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
-
-XCI_FILES = $(sort $(shell find ../../rtl/ethernet-udp/src -type f -name '*.xci'))
-XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
-
-XDC_FILES += ../../constraints/ax7a035b.xdc
-XDC_FILES += debug.xdc
-
-
-
-program: $(PROJECT).bit
-	echo "open_hw_manager" > program.tcl
-	echo "connect_hw_server" >> program.tcl
-	echo "open_hw_target" >> program.tcl
-	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
-	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
-	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
-	echo "program_hw_devices [current_hw_device]" >> program.tcl
-	echo "exit" >> program.tcl
-	vivado -nojournal -nolog -mode batch -source program.tcl
-
-$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
-	echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
-	echo "exit" >> generate_mcs.tcl
-	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
-	mkdir -p rev
-	COUNT=100; \
-	while [ -e rev/$*_rev$$COUNT.bit ]; \
-	do COUNT=$$((COUNT+1)); done; \
-	COUNT=$$((COUNT-1)); \
-	for x in .mcs .prm; \
-	do cp $*$$x rev/$*_rev$$COUNT$$x; \
-	echo "Output: rev/$*_rev$$COUNT$$x"; done;

designs/eth_ctrl_debug/README.md

@@ -1,7 +0,0 @@
-# Тестовый проект Eth + CTRL
-Проект состоит из AXIS Ethernet и контроллера. Для тестирования сделано три разных частотных домена: ethernet 125MHz, DAC 130MHz, ADC 65MHz для тестирования сихронизации. Есть ILA на все выходы контроллера и на шину AXIS eth -> ctrl. Для отправки пакетов используйте скрипт ```console.py --debug```.
-
-## Сборка
-```make all``` - собрать все до битстрима
-
-```make vivado``` - открыть проект в Vivado

designs/eth_ctrl_debug/debug.xdc

@@ -1,147 +0,0 @@
-set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst]
-
-
-
-
-create_debug_core u_ila_0 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property port_width 1 [get_debug_ports u_ila_0/clk]
-connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out2]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-set_property port_width 32 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {adc_pulse_period_dbg[0]} {adc_pulse_period_dbg[1]} {adc_pulse_period_dbg[2]} {adc_pulse_period_dbg[3]} {adc_pulse_period_dbg[4]} {adc_pulse_period_dbg[5]} {adc_pulse_period_dbg[6]} {adc_pulse_period_dbg[7]} {adc_pulse_period_dbg[8]} {adc_pulse_period_dbg[9]} {adc_pulse_period_dbg[10]} {adc_pulse_period_dbg[11]} {adc_pulse_period_dbg[12]} {adc_pulse_period_dbg[13]} {adc_pulse_period_dbg[14]} {adc_pulse_period_dbg[15]} {adc_pulse_period_dbg[16]} {adc_pulse_period_dbg[17]} {adc_pulse_period_dbg[18]} {adc_pulse_period_dbg[19]} {adc_pulse_period_dbg[20]} {adc_pulse_period_dbg[21]} {adc_pulse_period_dbg[22]} {adc_pulse_period_dbg[23]} {adc_pulse_period_dbg[24]} {adc_pulse_period_dbg[25]} {adc_pulse_period_dbg[26]} {adc_pulse_period_dbg[27]} {adc_pulse_period_dbg[28]} {adc_pulse_period_dbg[29]} {adc_pulse_period_dbg[30]} {adc_pulse_period_dbg[31]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-set_property port_width 8 [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {finish_cnt[0]} {finish_cnt[1]} {finish_cnt[2]} {finish_cnt[3]} {finish_cnt[4]} {finish_cnt[5]} {finish_cnt[6]} {finish_cnt[7]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-set_property port_width 16 [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {adc_pulse_num_dbg[0]} {adc_pulse_num_dbg[1]} {adc_pulse_num_dbg[2]} {adc_pulse_num_dbg[3]} {adc_pulse_num_dbg[4]} {adc_pulse_num_dbg[5]} {adc_pulse_num_dbg[6]} {adc_pulse_num_dbg[7]} {adc_pulse_num_dbg[8]} {adc_pulse_num_dbg[9]} {adc_pulse_num_dbg[10]} {adc_pulse_num_dbg[11]} {adc_pulse_num_dbg[12]} {adc_pulse_num_dbg[13]} {adc_pulse_num_dbg[14]} {adc_pulse_num_dbg[15]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-set_property port_width 1 [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list adc_rst_dbg]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-set_property port_width 1 [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list adc_start_dbg]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-set_property port_width 1 [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list finish_dbg]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-set_property port_width 1 [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list finish_pending]]
-create_debug_core u_ila_1 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
-set_property port_width 1 [get_debug_ports u_ila_1/clk]
-connect_debug_port u_ila_1/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
-set_property port_width 2 [get_debug_ports u_ila_1/probe0]
-connect_debug_port u_ila_1/probe0 [get_nets [list {axis_mac0/rx_state[0]} {axis_mac0/rx_state[1]}]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
-set_property port_width 16 [get_debug_ports u_ila_1/probe1]
-connect_debug_port u_ila_1/probe1 [get_nets [list {axis_mac0/udp_rec_data_length[0]} {axis_mac0/udp_rec_data_length[1]} {axis_mac0/udp_rec_data_length[2]} {axis_mac0/udp_rec_data_length[3]} {axis_mac0/udp_rec_data_length[4]} {axis_mac0/udp_rec_data_length[5]} {axis_mac0/udp_rec_data_length[6]} {axis_mac0/udp_rec_data_length[7]} {axis_mac0/udp_rec_data_length[8]} {axis_mac0/udp_rec_data_length[9]} {axis_mac0/udp_rec_data_length[10]} {axis_mac0/udp_rec_data_length[11]} {axis_mac0/udp_rec_data_length[12]} {axis_mac0/udp_rec_data_length[13]} {axis_mac0/udp_rec_data_length[14]} {axis_mac0/udp_rec_data_length[15]}]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
-set_property port_width 96 [get_debug_ports u_ila_1/probe2]
-connect_debug_port u_ila_1/probe2 [get_nets [list {udp_ctrl_inst/cfg_bus_eth[0]} {udp_ctrl_inst/cfg_bus_eth[1]} {udp_ctrl_inst/cfg_bus_eth[2]} {udp_ctrl_inst/cfg_bus_eth[3]} {udp_ctrl_inst/cfg_bus_eth[4]} {udp_ctrl_inst/cfg_bus_eth[5]} {udp_ctrl_inst/cfg_bus_eth[6]} {udp_ctrl_inst/cfg_bus_eth[7]} {udp_ctrl_inst/cfg_bus_eth[8]} {udp_ctrl_inst/cfg_bus_eth[9]} {udp_ctrl_inst/cfg_bus_eth[10]} {udp_ctrl_inst/cfg_bus_eth[11]} {udp_ctrl_inst/cfg_bus_eth[12]} {udp_ctrl_inst/cfg_bus_eth[13]} {udp_ctrl_inst/cfg_bus_eth[14]} {udp_ctrl_inst/cfg_bus_eth[15]} {udp_ctrl_inst/cfg_bus_eth[16]} {udp_ctrl_inst/cfg_bus_eth[17]} {udp_ctrl_inst/cfg_bus_eth[18]} {udp_ctrl_inst/cfg_bus_eth[19]} {udp_ctrl_inst/cfg_bus_eth[20]} {udp_ctrl_inst/cfg_bus_eth[21]} {udp_ctrl_inst/cfg_bus_eth[22]} {udp_ctrl_inst/cfg_bus_eth[23]} {udp_ctrl_inst/cfg_bus_eth[24]} {udp_ctrl_inst/cfg_bus_eth[25]} {udp_ctrl_inst/cfg_bus_eth[26]} {udp_ctrl_inst/cfg_bus_eth[27]} {udp_ctrl_inst/cfg_bus_eth[28]} {udp_ctrl_inst/cfg_bus_eth[29]} {udp_ctrl_inst/cfg_bus_eth[30]} {udp_ctrl_inst/cfg_bus_eth[31]} {udp_ctrl_inst/cfg_bus_eth[32]} {udp_ctrl_inst/cfg_bus_eth[33]} {udp_ctrl_inst/cfg_bus_eth[34]} {udp_ctrl_inst/cfg_bus_eth[35]} {udp_ctrl_inst/cfg_bus_eth[36]} {udp_ctrl_inst/cfg_bus_eth[37]} {udp_ctrl_inst/cfg_bus_eth[38]} {udp_ctrl_inst/cfg_bus_eth[39]} {udp_ctrl_inst/cfg_bus_eth[40]} {udp_ctrl_inst/cfg_bus_eth[41]} {udp_ctrl_inst/cfg_bus_eth[42]} {udp_ctrl_inst/cfg_bus_eth[43]} {udp_ctrl_inst/cfg_bus_eth[44]} {udp_ctrl_inst/cfg_bus_eth[45]} {udp_ctrl_inst/cfg_bus_eth[46]} {udp_ctrl_inst/cfg_bus_eth[47]} {udp_ctrl_inst/cfg_bus_eth[48]} {udp_ctrl_inst/cfg_bus_eth[49]} {udp_ctrl_inst/cfg_bus_eth[50]} {udp_ctrl_inst/cfg_bus_eth[51]} {udp_ctrl_inst/cfg_bus_eth[52]} {udp_ctrl_inst/cfg_bus_eth[53]} {udp_ctrl_inst/cfg_bus_eth[54]} {udp_ctrl_inst/cfg_bus_eth[55]} {udp_ctrl_inst/cfg_bus_eth[56]} {udp_ctrl_inst/cfg_bus_eth[57]} {udp_ctrl_inst/cfg_bus_eth[58]} {udp_ctrl_inst/cfg_bus_eth[59]} {udp_ctrl_inst/cfg_bus_eth[60]} {udp_ctrl_inst/cfg_bus_eth[61]} {udp_ctrl_inst/cfg_bus_eth[62]} {udp_ctrl_inst/cfg_bus_eth[63]} {udp_ctrl_inst/cfg_bus_eth[64]} {udp_ctrl_inst/cfg_bus_eth[65]} {udp_ctrl_inst/cfg_bus_eth[66]} {udp_ctrl_inst/cfg_bus_eth[67]} {udp_ctrl_inst/cfg_bus_eth[68]} {udp_ctrl_inst/cfg_bus_eth[69]} {udp_ctrl_inst/cfg_bus_eth[70]} {udp_ctrl_inst/cfg_bus_eth[71]} {udp_ctrl_inst/cfg_bus_eth[72]} {udp_ctrl_inst/cfg_bus_eth[73]} {udp_ctrl_inst/cfg_bus_eth[74]} {udp_ctrl_inst/cfg_bus_eth[75]} {udp_ctrl_inst/cfg_bus_eth[76]} {udp_ctrl_inst/cfg_bus_eth[77]} {udp_ctrl_inst/cfg_bus_eth[78]} {udp_ctrl_inst/cfg_bus_eth[79]} {udp_ctrl_inst/cfg_bus_eth[80]} {udp_ctrl_inst/cfg_bus_eth[81]} {udp_ctrl_inst/cfg_bus_eth[82]} {udp_ctrl_inst/cfg_bus_eth[83]} {udp_ctrl_inst/cfg_bus_eth[84]} {udp_ctrl_inst/cfg_bus_eth[85]} {udp_ctrl_inst/cfg_bus_eth[86]} {udp_ctrl_inst/cfg_bus_eth[87]} {udp_ctrl_inst/cfg_bus_eth[88]} {udp_ctrl_inst/cfg_bus_eth[89]} {udp_ctrl_inst/cfg_bus_eth[90]} {udp_ctrl_inst/cfg_bus_eth[91]} {udp_ctrl_inst/cfg_bus_eth[92]} {udp_ctrl_inst/cfg_bus_eth[93]} {udp_ctrl_inst/cfg_bus_eth[94]} {udp_ctrl_inst/cfg_bus_eth[95]}]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
-set_property port_width 16 [get_debug_ports u_ila_1/probe3]
-connect_debug_port u_ila_1/probe3 [get_nets [list {axis_mac0/rx_payload_len[0]} {axis_mac0/rx_payload_len[1]} {axis_mac0/rx_payload_len[2]} {axis_mac0/rx_payload_len[3]} {axis_mac0/rx_payload_len[4]} {axis_mac0/rx_payload_len[5]} {axis_mac0/rx_payload_len[6]} {axis_mac0/rx_payload_len[7]} {axis_mac0/rx_payload_len[8]} {axis_mac0/rx_payload_len[9]} {axis_mac0/rx_payload_len[10]} {axis_mac0/rx_payload_len[11]} {axis_mac0/rx_payload_len[12]} {axis_mac0/rx_payload_len[13]} {axis_mac0/rx_payload_len[14]} {axis_mac0/rx_payload_len[15]}]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
-set_property port_width 8 [get_debug_ports u_ila_1/probe4]
-connect_debug_port u_ila_1/probe4 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]}]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
-set_property port_width 3 [get_debug_ports u_ila_1/probe5]
-connect_debug_port u_ila_1/probe5 [get_nets [list {udp_ctrl_inst/eth_state[0]} {udp_ctrl_inst/eth_state[1]} {udp_ctrl_inst/eth_state[2]}]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
-set_property port_width 1 [get_debug_ports u_ila_1/probe6]
-connect_debug_port u_ila_1/probe6 [get_nets [list axis_mac0/arp_found]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
-set_property port_width 1 [get_debug_ports u_ila_1/probe7]
-connect_debug_port u_ila_1/probe7 [get_nets [list udp_ctrl_inst/axis_hs]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
-set_property port_width 1 [get_debug_ports u_ila_1/probe8]
-connect_debug_port u_ila_1/probe8 [get_nets [list udp_ctrl_inst/busy_flag_eth]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
-set_property port_width 1 [get_debug_ports u_ila_1/probe9]
-connect_debug_port u_ila_1/probe9 [get_nets [list axis_mac0/m_axis_rx_tlast]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
-set_property port_width 1 [get_debug_ports u_ila_1/probe10]
-connect_debug_port u_ila_1/probe10 [get_nets [list m_axis_rx_tlast]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11]
-set_property port_width 1 [get_debug_ports u_ila_1/probe11]
-connect_debug_port u_ila_1/probe11 [get_nets [list axis_mac0/m_axis_rx_tready]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12]
-set_property port_width 1 [get_debug_ports u_ila_1/probe12]
-connect_debug_port u_ila_1/probe12 [get_nets [list m_axis_rx_tready]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13]
-set_property port_width 1 [get_debug_ports u_ila_1/probe13]
-connect_debug_port u_ila_1/probe13 [get_nets [list axis_mac0/req_ready]]
-create_debug_core u_ila_2 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
-set_property port_width 1 [get_debug_ports u_ila_2/clk]
-connect_debug_port u_ila_2/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out1]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
-set_property port_width 12 [get_debug_ports u_ila_2/probe0]
-connect_debug_port u_ila_2/probe0 [get_nets [list {dac_pulse_height_dbg[0]} {dac_pulse_height_dbg[1]} {dac_pulse_height_dbg[2]} {dac_pulse_height_dbg[3]} {dac_pulse_height_dbg[4]} {dac_pulse_height_dbg[5]} {dac_pulse_height_dbg[6]} {dac_pulse_height_dbg[7]} {dac_pulse_height_dbg[8]} {dac_pulse_height_dbg[9]} {dac_pulse_height_dbg[10]} {dac_pulse_height_dbg[11]}]]
-create_debug_port u_ila_2 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
-set_property port_width 16 [get_debug_ports u_ila_2/probe1]
-connect_debug_port u_ila_2/probe1 [get_nets [list {dac_pulse_num_dbg[0]} {dac_pulse_num_dbg[1]} {dac_pulse_num_dbg[2]} {dac_pulse_num_dbg[3]} {dac_pulse_num_dbg[4]} {dac_pulse_num_dbg[5]} {dac_pulse_num_dbg[6]} {dac_pulse_num_dbg[7]} {dac_pulse_num_dbg[8]} {dac_pulse_num_dbg[9]} {dac_pulse_num_dbg[10]} {dac_pulse_num_dbg[11]} {dac_pulse_num_dbg[12]} {dac_pulse_num_dbg[13]} {dac_pulse_num_dbg[14]} {dac_pulse_num_dbg[15]}]]
-create_debug_port u_ila_2 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2]
-set_property port_width 32 [get_debug_ports u_ila_2/probe2]
-connect_debug_port u_ila_2/probe2 [get_nets [list {dac_pulse_period_dbg[0]} {dac_pulse_period_dbg[1]} {dac_pulse_period_dbg[2]} {dac_pulse_period_dbg[3]} {dac_pulse_period_dbg[4]} {dac_pulse_period_dbg[5]} {dac_pulse_period_dbg[6]} {dac_pulse_period_dbg[7]} {dac_pulse_period_dbg[8]} {dac_pulse_period_dbg[9]} {dac_pulse_period_dbg[10]} {dac_pulse_period_dbg[11]} {dac_pulse_period_dbg[12]} {dac_pulse_period_dbg[13]} {dac_pulse_period_dbg[14]} {dac_pulse_period_dbg[15]} {dac_pulse_period_dbg[16]} {dac_pulse_period_dbg[17]} {dac_pulse_period_dbg[18]} {dac_pulse_period_dbg[19]} {dac_pulse_period_dbg[20]} {dac_pulse_period_dbg[21]} {dac_pulse_period_dbg[22]} {dac_pulse_period_dbg[23]} {dac_pulse_period_dbg[24]} {dac_pulse_period_dbg[25]} {dac_pulse_period_dbg[26]} {dac_pulse_period_dbg[27]} {dac_pulse_period_dbg[28]} {dac_pulse_period_dbg[29]} {dac_pulse_period_dbg[30]} {dac_pulse_period_dbg[31]}]]
-create_debug_port u_ila_2 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3]
-set_property port_width 32 [get_debug_ports u_ila_2/probe3]
-connect_debug_port u_ila_2/probe3 [get_nets [list {dac_pulse_width_dbg[0]} {dac_pulse_width_dbg[1]} {dac_pulse_width_dbg[2]} {dac_pulse_width_dbg[3]} {dac_pulse_width_dbg[4]} {dac_pulse_width_dbg[5]} {dac_pulse_width_dbg[6]} {dac_pulse_width_dbg[7]} {dac_pulse_width_dbg[8]} {dac_pulse_width_dbg[9]} {dac_pulse_width_dbg[10]} {dac_pulse_width_dbg[11]} {dac_pulse_width_dbg[12]} {dac_pulse_width_dbg[13]} {dac_pulse_width_dbg[14]} {dac_pulse_width_dbg[15]} {dac_pulse_width_dbg[16]} {dac_pulse_width_dbg[17]} {dac_pulse_width_dbg[18]} {dac_pulse_width_dbg[19]} {dac_pulse_width_dbg[20]} {dac_pulse_width_dbg[21]} {dac_pulse_width_dbg[22]} {dac_pulse_width_dbg[23]} {dac_pulse_width_dbg[24]} {dac_pulse_width_dbg[25]} {dac_pulse_width_dbg[26]} {dac_pulse_width_dbg[27]} {dac_pulse_width_dbg[28]} {dac_pulse_width_dbg[29]} {dac_pulse_width_dbg[30]} {dac_pulse_width_dbg[31]}]]
-create_debug_port u_ila_2 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4]
-set_property port_width 1 [get_debug_ports u_ila_2/probe4]
-connect_debug_port u_ila_2/probe4 [get_nets [list dac_rst_dbg]]
-create_debug_port u_ila_2 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5]
-set_property port_width 1 [get_debug_ports u_ila_2/probe5]
-connect_debug_port u_ila_2/probe5 [get_nets [list dac_start_dbg]]
-set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
-set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
-set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
-connect_debug_port dbg_hub/clk [get_nets dac_clk]

designs/eth_ctrl_debug/eth_ctrl_debug.sv

@@ -1,298 +0,0 @@
-`timescale 1 ns / 1 ns
-
-module eth_ctrl_debug_top #(
-    parameter int unsigned DAC_DATA_WIDTH = 12
-)(
-    input               sys_clk_p,
-    input               sys_clk_n,
-    input               rst_n,
-
-    output [3:0]        led,
-
-    output              e_reset,
-    output              e_mdc,
-    inout               e_mdio,
-
-    output [3:0]        rgmii_txd,
-    output              rgmii_txctl,
-    output              rgmii_txc,
-    input  [3:0]        rgmii_rxd,
-    input               rgmii_rxctl,
-    input               rgmii_rxc
-);
-
-    // -------------------------------------------------------------------------
-    // Internal GMII-side signals
-    // -------------------------------------------------------------------------
-    wire  [7:0] gmii_txd;
-    wire        gmii_tx_en;
-    wire        gmii_tx_er;
-    wire        gmii_tx_clk;
-    wire        gmii_crs;
-    wire        gmii_col;
-    wire  [7:0] gmii_rxd_i;
-    wire        gmii_rx_dv;
-    wire        gmii_rx_er;
-    wire        gmii_rx_clk;
-
-    wire [31:0] pack_total_len;
-
-    wire        e_rx_dv;
-    wire [7:0]  e_rxd;
-    wire        e_tx_en;
-    wire [7:0]  e_txd;
-    wire        e_rst_n;
-    wire        sys_clk;
-
-    wire        duplex_mode;
-
-    assign duplex_mode = 1'b1;
-
-    // -------------------------------------------------------------------------
-    // System clock buffer (200 MHz differential input)
-    // -------------------------------------------------------------------------
-    IBUFDS sys_clk_ibufgds (
-        .O  (sys_clk),
-        .I  (sys_clk_p),
-        .IB (sys_clk_n)
-    );
-
-    // -------------------------------------------------------------------------
-    // IDELAYCTRL
-    // -------------------------------------------------------------------------
-    (* IODELAY_GROUP = "rgmii_idelay_group" *)
-    IDELAYCTRL IDELAYCTRL_inst (
-        .RDY    (),
-        .REFCLK (sys_clk),
-        .RST    (1'b0)
-    );
-
-    // -------------------------------------------------------------------------
-    // Generated clocks for controller
-    // Need to create this IP in Vivado:
-    //  input : 200 MHz
-    //  output0: 130 MHz
-    //  output1: 65 MHz
-    // -------------------------------------------------------------------------
-    wire dac_clk;
-    wire adc_clk;
-    wire clk_wiz_locked;
-
-    clk_wiz_ctrl_inst clk_wiz_ctrl_inst (
-        .clk_in1   (sys_clk),
-        .reset    (~rst_n),
-        .clk_out1  (dac_clk),   // 130 MHz
-        .clk_out2  (adc_clk),   // 65 MHz
-        .locked    (clk_wiz_locked)
-    );
-
-    // -------------------------------------------------------------------------
-    // GMII <-> RGMII conversion
-    // -------------------------------------------------------------------------
-    util_gmii_to_rgmii util_gmii_to_rgmii_m0 (
-        .reset           (1'b0),
-        .rgmii_td        (rgmii_txd),
-        .rgmii_tx_ctl    (rgmii_txctl),
-        .rgmii_txc       (rgmii_txc),
-        .rgmii_rd        (rgmii_rxd),
-        .rgmii_rx_ctl    (rgmii_rxctl),
-        .gmii_rx_clk     (gmii_rx_clk),
-        .gmii_txd        (e_txd),
-        .gmii_tx_en      (e_tx_en),
-        .gmii_tx_er      (1'b0),
-        .gmii_tx_clk     (gmii_tx_clk),
-        .gmii_crs        (gmii_crs),
-        .gmii_col        (gmii_col),
-        .gmii_rxd        (gmii_rxd_i),
-        .rgmii_rxc       (rgmii_rxc),
-        .gmii_rx_dv      (gmii_rx_dv),
-        .gmii_rx_er      (gmii_rx_er),
-        .speed_selection (2'b10),
-        .duplex_mode     (duplex_mode)
-    );
-
-    // -------------------------------------------------------------------------
-    // GMII arbitration / adaptation
-    // -------------------------------------------------------------------------
-    gmii_arbi arbi_inst (
-        .clk            (gmii_tx_clk),
-        .rst_n          (rst_n),
-        .speed          (2'b10),
-        .link           (1'b1),
-        .pack_total_len (pack_total_len),
-        .e_rst_n        (e_rst_n),
-        .gmii_rx_dv     (gmii_rx_dv),
-        .gmii_rxd       (gmii_rxd_i),
-        .gmii_tx_en     (gmii_tx_en),
-        .gmii_txd       (gmii_txd),
-        .e_rx_dv        (e_rx_dv),
-        .e_rxd          (e_rxd),
-        .e_tx_en        (e_tx_en),
-        .e_txd          (e_txd)
-    );
-
-    // -------------------------------------------------------------------------
-    // axis_mac interface
-    // RX stream from Ethernet goes into controller
-    // TX stream is unused for now
-    // -------------------------------------------------------------------------
-    wire        req_ready;
-
-    reg         send_req;
-    reg  [15:0] data_length;
-
-    reg  [7:0]  s_axis_tx_tdata;
-    reg         s_axis_tx_tvalid;
-    wire        s_axis_tx_tready;
-    reg         s_axis_tx_tlast;
-
-    (* MARK_DEBUG="true" *) wire [7:0]  m_axis_rx_tdata;
-    (* MARK_DEBUG="true" *) wire        m_axis_rx_tvalid;
-    (* MARK_DEBUG="true" *) wire        m_axis_rx_tlast;
-    (* MARK_DEBUG="true" *) wire        m_axis_rx_tready;
-
-    // Always ready to accept RX payload bytes
-    assign m_axis_rx_tready = 1'b1;
-
-    // TX disabled
-    always @(*) begin
-        send_req        = 1'b0;
-        data_length     = 16'd0;
-        s_axis_tx_tdata = 8'd0;
-        s_axis_tx_tvalid= 1'b0;
-        s_axis_tx_tlast = 1'b0;
-    end
-
-    axis_mac axis_mac0 (
-        .gmii_tx_clk       (gmii_tx_clk),
-        .gmii_rx_clk       (gmii_rx_clk),
-        .rst_n             (e_rst_n),
-
-        .gmii_rx_dv        (e_rx_dv),
-        .gmii_rxd          (e_rxd),
-        .gmii_tx_en        (gmii_tx_en),
-        .gmii_txd          (gmii_txd),
-
-        .send_req          (send_req),
-        .data_length       (data_length),
-        .req_ready         (req_ready),
-
-        .s_axis_tx_tdata   (s_axis_tx_tdata),
-        .s_axis_tx_tvalid  (s_axis_tx_tvalid),
-        .s_axis_tx_tready  (s_axis_tx_tready),
-        .s_axis_tx_tlast   (s_axis_tx_tlast),
-
-        .m_axis_rx_tdata   (m_axis_rx_tdata),
-        .m_axis_rx_tvalid  (m_axis_rx_tvalid),
-        .m_axis_rx_tready  (m_axis_rx_tready),
-        .m_axis_rx_tlast   (m_axis_rx_tlast)
-    );
-
-    // PHY reset helper from your original example
-    reset reset_m0 (
-        .clk   (sys_clk),
-        .key1  (rst_n),
-        .rst_n (e_reset)
-    );
-
-    // MDIO lines are not driven here yet
-    assign e_mdc  = 1'b0;
-    assign e_mdio = 1'bz;
-
-    // -------------------------------------------------------------------------
-    // Controller reset
-    // Use both external reset and clk_wiz lock
-    // -------------------------------------------------------------------------
-    wire ctrl_rst_n = rst_n & clk_wiz_locked;
-
-    // -------------------------------------------------------------------------
-    // Debug finish generator
-    //
-    // After each adc_start pulse generates one finish pulse after some delay.
-    // This is just for first bring-up so the controller can leave busy state
-    // If you don't want this, replace with:
-    // wire finish_dbg = 1'b0;
-    // -------------------------------------------------------------------------
-    (* MARK_DEBUG="true" *) logic        finish_dbg;
-    (* MARK_DEBUG="true" *) logic [7:0]  finish_cnt;
-    (* MARK_DEBUG="true" *) logic        finish_pending;
-
-    // Controller outputs to debug
-    (* MARK_DEBUG="true" *) wire [31:0]               dac_pulse_width_dbg;
-    (* MARK_DEBUG="true" *) wire [31:0]               dac_pulse_period_dbg;
-    (* MARK_DEBUG="true" *) wire [DAC_DATA_WIDTH-1:0] dac_pulse_height_dbg;
-    (* MARK_DEBUG="true" *) wire [15:0]               dac_pulse_num_dbg;
-
-    (* MARK_DEBUG="true" *) wire [31:0]               adc_pulse_period_dbg;
-    (* MARK_DEBUG="true" *) wire [15:0]               adc_pulse_num_dbg;
-
-    (* MARK_DEBUG="true" *) wire                      dac_start_dbg;
-    (* MARK_DEBUG="true" *) wire                      adc_start_dbg;
-    (* MARK_DEBUG="true" *) wire                      dac_rst_dbg;
-    (* MARK_DEBUG="true" *) wire                      adc_rst_dbg;
-
-    always_ff @(posedge adc_clk or negedge ctrl_rst_n) begin
-        if (!ctrl_rst_n) begin
-            finish_dbg     <= 1'b0;
-            finish_cnt     <= 8'd0;
-            finish_pending <= 1'b0;
-        end else begin
-            finish_dbg <= 1'b0;
-
-            if (adc_start_dbg) begin
-                finish_pending <= 1'b1;
-                finish_cnt     <= 8'd80;
-            end else if (finish_pending) begin
-                if (finish_cnt == 8'd0) begin
-                    finish_dbg     <= 1'b1;
-                    finish_pending <= 1'b0;
-                end else begin
-                    finish_cnt <= finish_cnt - 8'd1;
-                end
-            end
-        end
-    end
-
-    // -------------------------------------------------------------------------
-    // Controller
-    // ETH domain = gmii_rx_clk, because RX AXI master comes from axis_mac RX side
-    // -------------------------------------------------------------------------
-    control #(
-        .DAC_DATA_WIDTH(DAC_DATA_WIDTH)
-    ) udp_ctrl_inst (
-        .eth_clk_in        (gmii_rx_clk),
-        .dac_clk_in        (dac_clk),
-        .adc_clk_in        (adc_clk),
-        .rst_n             (ctrl_rst_n),
-
-        .s_axis_tdata      (m_axis_rx_tdata),
-        .s_axis_tvalid     (m_axis_rx_tvalid),
-        .s_axis_tready     (), // controller internally always ready in current version
-        .s_axis_tlast      (m_axis_rx_tlast),
-
-        .finish            (finish_dbg),
-
-        .dac_pulse_width   (dac_pulse_width_dbg),
-        .dac_pulse_period  (dac_pulse_period_dbg),
-        .dac_pulse_height  (dac_pulse_height_dbg),
-        .dac_pulse_num     (dac_pulse_num_dbg),
-
-        .adc_pulse_period  (adc_pulse_period_dbg),
-        .adc_pulse_num     (adc_pulse_num_dbg),
-
-        .dac_start         (dac_start_dbg),
-        .adc_start         (adc_start_dbg),
-
-        .dac_rst           (dac_rst_dbg),
-        .adc_rst           (adc_rst_dbg)
-    );
-
-    // -------------------------------------------------------------------------
-    // Simple LED status
-    // -------------------------------------------------------------------------
-    assign led[0] = clk_wiz_locked;
-    assign led[1] = m_axis_rx_tvalid;
-    assign led[2] = dac_start_dbg;
-    assign led[3] = adc_rst_dbg;
-
-endmodule

designs/eth_ctrl_debug/ip/clk_wiz_ctrl_inst.xci

@@ -1,689 +0,0 @@
-{
-  "schema": "xilinx.com:schema:json_instance:1.0",
-  "ip_inst": {
-    "xci_name": "clk_wiz_ctrl_inst",
-    "component_reference": "xilinx.com:ip:clk_wiz:6.0",
-    "ip_revision": "16",
-    "gen_directory": "../../../../eth_ctrl_debug_top.gen/sources_1/ip/clk_wiz_ctrl_inst",
-    "parameters": {
-      "component_parameters": {
-        "Component_Name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "user", "usage": "all" } ],
-        "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
-        "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
-        "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
-        "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
-        "PRIM_IN_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
-        "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
-        "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
-        "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
-        "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
-        "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
-        "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
-        "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKIN1_JITTER_PS": [ { "value": "50.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "NUM_OUT_CLKS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
-        "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
-        "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
-        "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
-        "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
-        "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
-        "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
-        "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
-        "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
-        "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
-        "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
-        "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
-        "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
-        "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
-        "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
-        "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
-        "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
-        "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
-        "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "130.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
-        "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
-        "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
-        "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
-        "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
-        "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
-        "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
-        "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
-        "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
-        "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
-        "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
-        "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
-        "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
-        "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
-        "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
-        "MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
-        "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "7.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKOUT1_DIVIDE": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
-        "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
-        "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
-        "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
-        "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
-        "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
-        "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
-        "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
-        "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
-        "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
-        "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
-        "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
-        "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
-        "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT1_JITTER": [ { "value": "102.676", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT1_PHASE_ERROR": [ { "value": "87.159", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT2_JITTER": [ { "value": "117.878", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
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-        "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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-        "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
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-        "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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-            "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
-          },
-          "port_maps": {
-            "CLK_IN1": [ { "physical_name": "clk_in1" } ]
-          }
-        },
-        "clock_CLK_OUT1": {
-          "vlnv": "xilinx.com:signal:clock:1.0",
-          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
-          "mode": "master",
-          "parameters": {
-            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
-            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
-          },
-          "port_maps": {
-            "CLK_OUT1": [ { "physical_name": "clk_out1" } ]
-          }
-        },
-        "clock_CLK_OUT2": {
-          "vlnv": "xilinx.com:signal:clock:1.0",
-          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
-          "mode": "master",
-          "parameters": {
-            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
-            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
-          },
-          "port_maps": {
-            "CLK_OUT2": [ { "physical_name": "clk_out2" } ]
-          }
-        }
-      }
-    }
-  }
-}

designs/eth_generator/Makefile

@@ -1,52 +0,0 @@
-# SPDX-License-Identifier: MIT
-#
-# Copyright (c) 2025 FPGA Ninja, LLC
-#
-# Authors:
-# - Alex Forencich
-#
-
-# FPGA settings
-FPGA_PART = xc7a35tfgg484-1
-FPGA_TOP = eth_generator_top
-FPGA_ARCH = artix7
-
-RTL_DIR = ../../rtl
-
-
-include ../../scripts/vivado.mk
-
-SYN_FILES += eth_generator.sv
-SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
-
-XCI_FILES = $(sort $(shell find ../../rtl/ethernet-udp/src -type f -name '*.xci'))
-XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
-
-XDC_FILES += ../../constraints/ax7a035b.xdc
-XDC_FILES += debug.xdc
-
-
-
-program: $(PROJECT).bit
-	echo "open_hw_manager" > program.tcl
-	echo "connect_hw_server" >> program.tcl
-	echo "open_hw_target" >> program.tcl
-	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
-	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
-	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
-	echo "program_hw_devices [current_hw_device]" >> program.tcl
-	echo "exit" >> program.tcl
-	vivado -nojournal -nolog -mode batch -source program.tcl
-
-$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
-	echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
-	echo "exit" >> generate_mcs.tcl
-	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
-	mkdir -p rev
-	COUNT=100; \
-	while [ -e rev/$*_rev$$COUNT.bit ]; \
-	do COUNT=$$((COUNT+1)); done; \
-	COUNT=$$((COUNT-1)); \
-	for x in .mcs .prm; \
-	do cp $*$$x rev/$*_rev$$COUNT$$x; \
-	echo "Output: rev/$*_rev$$COUNT$$x"; done;

designs/eth_generator/README.md

@@ -1,11 +0,0 @@
-# Тестовый проект Generator + ETH + CTRL
-Проект состоит из AXIS Ethernet, контроллера и генератора. Позволяет генерировать сигналы, задав параметры через Ethernet.
-## Сборка
-```make all``` - собрать все до битстрима
-
-```make vivado``` - открыть проект в Vivado
-
-## Управление
-Используйте software/console.py. Пример:
-
-```python3 console.py --pulse_width 3_500_000 --pulse_period 20_000_000 --pulse_height 10000 --pulse_num 5500 --dac-bits 14```

designs/eth_generator/debug.xdc

@@ -1,117 +0,0 @@
-set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst]
-
-
-
-
-connect_debug_port u_ila_2/probe0 [get_nets [list {dac_pulse_height_dbg[0]} {dac_pulse_height_dbg[1]} {dac_pulse_height_dbg[2]} {dac_pulse_height_dbg[3]} {dac_pulse_height_dbg[4]} {dac_pulse_height_dbg[5]} {dac_pulse_height_dbg[6]} {dac_pulse_height_dbg[7]} {dac_pulse_height_dbg[8]} {dac_pulse_height_dbg[9]} {dac_pulse_height_dbg[10]} {dac_pulse_height_dbg[11]}]]
-connect_debug_port u_ila_2/probe1 [get_nets [list {dac_pulse_num_dbg[0]} {dac_pulse_num_dbg[1]} {dac_pulse_num_dbg[2]} {dac_pulse_num_dbg[3]} {dac_pulse_num_dbg[4]} {dac_pulse_num_dbg[5]} {dac_pulse_num_dbg[6]} {dac_pulse_num_dbg[7]} {dac_pulse_num_dbg[8]} {dac_pulse_num_dbg[9]} {dac_pulse_num_dbg[10]} {dac_pulse_num_dbg[11]} {dac_pulse_num_dbg[12]} {dac_pulse_num_dbg[13]} {dac_pulse_num_dbg[14]} {dac_pulse_num_dbg[15]}]]
-connect_debug_port u_ila_2/probe2 [get_nets [list {dac_pulse_period_dbg[0]} {dac_pulse_period_dbg[1]} {dac_pulse_period_dbg[2]} {dac_pulse_period_dbg[3]} {dac_pulse_period_dbg[4]} {dac_pulse_period_dbg[5]} {dac_pulse_period_dbg[6]} {dac_pulse_period_dbg[7]} {dac_pulse_period_dbg[8]} {dac_pulse_period_dbg[9]} {dac_pulse_period_dbg[10]} {dac_pulse_period_dbg[11]} {dac_pulse_period_dbg[12]} {dac_pulse_period_dbg[13]} {dac_pulse_period_dbg[14]} {dac_pulse_period_dbg[15]} {dac_pulse_period_dbg[16]} {dac_pulse_period_dbg[17]} {dac_pulse_period_dbg[18]} {dac_pulse_period_dbg[19]} {dac_pulse_period_dbg[20]} {dac_pulse_period_dbg[21]} {dac_pulse_period_dbg[22]} {dac_pulse_period_dbg[23]} {dac_pulse_period_dbg[24]} {dac_pulse_period_dbg[25]} {dac_pulse_period_dbg[26]} {dac_pulse_period_dbg[27]} {dac_pulse_period_dbg[28]} {dac_pulse_period_dbg[29]} {dac_pulse_period_dbg[30]} {dac_pulse_period_dbg[31]}]]
-connect_debug_port u_ila_2/probe3 [get_nets [list {dac_pulse_width_dbg[0]} {dac_pulse_width_dbg[1]} {dac_pulse_width_dbg[2]} {dac_pulse_width_dbg[3]} {dac_pulse_width_dbg[4]} {dac_pulse_width_dbg[5]} {dac_pulse_width_dbg[6]} {dac_pulse_width_dbg[7]} {dac_pulse_width_dbg[8]} {dac_pulse_width_dbg[9]} {dac_pulse_width_dbg[10]} {dac_pulse_width_dbg[11]} {dac_pulse_width_dbg[12]} {dac_pulse_width_dbg[13]} {dac_pulse_width_dbg[14]} {dac_pulse_width_dbg[15]} {dac_pulse_width_dbg[16]} {dac_pulse_width_dbg[17]} {dac_pulse_width_dbg[18]} {dac_pulse_width_dbg[19]} {dac_pulse_width_dbg[20]} {dac_pulse_width_dbg[21]} {dac_pulse_width_dbg[22]} {dac_pulse_width_dbg[23]} {dac_pulse_width_dbg[24]} {dac_pulse_width_dbg[25]} {dac_pulse_width_dbg[26]} {dac_pulse_width_dbg[27]} {dac_pulse_width_dbg[28]} {dac_pulse_width_dbg[29]} {dac_pulse_width_dbg[30]} {dac_pulse_width_dbg[31]}]]
-connect_debug_port u_ila_2/probe4 [get_nets [list dac_rst_dbg]]
-connect_debug_port u_ila_2/probe5 [get_nets [list dac_start_dbg]]
-
-
-connect_debug_port u_ila_1/probe7 [get_nets [list p2_wrt_OBUF]]
-
-create_debug_core u_ila_0 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property port_width 1 [get_debug_ports u_ila_0/clk]
-connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-set_property port_width 3 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {udp_ctrl_inst/eth_state[0]} {udp_ctrl_inst/eth_state[1]} {udp_ctrl_inst/eth_state[2]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-set_property port_width 96 [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {udp_ctrl_inst/cfg_bus_eth[0]} {udp_ctrl_inst/cfg_bus_eth[1]} {udp_ctrl_inst/cfg_bus_eth[2]} {udp_ctrl_inst/cfg_bus_eth[3]} {udp_ctrl_inst/cfg_bus_eth[4]} {udp_ctrl_inst/cfg_bus_eth[5]} {udp_ctrl_inst/cfg_bus_eth[6]} {udp_ctrl_inst/cfg_bus_eth[7]} {udp_ctrl_inst/cfg_bus_eth[8]} {udp_ctrl_inst/cfg_bus_eth[9]} {udp_ctrl_inst/cfg_bus_eth[10]} {udp_ctrl_inst/cfg_bus_eth[11]} {udp_ctrl_inst/cfg_bus_eth[12]} {udp_ctrl_inst/cfg_bus_eth[13]} {udp_ctrl_inst/cfg_bus_eth[14]} {udp_ctrl_inst/cfg_bus_eth[15]} {udp_ctrl_inst/cfg_bus_eth[16]} {udp_ctrl_inst/cfg_bus_eth[17]} {udp_ctrl_inst/cfg_bus_eth[18]} {udp_ctrl_inst/cfg_bus_eth[19]} {udp_ctrl_inst/cfg_bus_eth[20]} {udp_ctrl_inst/cfg_bus_eth[21]} {udp_ctrl_inst/cfg_bus_eth[22]} {udp_ctrl_inst/cfg_bus_eth[23]} {udp_ctrl_inst/cfg_bus_eth[24]} {udp_ctrl_inst/cfg_bus_eth[25]} {udp_ctrl_inst/cfg_bus_eth[26]} {udp_ctrl_inst/cfg_bus_eth[27]} {udp_ctrl_inst/cfg_bus_eth[28]} {udp_ctrl_inst/cfg_bus_eth[29]} {udp_ctrl_inst/cfg_bus_eth[30]} {udp_ctrl_inst/cfg_bus_eth[31]} {udp_ctrl_inst/cfg_bus_eth[32]} {udp_ctrl_inst/cfg_bus_eth[33]} {udp_ctrl_inst/cfg_bus_eth[34]} {udp_ctrl_inst/cfg_bus_eth[35]} {udp_ctrl_inst/cfg_bus_eth[36]} {udp_ctrl_inst/cfg_bus_eth[37]} {udp_ctrl_inst/cfg_bus_eth[38]} {udp_ctrl_inst/cfg_bus_eth[39]} {udp_ctrl_inst/cfg_bus_eth[40]} {udp_ctrl_inst/cfg_bus_eth[41]} {udp_ctrl_inst/cfg_bus_eth[42]} {udp_ctrl_inst/cfg_bus_eth[43]} {udp_ctrl_inst/cfg_bus_eth[44]} {udp_ctrl_inst/cfg_bus_eth[45]} {udp_ctrl_inst/cfg_bus_eth[46]} {udp_ctrl_inst/cfg_bus_eth[47]} {udp_ctrl_inst/cfg_bus_eth[48]} {udp_ctrl_inst/cfg_bus_eth[49]} {udp_ctrl_inst/cfg_bus_eth[50]} {udp_ctrl_inst/cfg_bus_eth[51]} {udp_ctrl_inst/cfg_bus_eth[52]} {udp_ctrl_inst/cfg_bus_eth[53]} {udp_ctrl_inst/cfg_bus_eth[54]} {udp_ctrl_inst/cfg_bus_eth[55]} {udp_ctrl_inst/cfg_bus_eth[56]} {udp_ctrl_inst/cfg_bus_eth[57]} {udp_ctrl_inst/cfg_bus_eth[58]} {udp_ctrl_inst/cfg_bus_eth[59]} {udp_ctrl_inst/cfg_bus_eth[60]} {udp_ctrl_inst/cfg_bus_eth[61]} {udp_ctrl_inst/cfg_bus_eth[62]} {udp_ctrl_inst/cfg_bus_eth[63]} {udp_ctrl_inst/cfg_bus_eth[64]} {udp_ctrl_inst/cfg_bus_eth[65]} {udp_ctrl_inst/cfg_bus_eth[66]} {udp_ctrl_inst/cfg_bus_eth[67]} {udp_ctrl_inst/cfg_bus_eth[68]} {udp_ctrl_inst/cfg_bus_eth[69]} {udp_ctrl_inst/cfg_bus_eth[70]} {udp_ctrl_inst/cfg_bus_eth[71]} {udp_ctrl_inst/cfg_bus_eth[72]} {udp_ctrl_inst/cfg_bus_eth[73]} {udp_ctrl_inst/cfg_bus_eth[74]} {udp_ctrl_inst/cfg_bus_eth[75]} {udp_ctrl_inst/cfg_bus_eth[76]} {udp_ctrl_inst/cfg_bus_eth[77]} {udp_ctrl_inst/cfg_bus_eth[78]} {udp_ctrl_inst/cfg_bus_eth[79]} {udp_ctrl_inst/cfg_bus_eth[80]} {udp_ctrl_inst/cfg_bus_eth[81]} {udp_ctrl_inst/cfg_bus_eth[82]} {udp_ctrl_inst/cfg_bus_eth[83]} {udp_ctrl_inst/cfg_bus_eth[84]} {udp_ctrl_inst/cfg_bus_eth[85]} {udp_ctrl_inst/cfg_bus_eth[86]} {udp_ctrl_inst/cfg_bus_eth[87]} {udp_ctrl_inst/cfg_bus_eth[88]} {udp_ctrl_inst/cfg_bus_eth[89]} {udp_ctrl_inst/cfg_bus_eth[90]} {udp_ctrl_inst/cfg_bus_eth[91]} {udp_ctrl_inst/cfg_bus_eth[92]} {udp_ctrl_inst/cfg_bus_eth[93]} {udp_ctrl_inst/cfg_bus_eth[94]} {udp_ctrl_inst/cfg_bus_eth[95]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-set_property port_width 8 [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-set_property port_width 1 [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list udp_ctrl_inst/axis_hs]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-set_property port_width 1 [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list udp_ctrl_inst/busy_flag_eth]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-set_property port_width 1 [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list m_axis_rx_tlast]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-set_property port_width 1 [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list m_axis_rx_tready]]
-create_debug_core u_ila_1 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
-set_property port_width 1 [get_debug_ports u_ila_1/clk]
-connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out1]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
-set_property port_width 14 [get_debug_ports u_ila_1/probe0]
-connect_debug_port u_ila_1/probe0 [get_nets [list {p2_data_OBUF[0]} {p2_data_OBUF[1]} {p2_data_OBUF[2]} {p2_data_OBUF[3]} {p2_data_OBUF[4]} {p2_data_OBUF[5]} {p2_data_OBUF[6]} {p2_data_OBUF[7]} {p2_data_OBUF[8]} {p2_data_OBUF[9]} {p2_data_OBUF[10]} {p2_data_OBUF[11]} {p2_data_OBUF[12]} {p2_data_OBUF[13]}]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
-set_property port_width 16 [get_debug_ports u_ila_1/probe1]
-connect_debug_port u_ila_1/probe1 [get_nets [list {dac_pulse_num[0]} {dac_pulse_num[1]} {dac_pulse_num[2]} {dac_pulse_num[3]} {dac_pulse_num[4]} {dac_pulse_num[5]} {dac_pulse_num[6]} {dac_pulse_num[7]} {dac_pulse_num[8]} {dac_pulse_num[9]} {dac_pulse_num[10]} {dac_pulse_num[11]} {dac_pulse_num[12]} {dac_pulse_num[13]} {dac_pulse_num[14]} {dac_pulse_num[15]}]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
-set_property port_width 14 [get_debug_ports u_ila_1/probe2]
-connect_debug_port u_ila_1/probe2 [get_nets [list {dac_pulse_height[0]} {dac_pulse_height[1]} {dac_pulse_height[2]} {dac_pulse_height[3]} {dac_pulse_height[4]} {dac_pulse_height[5]} {dac_pulse_height[6]} {dac_pulse_height[7]} {dac_pulse_height[8]} {dac_pulse_height[9]} {dac_pulse_height[10]} {dac_pulse_height[11]} {dac_pulse_height[12]} {dac_pulse_height[13]}]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
-set_property port_width 32 [get_debug_ports u_ila_1/probe3]
-connect_debug_port u_ila_1/probe3 [get_nets [list {dac_pulse_period[0]} {dac_pulse_period[1]} {dac_pulse_period[2]} {dac_pulse_period[3]} {dac_pulse_period[4]} {dac_pulse_period[5]} {dac_pulse_period[6]} {dac_pulse_period[7]} {dac_pulse_period[8]} {dac_pulse_period[9]} {dac_pulse_period[10]} {dac_pulse_period[11]} {dac_pulse_period[12]} {dac_pulse_period[13]} {dac_pulse_period[14]} {dac_pulse_period[15]} {dac_pulse_period[16]} {dac_pulse_period[17]} {dac_pulse_period[18]} {dac_pulse_period[19]} {dac_pulse_period[20]} {dac_pulse_period[21]} {dac_pulse_period[22]} {dac_pulse_period[23]} {dac_pulse_period[24]} {dac_pulse_period[25]} {dac_pulse_period[26]} {dac_pulse_period[27]} {dac_pulse_period[28]} {dac_pulse_period[29]} {dac_pulse_period[30]} {dac_pulse_period[31]}]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
-set_property port_width 32 [get_debug_ports u_ila_1/probe4]
-connect_debug_port u_ila_1/probe4 [get_nets [list {dac_pulse_width[0]} {dac_pulse_width[1]} {dac_pulse_width[2]} {dac_pulse_width[3]} {dac_pulse_width[4]} {dac_pulse_width[5]} {dac_pulse_width[6]} {dac_pulse_width[7]} {dac_pulse_width[8]} {dac_pulse_width[9]} {dac_pulse_width[10]} {dac_pulse_width[11]} {dac_pulse_width[12]} {dac_pulse_width[13]} {dac_pulse_width[14]} {dac_pulse_width[15]} {dac_pulse_width[16]} {dac_pulse_width[17]} {dac_pulse_width[18]} {dac_pulse_width[19]} {dac_pulse_width[20]} {dac_pulse_width[21]} {dac_pulse_width[22]} {dac_pulse_width[23]} {dac_pulse_width[24]} {dac_pulse_width[25]} {dac_pulse_width[26]} {dac_pulse_width[27]} {dac_pulse_width[28]} {dac_pulse_width[29]} {dac_pulse_width[30]} {dac_pulse_width[31]}]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
-set_property port_width 1 [get_debug_ports u_ila_1/probe5]
-connect_debug_port u_ila_1/probe5 [get_nets [list dac_rst]]
-create_debug_port u_ila_1 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
-set_property port_width 1 [get_debug_ports u_ila_1/probe6]
-connect_debug_port u_ila_1/probe6 [get_nets [list dac_start]]
-create_debug_core u_ila_2 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
-set_property port_width 1 [get_debug_ports u_ila_2/clk]
-connect_debug_port u_ila_2/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out2]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
-set_property port_width 8 [get_debug_ports u_ila_2/probe0]
-connect_debug_port u_ila_2/probe0 [get_nets [list {finish_cnt[0]} {finish_cnt[1]} {finish_cnt[2]} {finish_cnt[3]} {finish_cnt[4]} {finish_cnt[5]} {finish_cnt[6]} {finish_cnt[7]}]]
-create_debug_port u_ila_2 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
-set_property port_width 1 [get_debug_ports u_ila_2/probe1]
-connect_debug_port u_ila_2/probe1 [get_nets [list finish_dbg]]
-create_debug_port u_ila_2 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2]
-set_property port_width 1 [get_debug_ports u_ila_2/probe2]
-connect_debug_port u_ila_2/probe2 [get_nets [list finish_pending]]
-set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
-set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
-set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
-connect_debug_port dbg_hub/clk [get_nets adc_clk]

designs/eth_generator/eth_generator.sv

@@ -1,345 +0,0 @@
-`timescale 1 ns / 1 ns
-
-module eth_generator_top #(
-    parameter int unsigned DAC_DATA_WIDTH = 14
-)(
-    input               sys_clk_p,
-    input               sys_clk_n,
-    input               rst_n,
-
-    output [3:0]        led,
-
-    output              e_reset,
-    output              e_mdc,
-    inout               e_mdio,
-
-    output [3:0]        rgmii_txd,
-    output              rgmii_txctl,
-    output              rgmii_txc,
-    input  [3:0]        rgmii_rxd,
-    input               rgmii_rxctl,
-    input               rgmii_rxc,
-
-    // DAC
-    output              p2_clk,
-    output              p2_wrt,
-    (* MARK_DEBUG="true" *) output [13:0]       p2_data
-);
-
-    // -------------------------------------------------------------------------
-    // Internal GMII-side signals
-    // -------------------------------------------------------------------------
-    wire  [7:0] gmii_txd;
-    wire        gmii_tx_en;
-    wire        gmii_tx_er;
-    wire        gmii_tx_clk;
-    wire        gmii_crs;
-    wire        gmii_col;
-    wire  [7:0] gmii_rxd_i;
-    wire        gmii_rx_dv;
-    wire        gmii_rx_er;
-    wire        gmii_rx_clk;
-
-    wire [31:0] pack_total_len;
-
-    wire        e_rx_dv;
-    wire [7:0]  e_rxd;
-    wire        e_tx_en;
-    wire [7:0]  e_txd;
-    wire        e_rst_n;
-    wire        sys_clk;
-
-    wire        duplex_mode;
-    
-
-    assign duplex_mode = 1'b1;
-
-    // -------------------------------------------------------------------------
-    // System clock buffer (200 MHz differential input)
-    // -------------------------------------------------------------------------
-    IBUFDS sys_clk_ibufgds (
-        .O  (sys_clk),
-        .I  (sys_clk_p),
-        .IB (sys_clk_n)
-    );
-
-    // -------------------------------------------------------------------------
-    // IDELAYCTRL
-    // -------------------------------------------------------------------------
-    (* IODELAY_GROUP = "rgmii_idelay_group" *)
-    IDELAYCTRL IDELAYCTRL_inst (
-        .RDY    (),
-        .REFCLK (sys_clk),
-        .RST    (1'b0)
-    );
-
-    // -------------------------------------------------------------------------
-    // Generated clocks for controller
-    // Need to create this IP in Vivado:
-    //  input : 200 MHz
-    //  output0: 130 MHz
-    //  output1: 65 MHz
-    // -------------------------------------------------------------------------
-    wire dac_clk;
-    wire adc_clk;
-    wire clk_wiz_locked;
-
-    clk_wiz_ctrl_inst clk_wiz_ctrl_inst (
-        .clk_in1   (sys_clk),
-        .reset    (~rst_n),
-        .clk_out1  (dac_clk),   // 130 MHz
-        .clk_out2  (adc_clk),   // 65 MHz
-        .locked    (clk_wiz_locked)
-    );
-
-    // -------------------------------------------------------------------------
-    // GMII <-> RGMII conversion
-    // -------------------------------------------------------------------------
-    util_gmii_to_rgmii util_gmii_to_rgmii_m0 (
-        .reset           (1'b0),
-        .rgmii_td        (rgmii_txd),
-        .rgmii_tx_ctl    (rgmii_txctl),
-        .rgmii_txc       (rgmii_txc),
-        .rgmii_rd        (rgmii_rxd),
-        .rgmii_rx_ctl    (rgmii_rxctl),
-        .gmii_rx_clk     (gmii_rx_clk),
-        .gmii_txd        (e_txd),
-        .gmii_tx_en      (e_tx_en),
-        .gmii_tx_er      (1'b0),
-        .gmii_tx_clk     (gmii_tx_clk),
-        .gmii_crs        (gmii_crs),
-        .gmii_col        (gmii_col),
-        .gmii_rxd        (gmii_rxd_i),
-        .rgmii_rxc       (rgmii_rxc),
-        .gmii_rx_dv      (gmii_rx_dv),
-        .gmii_rx_er      (gmii_rx_er),
-        .speed_selection (2'b10),
-        .duplex_mode     (duplex_mode)
-    );
-
-    // -------------------------------------------------------------------------
-    // GMII arbitration / adaptation
-    // -------------------------------------------------------------------------
-    gmii_arbi arbi_inst (
-        .clk            (gmii_tx_clk),
-        .rst_n          (rst_n),
-        .speed          (2'b10),
-        .link           (1'b1),
-        .pack_total_len (pack_total_len),
-        .e_rst_n        (e_rst_n),
-        .gmii_rx_dv     (gmii_rx_dv),
-        .gmii_rxd       (gmii_rxd_i),
-        .gmii_tx_en     (gmii_tx_en),
-        .gmii_txd       (gmii_txd),
-        .e_rx_dv        (e_rx_dv),
-        .e_rxd          (e_rxd),
-        .e_tx_en        (e_tx_en),
-        .e_txd          (e_txd)
-    );
-
-    // -------------------------------------------------------------------------
-    // axis_mac interface
-    // RX stream from Ethernet goes into controller
-    // TX stream is unused for now
-    // -------------------------------------------------------------------------
-    wire        req_ready;
-
-    reg         send_req;
-    reg  [15:0] data_length;
-
-    reg  [7:0]  s_axis_tx_tdata;
-    reg         s_axis_tx_tvalid;
-    wire        s_axis_tx_tready;
-    reg         s_axis_tx_tlast;
-
-    (* MARK_DEBUG="true" *) wire [7:0]  m_axis_rx_tdata;
-    (* MARK_DEBUG="true" *) wire        m_axis_rx_tvalid;
-    (* MARK_DEBUG="true" *) wire        m_axis_rx_tlast;
-    (* MARK_DEBUG="true" *) wire        m_axis_rx_tready;
-
-    // Always ready to accept RX payload bytes
-    assign m_axis_rx_tready = 1'b1;
-
-    // TX disabled
-    always @(*) begin
-        send_req        = 1'b0;
-        data_length     = 16'd0;
-        s_axis_tx_tdata = 8'd0;
-        s_axis_tx_tvalid= 1'b0;
-        s_axis_tx_tlast = 1'b0;
-    end
-
-    axis_mac axis_mac0 (
-        .gmii_tx_clk       (gmii_tx_clk),
-        .gmii_rx_clk       (gmii_rx_clk),
-        .rst_n             (e_rst_n),
-
-        .gmii_rx_dv        (e_rx_dv),
-        .gmii_rxd          (e_rxd),
-        .gmii_tx_en        (gmii_tx_en),
-        .gmii_txd          (gmii_txd),
-
-        .send_req          (send_req),
-        .data_length       (data_length),
-        .req_ready         (req_ready),
-
-        .s_axis_tx_tdata   (s_axis_tx_tdata),
-        .s_axis_tx_tvalid  (s_axis_tx_tvalid),
-        .s_axis_tx_tready  (s_axis_tx_tready),
-        .s_axis_tx_tlast   (s_axis_tx_tlast),
-
-        .m_axis_rx_tdata   (m_axis_rx_tdata),
-        .m_axis_rx_tvalid  (m_axis_rx_tvalid),
-        .m_axis_rx_tready  (m_axis_rx_tready),
-        .m_axis_rx_tlast   (m_axis_rx_tlast)
-    );
-
-    // PHY reset helper from your original example
-    reset reset_m0 (
-        .clk   (sys_clk),
-        .key1  (rst_n),
-        .rst_n (e_reset)
-    );
-
-    // MDIO lines are not driven here yet
-    assign e_mdc  = 1'b0;
-    assign e_mdio = 1'bz;
-
-    // -------------------------------------------------------------------------
-    // Controller reset
-    // Use both external reset and clk_wiz lock
-    // -------------------------------------------------------------------------
-    wire ctrl_rst_n = rst_n & clk_wiz_locked;
-
-    // -------------------------------------------------------------------------
-    // Debug finish generator (still used here, since generator doesn't have finish signal)
-    //
-    // After each adc_start pulse generates one finish pulse after some delay.
-    // This is just for first bring-up so the controller can leave busy state
-    // If you don't want this, replace with:
-    // wire finish_dbg = 1'b0;
-    // -------------------------------------------------------------------------
-    (* MARK_DEBUG="true" *) logic        finish_dbg;
-    (* MARK_DEBUG="true" *) logic [7:0]  finish_cnt;
-    (* MARK_DEBUG="true" *) logic        finish_pending;
-
-    // Controller outputs to debug
-    (* MARK_DEBUG="true" *) wire [31:0]               dac_pulse_width;
-    (* MARK_DEBUG="true" *) wire [31:0]               dac_pulse_period;
-    (* MARK_DEBUG="true" *) wire [DAC_DATA_WIDTH-1:0] dac_pulse_height;
-    (* MARK_DEBUG="true" *) wire [15:0]               dac_pulse_num;
-
-    (* MARK_DEBUG="true" *) wire [31:0]               adc_pulse_period_dbg;
-    (* MARK_DEBUG="true" *) wire [15:0]               adc_pulse_num_dbg;
-
-    (* MARK_DEBUG="true" *) wire                      dac_start;
-    (* MARK_DEBUG="true" *) wire                      adc_start_dbg;
-    (* MARK_DEBUG="true" *) wire                      dac_rst;
-    (* MARK_DEBUG="true" *) wire                      adc_rst_dbg;
-
-    always_ff @(posedge adc_clk or negedge ctrl_rst_n) begin
-        if (!ctrl_rst_n) begin
-            finish_dbg     <= 1'b0;
-            finish_cnt     <= 8'd0;
-            finish_pending <= 1'b0;
-        end else begin
-            finish_dbg <= 1'b0;
-
-            if (adc_start_dbg) begin
-                finish_pending <= 1'b1;
-                finish_cnt     <= 8'd80;
-            end else if (finish_pending) begin
-                if (finish_cnt == 8'd0) begin
-                    finish_dbg     <= 1'b1;
-                    finish_pending <= 1'b0;
-                end else begin
-                    finish_cnt <= finish_cnt - 8'd1;
-                end
-            end
-        end
-    end
-
-    // -------------------------------------------------------------------------
-    // Controller
-    // ETH domain = gmii_rx_clk, because RX AXI master comes from axis_mac RX side
-    // -------------------------------------------------------------------------
-    control #(
-        .DAC_DATA_WIDTH(DAC_DATA_WIDTH)
-    ) udp_ctrl_inst (
-        .eth_clk_in        (gmii_rx_clk),
-        .dac_clk_in        (dac_clk),
-        .adc_clk_in        (adc_clk),
-        .rst_n             (ctrl_rst_n),
-
-        .s_axis_tdata      (m_axis_rx_tdata),
-        .s_axis_tvalid     (m_axis_rx_tvalid),
-        .s_axis_tready     (), // controller internally always ready in current version
-        .s_axis_tlast      (m_axis_rx_tlast),
-
-        .finish            (finish_dbg),
-
-        .dac_pulse_width   (dac_pulse_width),
-        .dac_pulse_period  (dac_pulse_period),
-        .dac_pulse_height  (dac_pulse_height),
-        .dac_pulse_num     (dac_pulse_num),
-
-        .adc_pulse_period  (adc_pulse_period_dbg),
-        .adc_pulse_num     (adc_pulse_num_dbg),
-
-        .dac_start         (dac_start),
-        .adc_start         (adc_start_dbg),
-
-        .dac_rst           (dac_rst),
-        .adc_rst           (adc_rst_dbg)
-    );
-
-    // -------------------------------------------------------------------------
-    // DAC
-    // -------------------------------------------------------------------------
-    generator #(
-        .DATA_WIDTH(DAC_DATA_WIDTH)
-    ) generator_inst (
-        .clk_in(dac_clk),
-        .rst(dac_rst),
-        .start(dac_start),
-        .pulse_width(dac_pulse_width),
-        .pulse_period(dac_pulse_period),
-        .pulse_height(dac_pulse_height),
-        .pulse_num(dac_pulse_num),
-        .pulse(p2_wrt ),
-        .pulse_height_out(p2_data)
-    );
-
-    // dac clk mgt
-    wire p2_clk_oddr;
-
-    ODDR #(
-        .DDR_CLK_EDGE("SAME_EDGE"),
-        .INIT(1'b0),
-        .SRTYPE("SYNC")
-    ) ODDR_p2_clk (
-        .Q (p2_clk_oddr),
-        .C (dac_clk),
-        .CE(1'b1),
-        .D1(1'b1),
-        .D2(1'b0),
-        .R (1'b0),
-        .S (1'b0)
-    );
-
-    OBUF OBUF_p2_clk (
-        .I(p2_clk_oddr),
-        .O(p2_clk)
-    );
-    
-    //assign p2_wrt = p2_clk;
-
-    // -------------------------------------------------------------------------
-    // Simple LED status
-    // -------------------------------------------------------------------------
-    assign led[0] = clk_wiz_locked;
-    assign led[1] = m_axis_rx_tvalid;
-    assign led[2] = dac_start;
-    assign led[3] = adc_rst_dbg;
-
-endmodule

designs/eth_generator/ip/clk_wiz_ctrl_inst.xci

@@ -1,689 +0,0 @@
-{
-  "schema": "xilinx.com:schema:json_instance:1.0",
-  "ip_inst": {
-    "xci_name": "clk_wiz_ctrl_inst",
-    "component_reference": "xilinx.com:ip:clk_wiz:6.0",
-    "ip_revision": "16",
-    "gen_directory": "../../../../eth_generator_top.gen/sources_1/ip/clk_wiz_ctrl_inst",
-    "parameters": {
-      "component_parameters": {
-        "Component_Name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "user", "usage": "all" } ],
-        "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
-        "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
-        "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
-        "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
-        "PRIM_IN_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
-        "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
-        "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
-        "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
-        "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
-        "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
-        "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
-        "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKIN1_JITTER_PS": [ { "value": "50.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "NUM_OUT_CLKS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
-        "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
-        "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
-        "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
-        "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
-        "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
-        "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
-        "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
-        "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
-        "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
-        "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
-        "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
-        "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
-        "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
-        "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
-        "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
-        "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
-        "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
-        "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
-        "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
-        "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
-        "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
-        "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
-        "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
-        "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
-        "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
-        "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
-        "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
-        "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
-        "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
-        "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
-        "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
-        "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
-        "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
-        "MMCM_DIVCLK_DIVIDE": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
-        "MMCM_CLKFBOUT_MULT_F": [ { "value": "16.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
-        "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "6.750", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKOUT1_DIVIDE": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
-        "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
-        "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
-        "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
-        "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
-        "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
-        "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
-        "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
-        "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
-        "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
-        "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
-        "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
-        "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
-        "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT1_JITTER": [ { "value": "162.582", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT1_PHASE_ERROR": [ { "value": "137.238", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT2_JITTER": [ { "value": "185.296", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT2_PHASE_ERROR": [ { "value": "137.238", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
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-        "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
-        "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
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-            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
-            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
-          },
-          "port_maps": {
-            "CLK_OUT1": [ { "physical_name": "clk_out1" } ]
-          }
-        },
-        "clock_CLK_OUT2": {
-          "vlnv": "xilinx.com:signal:clock:1.0",
-          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
-          "mode": "master",
-          "parameters": {
-            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
-            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
-          },
-          "port_maps": {
-            "CLK_OUT2": [ { "physical_name": "clk_out2" } ]
-          }
-        }
-      }
-    }
-  }
-}

designs/reflectometer_base/Makefile

@@ -17,6 +17,7 @@ RTL_DIR = ../../rtl
 include ../../scripts/vivado.mk
 
 SYN_FILES += reflectometer.sv
+SYN_FILES += tb_reflectometer.sv
 SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
 
 XCI_FILES = $(sort $(shell find ../../rtl/ethernet-udp/src -type f -name '*.xci'))

designs/reflectometer_base/README.md

@@ -0,0 +1,145 @@
+# Рефлектометр
+
+Модуль представляет собой законченную встраиваемую систему рефлектометра, объединяющую:
+
+- контроллер управления
+- генератор импульсов (DAC path)
+- сэмплер данных (ADC path)
+- аккумулятор и обработчик данных
+
+Система предназначена для формирования импульсов, синхронного сбора отраженного сигнала, накопления результатов и передачи обработанных данных во внешнюю систему.
+
+Данный модуль является полноценным интегрируемым блоком, который может использоваться как самостоятельная аппаратная подсистема внутри более крупного проекта.
+
+---
+
+## Назначение системы
+
+Основная задача системы:
+
+1. Получить параметры измерения через AXI Stream
+2. Сформировать последовательность импульсов на DAC
+3. Выполнить синходную выборку данных с ADC
+4. Накопить и обработать результаты
+5. Передать итоговые данные обратно через AXI Stream
+
+Таким образом реализуется полный цикл измерения без необходимости внешнего управления отдельными блоками.
+
+---
+
+## Состав системы
+
+### Controller
+
+Принимает входные команды по AXI Stream (Ethernet RX), декодирует параметры измерения и управляет всеми внутренними модулями системы.
+
+Формирует:
+
+- запуск генератора (`dac_start`)
+- запуск аккумулятора (`adc_start`)
+- параметры импульсов DAC
+- параметры выборки ADC
+- локальные reset-сигналы
+
+---
+
+### Generator
+
+Формирует последовательность импульсов на DAC с заданными:
+
+- амплитудой
+- длительностью
+- периодом
+- количеством повторений
+
+Для каждого импульса инициирует запуск выборки в сэмплере.
+
+---
+
+### Sampler
+
+Выполняет синхронный сбор данных с ADC по запросу генератора.
+
+Поддерживает:
+
+- фильтрацию `out_of_range`
+- упаковку данных
+- преобразование типа кода ( прямой или дополнительный)
+
+---
+
+### Accumulator
+
+Получает поток данных от сэмплера, выполняет накопление, усреднение и оконную обработку, после чего формирует пакеты для передачи результата.
+
+---
+
+## Управление системой
+
+Пользователь взаимодействует только с контроллером через AXI Stream-интерфейс.
+
+Прямое управление генератором, сэмплером и аккумулятором не требуется.
+
+---
+
+## Clock Domain Crossing (CDC)
+
+Система работает в нескольких тактовых доменах:
+
+- Ethernet RX (`gmii_rx_clk`)
+- Ethernet TX (`gmii_tx_clk`)
+- DAC (`dac_clk`)
+- ADC (`adc_clk`)
+
+Для корректной синхронизации между DAC и ADC используются специальные CDC-регистры для сигналов:
+
+- `sample_req`
+- `sample_done`
+
+Это обеспечивает безопасную передачу handshake-сигналов между тактовыми доменами.
+
+---
+
+## Список параметров
+
+### DAC_DATA_WIDTH
+Ширина выходных данных отправляемых на ЦАП.
+
+### ZERO_LEVEL
+Уровень сигнала в состоянии отсутствия импульса (базовый уровень сигнала).
+
+Типовые значения:
+
+- `8192` — середина диапазона ЦАП
+- `0` — нулевой уровень
+
+### ADC_DATA_WIDTH
+Ширина входных данных, получаемых с АЦП.
+
+### PACK_FACTOR
+Количество отсчетов, собираемых в один выходной пакет.
+
+### PROCESS_MODE
+Режим интерпретации входного кода:
+
+- `0` — прямой код
+- `1` — дополнительный код
+
+### ACCUM_WIDTH 
+Размер данных для аккумуляции, должен быть степенью числа 2. По умолчанию - 32
+
+### N_MAX 
+Максимальное число окон в последовательности. Должно быть степенью числа 2. Влияет на размер используемой памяти.
+
+### WINDOW_SIZE 
+Размер окна усреднения
+
+### PACKET_SIZE 
+Размер выходного пакета
+
+---
+
+## Сборка
+```make all``` - собрать все до битстрима
+
+```make vivado``` - открыть проект в Vivado

designs/reflectometer_base/reflectometer.sv

@@ -5,6 +5,7 @@ module reflectometer_top #(
     parameter int unsigned ADC_DATA_WIDTH = 12,
     parameter PACK_FACTOR = 1,
     parameter PROCESS_MODE = 0,
+    parameter ZERO_LEVEL = 8192,
     parameter ACCUM_WIDTH = 32,
     parameter N_MAX = 4096,
     parameter WINDOW_SIZE = 65,
@@ -191,7 +192,8 @@ module reflectometer_top #(
     //------------------------------------------------------------
 
     generator #(
-        .DATA_WIDTH(DAC_DATA_WIDTH)
+        .DATA_WIDTH(DAC_DATA_WIDTH),
+        .ZERO_LEVEL(ZERO_LEVEL)
     ) generator_inst (
         .clk_in(dac_clk),
         .rst(dac_rst),

designs/reflectometer_base/tb_reflectometer.sv

@@ -0,0 +1,267 @@
+`timescale 1ns / 1ps
+
+module tb_reflectometer;
+
+    // parameters
+    localparam int unsigned DAC_DATA_WIDTH = 14;
+    localparam int unsigned ADC_DATA_WIDTH = 12;
+    localparam PACK_FACTOR = 1;     // not used in TB
+    localparam PROCESS_MODE = 0;    // 0 - uint, 1 - int
+    localparam ZERO_LEVEL = 8192;   // DAC zero voltage representation (2^14 / 2)
+    localparam ACCUM_WIDTH = 32;    // accumulator number bit witdth
+    localparam N_MAX = 4096;        // max value of windows to average by experiments
+    localparam WINDOW_SIZE = 65;    // fixed subwindow size to average by time
+    localparam PACKET_SIZE = 1024;  // bytes per UDP packet
+
+    localparam int unsigned ADC_CLK_MHZ = 65;
+    localparam int unsigned DAC_CLK_MHZ = 125;
+
+    // may be changed for test purposes
+    localparam int unsigned PULSE_WIDTH = 2**6;
+    localparam int unsigned PULSE_PERIOD = 2**8;
+    localparam int unsigned PULSE_NUM = 10;
+    localparam int unsigned PULSE_HEIGHT = 2**12;
+    localparam int unsigned PULSE_PERIOD_ADC = (int'(real'(ADC_CLK_MHZ) / real'(DAC_CLK_MHZ) * real'(PULSE_PERIOD)) / int'(WINDOW_SIZE)) * int'(WINDOW_SIZE);
+    
+    initial begin
+        if (PULSE_WIDTH <= 0)
+            $fatal(1, "PULSE_WIDTH should be positive");
+        if (PULSE_PERIOD <= 0)
+            $fatal(1, "PULSE_PERIOD should be positive");
+        if (PULSE_NUM <= 0)
+            $fatal(1, "PULSE_NUM should be positive");
+        if (PULSE_HEIGHT <= 0)
+            $fatal(1, "PULSE_HEIGHT should be positive");
+        if (PULSE_WIDTH >= 2**32-1)
+            $fatal(1, "PULSE_WIDTH too high");
+        if (PULSE_PERIOD >= 2**32-1)
+            $fatal(1, "PULSE_PERIOD too high");
+        if (PULSE_NUM >= 2**16-1)
+            $fatal(1, "PULSE_NUM too high");
+        if (PULSE_HEIGHT >= 2**DAC_DATA_WIDTH-1)
+            $fatal(1, "PULSE_HEIGHT too high");
+        if (PULSE_PERIOD_ADC % WINDOW_SIZE == 0)
+            $fatal(1, "PULSE_PERIOD_ADC isn't multiple of WINDOW_SIZE");
+    end
+
+    // DUT signals
+    logic clk200, clk_eth_phy_tx, clk_eth_phy_rx; // GMII clocks
+    logic rst_n;
+    wire [3:0] status_leds; // [ None, dac_start, m_axis_valid, clk_wiz_locked ]
+
+    wire dac_clk, dac_en;
+    wire [DAC_DATA_WIDTH-1:0] dac_data;
+    wire adc_clk;
+    logic adc_otr;
+    logic [ADC_DATA_WIDTH-1:0] adc_data;
+
+    wire [7:0]   s_axis_tx_tdata;
+    wire         s_axis_tx_tvalid;
+    logic        s_axis_tx_tready;
+    wire         s_axis_tx_tlast;
+    
+    logic        phy_ready;
+    wire         accum_tx_start;
+    logic [7:0]  m_axis_rx_tdata;
+    logic        m_axis_rx_tvalid;
+    logic        m_axis_rx_tlast;
+    logic        m_axis_rx_tready;
+
+    logic [127:0] dut_config = 0;
+
+    // DUT
+    reflectometer_top #(
+        .DAC_DATA_WIDTH(DAC_DATA_WIDTH),
+        .ADC_DATA_WIDTH(ADC_DATA_WIDTH),
+        .PACK_FACTOR(PACK_FACTOR),
+        .PROCESS_MODE(PROCESS_MODE),
+        .ZERO_LEVEL(ZERO_LEVEL),
+        .ACCUM_WIDTH(ACCUM_WIDTH),
+        .N_MAX(N_MAX),
+        .WINDOW_SIZE(WINDOW_SIZE),
+        .PACKET_SIZE(PACKET_SIZE)
+    ) DUT (
+        .sys_clk(clk200),                  // main clk 200 mhz
+        .rst_n(rst_n),                     // rst_n
+        .led(status_leds),                 // indication [3:0]
+        .gmii_rx_clk(clk_eth_phy_rx),      // ext. clk from PHY
+        .gmii_tx_clk(clk_eth_phy_tx),      // ext. clk from PHY
+        // accumulated data stream
+        .s_axis_tx_tdata(s_axis_tx_tdata),  
+        .s_axis_tx_tvalid(s_axis_tx_tvalid), 
+        .s_axis_tx_tready(s_axis_tx_tready), 
+        .s_axis_tx_tlast(s_axis_tx_tlast),  
+        // controller data stream
+        .m_axis_rx_tdata(m_axis_rx_tdata), 
+        .m_axis_rx_tvalid(m_axis_rx_tvalid), 
+        .m_axis_rx_tlast(m_axis_rx_tlast),  
+        .m_axis_rx_tready(m_axis_rx_tready), 
+        
+        .req_ready(phy_ready),        // AXI-stream requester ready
+        .send_req(accum_tx_start),         // AXI-stream start transmit
+        .p2_clk(dac_clk),           // DAC clk
+        .p2_data(dac_data),          // DAC [DAC_DATA_WIDTH-1:0] data
+        .p2_wrt(dac_en),           // DAC write enable
+        .ch2_clk(adc_clk),          // ADC clk
+        .ch2_data(adc_data),         // ADC [ADC_DATA_WIDTH-1:0] data
+        .ch2_otr(adc_otr)           // ADC signal out-of-range
+    );
+
+    // clocks
+    initial begin
+        // 200 MHz    
+        clk200 = 1'b0;
+        forever #2.5 clk200 = ~clk200;
+    end
+    initial begin
+        // 125 MHz
+        clk_eth_phy_tx = 1'b0;
+        forever #4 clk_eth_phy_tx = ~clk_eth_phy_tx;
+    end
+    initial begin
+        // 125 MHz
+        clk_eth_phy_rx = 1'b0;
+        forever #4 clk_eth_phy_rx = ~clk_eth_phy_rx;
+    end
+
+    // ADC input noise simulation
+    always @(posedge adc_clk or negedge rst_n) begin
+        if (!rst_n) begin
+            adc_data <= '0; 
+        end else begin
+            adc_data <= $urandom() & ((1 << ADC_DATA_WIDTH) - 1);
+        end
+    end
+    assign adc_otr = 1'b0;
+
+    // AXIS tasks
+    task automatic axis_send_byte(
+        ref  logic       clk,
+        input  logic [7:0] data,
+        input  logic       last,
+        ref    logic       tvalid,
+        ref    logic [7:0] tdata,
+        ref    logic       tlast,
+        input  logic       tready
+    );
+        @(posedge clk);
+        tdata  <= data;
+        tlast  <= last;
+        tvalid <= 1'b1;
+
+        // Ждем готовности приемника
+        wait(tready === 1'b1);
+
+        @(posedge clk);
+        tvalid <= 1'b0;
+        tlast  <= 1'b0;
+    endtask
+
+    task automatic dut_soft_reset();
+        axis_send_byte(
+            .clk(clk_eth_phy_rx),
+            .data(8'b00001111),
+            .last(1'b1),
+            .tvalid(m_axis_rx_tvalid),
+            .tdata(m_axis_rx_tdata),
+            .tlast(m_axis_rx_tlast),
+            .tready(m_axis_rx_tready)
+        );
+    endtask
+
+    task automatic dut_start();
+        axis_send_byte(
+            .clk(clk_eth_phy_rx),
+            .data(8'b11110000),
+            .last(1'b1),
+            .tvalid(m_axis_rx_tvalid),
+            .tdata(m_axis_rx_tdata),
+            .tlast(m_axis_rx_tlast),
+            .tready(m_axis_rx_tready)
+        );
+    endtask
+
+//    task automatic dut_send_config(
+//        input logic [127:0] ctrl_config
+//    );
+//        // команда set_data
+//        axis_send_byte(
+//            .clk(clk_eth_phy_rx),
+//            .data(8'b10001000),
+//            .last(1'b0),
+//            .tvalid(m_axis_rx_tvalid),
+//            .tdata(m_axis_rx_tdata),
+//            .tlast(m_axis_rx_tlast),
+//            .tready(m_axis_rx_tready)
+//        );
+//        // config burst
+//        for (int i = 0; i < 16; i++) begin
+//            logic [7:0] byte_to_send;
+//            logic       is_last;
+
+//            // get byte
+//            byte_to_send = ctrl_config[i*8 +: 8];
+//            // tlast for last byte
+//            is_last = (i == 15);
+
+//            axis_send_byte(
+//                .clk(clk_eth_phy_rx),
+//                .data(byte_to_send),
+//                .last(is_last),
+//                .tvalid(m_axis_rx_tvalid),
+//                .tdata(m_axis_rx_tdata),
+//                .tlast(m_axis_rx_tlast),
+//                .tready(m_axis_rx_tready)
+//            );
+//        end
+//    endtask
+
+
+
+    // some helpers for controller axis
+    
+    // GAME PLAN
+    // 1. setup reflectometer
+    // 2. create some reference signal with noise + virtual ADC
+    // 3. setup m_axis endpoint for controller to start reflectometer (create multiple tasks)
+    // 4. setup s_axis endpoint for data gathering and plotting
+    // 5. check standalone reflectometer
+    // 6. add reference signal averaging loop throw generator pulse posedge detection
+    // 7. visual comparision of reference VS reflectometer
+    // 8. add statistics for signal comparision (MSE/RMSE)  
+    
+    // main TB
+    initial begin
+        // setup
+        rst_n = 1'b0;
+        s_axis_tx_tready = 1'b0;
+        m_axis_rx_tdata = 1'b0;
+        m_axis_rx_tvalid = 1'b0;
+        m_axis_rx_tlast = 1'b0;
+        phy_ready = 1'b0;
+        
+        // startup
+        #100;
+        rst_n = 1'b1;
+        wait(DUT.clk_wiz_ctrl_inst.locked == 1'b1);
+        #20;
+        $display("=== clocks ready / wiz. locked ===");
+        #40;
+        // ready to work
+        
+        dut_config[31:0]                    = PULSE_WIDTH;
+        dut_config[63:32]                   = PULSE_PERIOD;
+        dut_config[79:64]                   = PULSE_NUM;
+        dut_config[79+DAC_DATA_WIDTH:80]    = PULSE_HEIGHT;
+        dut_config[127:96]                  = PULSE_PERIOD_ADC;
+        
+//       dut_send_config(dut_config);
+        dut_start();
+        // dut_start();
+        #1000;
+        // dut_soft_reset();
+
+        $display("=== ALL BASIC TESTS PASSED ===");
+        $finish;
+    end
+endmodule

designs/reflectometer_prototype/README.md

@@ -1,11 +1,13 @@
-# Тестовый проект Generator + ETH + CTRL
+# Тестовый проект рефлектометра
-Проект состоит из AXIS Ethernet, контроллера и генератора. Позволяет генерировать сигналы, задав параметры через Ethernet.
+Проект состоит из AXIS Ethernet и основной части рефлектометра - генератора, сэмплера, контроллера и синхронизирующей логики. Разработан для AX7102, АЦП AN9238, ЦАП AD9767. Плата подключается по ethernet к компьютеру, IP должен быть 192.168.0.3 у компьютера, в ПЛИС установлен IP 192.168.0.2, после подключения должен пройти ARP и после этого можно начнить коммуникацию через консольку.
 ## Сборка
 ```make all``` - собрать все до битстрима
 
 ```make vivado``` - открыть проект в Vivado
 
 ## Управление
-Используйте software/console.py. Пример:
+Используйте software/console.py. Примеры:
 
-```python3 console.py --pulse_width 3_500_000 --pulse_period 20_000_000 --pulse_height 10000 --pulse_num 5500 --dac-bits 14```
+```python3 console.py --pulse_width 3500 --pulse_period 20000 --pulse_height 15000 --pulse_num 550 --dac-bits 14```
+
+```python3 console.py --pulse_width 15000 --pulse_period 20000 --pulse_height 1500 --pulse_num 550 --dac-bits 14```

designs/reflectometer_prototype/prototype.sv

@@ -5,6 +5,7 @@ module prototype_top #(
     parameter int unsigned ADC_DATA_WIDTH = 12,
     parameter PACK_FACTOR = 1,
     parameter PROCESS_MODE = 0,
+    parameter ZERO_LEVEL = 8192,
     parameter ACCUM_WIDTH = 32,
     parameter N_MAX = 4096,
     parameter WINDOW_SIZE = 65,
@@ -131,6 +132,7 @@ module prototype_top #(
         .PACK_FACTOR(PACK_FACTOR),
         .ACCUM_WIDTH(ACCUM_WIDTH),
         .N_MAX(N_MAX),
+        .ZERO_LEVEL(ZERO_LEVEL),
         .WINDOW_SIZE(WINDOW_SIZE),
         .PACKET_SIZE(PACKET_SIZE),
         .ADC_DATA_WIDTH(ADC_DATA_WIDTH),

docs/sampler.md

@@ -1 +0,0 @@
-# Блок Sampler

rtl/accum/tests/tb_accumulator_top_behav.wcfg

@@ -11,13 +11,13 @@
       </db_ref>
    </db_ref_list>
    <zoom_setting>
-      <ZoomStartTime time="0.000000 us"></ZoomStartTime>
+      <ZoomStartTime time="2,748,541.000 ns"></ZoomStartTime>
-      <ZoomEndTime time="16.740001 us"></ZoomEndTime>
+      <ZoomEndTime time="2,749,382.001 ns"></ZoomEndTime>
-      <Cursor1Time time="6.500000 us"></Cursor1Time>
+      <Cursor1Time time="2,749,045.000 ns"></Cursor1Time>
    </zoom_setting>
    <column_width_setting>
       <NameColumnWidth column_width="556"></NameColumnWidth>
-      <ValueColumnWidth column_width="111"></ValueColumnWidth>
+      <ValueColumnWidth column_width="107"></ValueColumnWidth>
    </column_width_setting>
    <WVObjectSize size="18" />
    <wvobject type="logic" fp_name="/tb_accumulator_top/clk_in">
@@ -116,6 +116,10 @@
          <obj_property name="ElementShortName">addrb[15:0]</obj_property>
          <obj_property name="ObjectShortName">addrb[15:0]</obj_property>
       </wvobject>
+      <wvobject type="array" fp_name="/tb_accumulator_top/dut/accum_main/wr_state">
+         <obj_property name="ElementShortName">wr_state[3:0]</obj_property>
+         <obj_property name="ObjectShortName">wr_state[3:0]</obj_property>
+      </wvobject>
    </wvobject>
    <wvobject type="group" fp_name="group27">
       <obj_property name="label">fifo</obj_property>
@@ -166,13 +170,13 @@
          <obj_property name="ObjectShortName">PROG_FULL_THRESH[31:0]</obj_property>
       </wvobject>
       <wvobject type="array" fp_name="/tb_accumulator_top/dut/output_async_fifo/xpm_fifo_async_inst/wr_data_count">
-         <obj_property name="ElementShortName">wr_data_count[4:0]</obj_property>
+         <obj_property name="ElementShortName">wr_data_count[9:0]</obj_property>
-         <obj_property name="ObjectShortName">wr_data_count[4:0]</obj_property>
+         <obj_property name="ObjectShortName">wr_data_count[9:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
       <wvobject type="array" fp_name="/tb_accumulator_top/dut/output_async_fifo/xpm_fifo_async_inst/rd_data_count">
-         <obj_property name="ElementShortName">rd_data_count[6:0]</obj_property>
+         <obj_property name="ElementShortName">rd_data_count[11:0]</obj_property>
-         <obj_property name="ObjectShortName">rd_data_count[6:0]</obj_property>
+         <obj_property name="ObjectShortName">rd_data_count[11:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
    </wvobject>

rtl/controller/README.md

@@ -41,14 +41,15 @@
 
 *start* отправляет пульс start на dac_start и adc_start в их доменах. при этом после этого блок перестает быть ready и ждет, пока не придет пульс finish, после этого он возвращается снова в *idle* состояние
 
-*set_data* значит, что следующие 96 бит = 12*8 байт, пришедшии по axis - это конфигурационная информация и ее нужно записать в внутренний регистр на 96 бит.
+*set_data* значит, что следующие 128 бит = 16*8 байт, пришедшии по axis - это конфигурационная информация и ее нужно записать в внутренний регистр на 128 бит.
 
-конфигурационный регистр на 96 бит делится так:
+конфигурационный регистр на 128 бит делится так:
 ```
 reg[31:0] - pulse_width
 reg[63:32] - pulse_period
 reg[79:64] - pulse_num
 reg[79+dac_data_width:80] - pulse_height
+reg[127:96] - pulse_period_adc
 ```
 
 соотвественно эти записанные значения выставляются на соотвествующие выходные сигналы в доменах dac_clk и adc_clk. выходы обновляются каждый раз, когда происходит set_data, и сигналы сохраняют своё значение до следующего set_data.

rtl/controller/tests/tb_control_behav.wcfg

@@ -0,0 +1,197 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="tb_control_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="tb_control" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="0.676 ns"></ZoomStartTime>
+      <ZoomEndTime time="645.677 ns"></ZoomEndTime>
+      <Cursor1Time time="349.676 ns"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="558"></NameColumnWidth>
+      <ValueColumnWidth column_width="61"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="23" />
+   <wvobject type="logic" fp_name="/tb_control/eth_clk_in">
+      <obj_property name="ElementShortName">eth_clk_in</obj_property>
+      <obj_property name="ObjectShortName">eth_clk_in</obj_property>
+      <obj_property name="CustomSignalColor">#008080</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_control/dac_clk_in">
+      <obj_property name="ElementShortName">dac_clk_in</obj_property>
+      <obj_property name="ObjectShortName">dac_clk_in</obj_property>
+      <obj_property name="CustomSignalColor">#FFA500</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_control/adc_clk_in">
+      <obj_property name="ElementShortName">adc_clk_in</obj_property>
+      <obj_property name="ObjectShortName">adc_clk_in</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_control/rst_n">
+      <obj_property name="ElementShortName">rst_n</obj_property>
+      <obj_property name="ObjectShortName">rst_n</obj_property>
+      <obj_property name="CustomSignalColor">#800080</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_control/s_axis_tdata">
+      <obj_property name="ElementShortName">s_axis_tdata[7:0]</obj_property>
+      <obj_property name="ObjectShortName">s_axis_tdata[7:0]</obj_property>
+      <obj_property name="CustomSignalColor">#008080</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="Radix">BINARYRADIX</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_control/s_axis_tvalid">
+      <obj_property name="ElementShortName">s_axis_tvalid</obj_property>
+      <obj_property name="ObjectShortName">s_axis_tvalid</obj_property>
+      <obj_property name="CustomSignalColor">#008080</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_control/s_axis_tready">
+      <obj_property name="ElementShortName">s_axis_tready</obj_property>
+      <obj_property name="ObjectShortName">s_axis_tready</obj_property>
+      <obj_property name="CustomSignalColor">#008080</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_control/s_axis_tlast">
+      <obj_property name="ElementShortName">s_axis_tlast</obj_property>
+      <obj_property name="ObjectShortName">s_axis_tlast</obj_property>
+      <obj_property name="CustomSignalColor">#008080</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_control/finish">
+      <obj_property name="ElementShortName">finish</obj_property>
+      <obj_property name="ObjectShortName">finish</obj_property>
+      <obj_property name="CustomSignalColor">#FAAFBE</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_control/dac_pulse_width">
+      <obj_property name="ElementShortName">dac_pulse_width[31:0]</obj_property>
+      <obj_property name="ObjectShortName">dac_pulse_width[31:0]</obj_property>
+      <obj_property name="CustomSignalColor">#FFA500</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_control/dac_pulse_period">
+      <obj_property name="ElementShortName">dac_pulse_period[31:0]</obj_property>
+      <obj_property name="ObjectShortName">dac_pulse_period[31:0]</obj_property>
+      <obj_property name="CustomSignalColor">#FFA500</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_control/dac_pulse_height">
+      <obj_property name="ElementShortName">dac_pulse_height[11:0]</obj_property>
+      <obj_property name="ObjectShortName">dac_pulse_height[11:0]</obj_property>
+      <obj_property name="CustomSignalColor">#FFA500</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_control/dac_pulse_num">
+      <obj_property name="ElementShortName">dac_pulse_num[15:0]</obj_property>
+      <obj_property name="ObjectShortName">dac_pulse_num[15:0]</obj_property>
+      <obj_property name="CustomSignalColor">#FFA500</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_control/adc_pulse_period">
+      <obj_property name="ElementShortName">adc_pulse_period[31:0]</obj_property>
+      <obj_property name="ObjectShortName">adc_pulse_period[31:0]</obj_property>
+      <obj_property name="CustomSignalColor">#FFA500</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_control/adc_pulse_num">
+      <obj_property name="ElementShortName">adc_pulse_num[15:0]</obj_property>
+      <obj_property name="ObjectShortName">adc_pulse_num[15:0]</obj_property>
+      <obj_property name="CustomSignalColor">#FFA500</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_control/dac_start">
+      <obj_property name="ElementShortName">dac_start</obj_property>
+      <obj_property name="ObjectShortName">dac_start</obj_property>
+      <obj_property name="CustomSignalColor">#FFA500</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_control/adc_start">
+      <obj_property name="ElementShortName">adc_start</obj_property>
+      <obj_property name="ObjectShortName">adc_start</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_control/dac_rst">
+      <obj_property name="ElementShortName">dac_rst</obj_property>
+      <obj_property name="ObjectShortName">dac_rst</obj_property>
+      <obj_property name="CustomSignalColor">#FFA500</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_control/adc_rst">
+      <obj_property name="ElementShortName">adc_rst</obj_property>
+      <obj_property name="ObjectShortName">adc_rst</obj_property>
+   </wvobject>
+   <wvobject type="group" fp_name="group499">
+      <obj_property name="label">tb signals</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject type="array" fp_name="/tb_control/dac_rst_count">
+         <obj_property name="ElementShortName">dac_rst_count[31:0]</obj_property>
+         <obj_property name="ObjectShortName">dac_rst_count[31:0]</obj_property>
+         <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/tb_control/adc_rst_count">
+         <obj_property name="ElementShortName">adc_rst_count[31:0]</obj_property>
+         <obj_property name="ObjectShortName">adc_rst_count[31:0]</obj_property>
+         <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/tb_control/dac_start_count">
+         <obj_property name="ElementShortName">dac_start_count[31:0]</obj_property>
+         <obj_property name="ObjectShortName">dac_start_count[31:0]</obj_property>
+         <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/tb_control/adc_start_count">
+         <obj_property name="ElementShortName">adc_start_count[31:0]</obj_property>
+         <obj_property name="ObjectShortName">adc_start_count[31:0]</obj_property>
+         <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/tb_control/test_pulse_width">
+         <obj_property name="ElementShortName">test_pulse_width[31:0]</obj_property>
+         <obj_property name="ObjectShortName">test_pulse_width[31:0]</obj_property>
+         <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/tb_control/test_pulse_period">
+         <obj_property name="ElementShortName">test_pulse_period[31:0]</obj_property>
+         <obj_property name="ObjectShortName">test_pulse_period[31:0]</obj_property>
+         <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/tb_control/test_pulse_num">
+         <obj_property name="ElementShortName">test_pulse_num[15:0]</obj_property>
+         <obj_property name="ObjectShortName">test_pulse_num[15:0]</obj_property>
+         <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/tb_control/test_pulse_height_raw">
+         <obj_property name="ElementShortName">test_pulse_height_raw[15:0]</obj_property>
+         <obj_property name="ObjectShortName">test_pulse_height_raw[15:0]</obj_property>
+         <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_control/DAC_DATA_WIDTH">
+      <obj_property name="ElementShortName">DAC_DATA_WIDTH[31:0]</obj_property>
+      <obj_property name="ObjectShortName">DAC_DATA_WIDTH[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_control/dut/cfg_ack_toggle_adc">
+      <obj_property name="ElementShortName">cfg_ack_toggle_adc</obj_property>
+      <obj_property name="ObjectShortName">cfg_ack_toggle_adc</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_control/dut/cfg_ack_toggle_dac">
+      <obj_property name="ElementShortName">cfg_ack_toggle_dac</obj_property>
+      <obj_property name="ObjectShortName">cfg_ack_toggle_dac</obj_property>
+   </wvobject>
+</wave_config>

rtl/generator/README.md

@@ -0,0 +1,91 @@
+# Генератор
+
+Модуль выполняет задачу формирования последовательности импульсов заданной амплитуды, длительности и периода.  
+Дополнительно реализован механизм синхронизации с модулем сэмплера через сигналы `request` и `done`, позволяющий запускать сбор данных для каждого импульса и ожидать подтверждения завершения выборки перед переходом к следующему импульсу.
+
+---
+
+## Список параметров
+
+### DATA_WIDTH
+Ширина выходных данных генератора.
+
+### ZERO_LEVEL
+Уровень сигнала в состоянии отсутствия импульса (базовый уровень сигнала).
+
+Типовые значения:
+
+- `8192` — середина диапазона ЦАП
+- `0` — нулевой уровень
+
+---
+
+## Список входных портов
+
+### clk_dac
+Сигнал тактирования модуля.
+
+### rst
+Сброс модуля и остановка генерации.
+
+### start
+Сигнал запуска последовательности импульсов.
+
+При его активации модуль фиксирует все входные параметры и начинает генерацию.
+
+Повторный запуск во время активной генерации блокируется с помощью внутреннего сигнала `enable`.
+
+### [31:0] pulse_width
+Длительность активной части импульса (в тактах).
+
+### [31:0] pulse_period
+Полный период импульса (в тактах).
+
+### [DATA_WIDTH-1:0] pulse_height
+Амплитуда импульса.
+
+### [15:0] pulse_num
+Количество импульсов, которое необходимо сгенерировать.
+
+### request
+Сигнал запроса на синхронизацию от сэмплера для текущего импульса.
+
+---
+
+## Список выходных портов
+
+### dac_wrt
+Выходной сигнал разрешения записи сигнала 
+
+### [DATA_WIDTH-1:0] dac_out
+Выходное значение амплитуды сигнала.
+
+Во время активной части импульса равно `pulse_height`, вне импульса — `ZERO_LEVEL`.
+
+### done
+Сигнал запроса на запуск синхронизации с сэмплером для текущего импульса.
+
+Поднимается в начале каждого нового импульса и снимается после получения `request`.
+
+---
+
+## Логика работы
+
+После прихода сигнала `start` модуль:
+
+- фиксирует входные параметры генерации
+- поднимает `enable = 1`
+- выполняет `pulse_num` циклов работы
+- - типичный цикл состоит в ожидании синхронизации (`synced`), после чего запуск генерации импульса
+
+Синхронизация представляет из себя простое рукопожатие с внешним модулем, имеющим сигналы `request`/`done` работающими в соответствии с этими сигналами генератора. Один из модулей, входит в ожидание и ставит на свой done активный уровень, после чего ждет, пока второй, запаздывающий модуль не войдет в свой режим ожидания, и не выставит для своего done активный уровень. Для каждого из модулей, на следующий такт после выставления активного уровня, производится проверка своего request. Так, при получении активного request (иными словами активного done от внешнего модуля), модуль незамедлительно опускает уровень своего done и начинает работать. Done подымается до активного уровня хотя-бы на один такт работы соответствующего модуля.
+
+---
+
+## Симуляция
+Тесты запускаются автоматически через make.
+```
+cd tests
+make sim
+```
+При успешном завершении теста высвечивается "ALL PASSED".

rtl/generator/src/generator.sv

@@ -1,103 +1,95 @@
 `timescale 1ns / 1ps
 
-
 module generator
 #(
-    parameter DATA_WIDTH = 14
+    parameter DATA_WIDTH = 14,
-    )
+    parameter ZERO_LEVEL = 8192 // 8192 or 0
+)
 (
-    input clk_in,
+    input clk_dac,
     input rst,
     input start,
     input [31:0]           pulse_width,
     input [31:0]           pulse_period,
     input [DATA_WIDTH-1:0] pulse_height,
     input [15:0]           pulse_num,
-    input sample_done,
+    input request,
     
-    output pulse,
+    output dac_wrt,
-    output[DATA_WIDTH-1:0] pulse_height_out,
+    output logic [DATA_WIDTH-1:0] dac_out,
-    output logic sample_req
+    output logic done
+);
+    logic [DATA_WIDTH-1:0] pulse_height_reg;
+    logic [31:0] pulse_width_reg, pulse_period_reg;
+    logic [15:0] pulse_num_reg;
     
-    );
+    logic [15:0] cnt_pulse_num;
+    logic [31:0] cnt_pulse_period;
 
-  (* MARK_DEBUG="true" *)  logic [DATA_WIDTH-1:0] pulse_height_reg, pulse_height_out_reg;
+    logic enable, synced;
 
-  (* MARK_DEBUG="true" *)  logic [31:0] pulse_width_reg, pulse_period_reg;
+    always @(posedge clk_dac) begin
-  (* MARK_DEBUG="true" *)  logic [15:0] pulse_num_reg;
-    
-  (* MARK_DEBUG="true" *)  logic enable;
-  (* MARK_DEBUG="true" *)  logic [15:0] cnt_pulse_num;
-  (* MARK_DEBUG="true" *)  logic [31:0] cnt_period;
-
-    
-    always @(posedge clk_in) begin
         if (rst) begin
-            pulse_height_reg <= 0;
+            pulse_height_reg   <=  ZERO_LEVEL;
-            pulse_height_out_reg <= '0;
+            pulse_width_reg    <=  0;
-            pulse_width_reg <= '0;
+            pulse_period_reg   <=  0;
-            pulse_period_reg <= '0;
+            pulse_num_reg      <=  0;
-            pulse_num_reg <= '0;
+            cnt_pulse_num      <=  0;
-            enable <= 0;
+            cnt_pulse_period   <=  0;
-            cnt_pulse_num <= '0;
+            dac_out            <=  ZERO_LEVEL;
-            cnt_period <= '0;
+            done               <=  0;
-            sample_req <= 0;
+            enable             <=  0;
-        end else begin
+            synced             <=  0;
-            if (start) begin
+        end 
-                enable <= 1'b1;
+        else begin
-                cnt_pulse_num <= '0;
+            // wait start for updating registers
-                cnt_period <= '0;
+            if (start & !enable) begin
-                
+                enable              <= 1;
-                sample_req <= 1;
+                pulse_width_reg     <= pulse_width;
-                
+                pulse_period_reg    <= pulse_period;
-                pulse_width_reg <= pulse_width;
+                pulse_num_reg       <= pulse_num;
-                pulse_period_reg <= pulse_period;
+                pulse_height_reg    <= pulse_height;
-                pulse_num_reg <= pulse_num;
-                pulse_height_reg <= pulse_height;
             end
+            // main work cycle
             if (enable) begin
-                if (!sample_req && (cnt_period == 0)) begin
+                if (cnt_pulse_num != pulse_num_reg) begin
-                    pulse_height_out_reg <= '0;
+                    // wait for synchronization with sampler
-                    if (sample_done) begin
+                    if (!synced) begin
-                        sample_req <= 1'b0;
+                        if (request & done) begin
-                    end
+                            synced  <= 1;
-                    
+                            done    <= 0;
-                    if (!sample_done) begin
-                        if (cnt_pulse_num == pulse_num_reg - 1) begin
-                            enable <= 1'b0;
                         end
-                        else begin
+                        else
-                            cnt_pulse_num <= cnt_pulse_num + 1;
+                            done <= 1;
-                            sample_req <= 1'b1;
+                    end
-                            cnt_period <= 1;
+                    else begin
+                        if (cnt_pulse_period != pulse_period_reg) begin
+                            if (cnt_pulse_period < pulse_width_reg)
+                                dac_out <= pulse_height_reg;
+                            else
+                                dac_out <= ZERO_LEVEL;
+                            cnt_pulse_period++;
+                        end
+                        else if (cnt_pulse_period == pulse_period_reg) begin
+                            cnt_pulse_num++;
+                            cnt_pulse_period    <=  0;
+                            synced              <=  0;
+                            dac_out             <=  ZERO_LEVEL;
                         end
                     end
                 end
-                 else begin
+                else if (cnt_pulse_num == pulse_num_reg) begin
-                        
+                    cnt_pulse_num   <=  0;
-                    if (cnt_period <= pulse_width_reg) begin
+                    enable          <=  0;
-                        pulse_height_out_reg <= pulse_height_reg;
-                    end else begin
-                        pulse_height_out_reg <= '0;
-                    end
-                    if (cnt_period == pulse_period_reg) begin
-                        cnt_period <= 0;
-                    end else begin
-                        cnt_period <= cnt_period + 1;
-                    end
-                    if (sample_req && sample_done) begin
-                        sample_req <= 0;
-                    end
                 end
             end
         end
     end
 
-     OBUF OBUF_pulse_clk (
+    // Gated DAC write signal from DAC clock. Needed for posedge
-        .I(clk_in),
+    OBUF OBUF_pulse_clk (
-        .O(pulse)
+        .I(clk_dac & enable),
+        .O(dac_wrt)
     );
     
-    assign pulse_height_out = pulse_height_out_reg;
-    
 endmodule

rtl/generator/tests/generator_tb.sv

@@ -1,105 +1,363 @@
 `timescale 1ns / 1ps
 
 module generator_tb;
+    // === Параметры ===
+    localparam DATA_WIDTH = 14;
+    localparam LOGIC_ZERO_LEVEL = 0; // DAC -5V for logic zero
+    localparam VOLTAGE_ZERO_LEVEL = 2**(DATA_WIDTH-1); // DAC 0V for logic zero
+    localparam CLK_PERIOD = 8;
+    parameter string ZERO_LEVEL = "logic"; // "logic" VS "true"
 
-    parameter DATA_WIDTH = 14;
+    // === Сигналы ===
-    parameter CLK_PERIOD = 16;
+    // Системные сигналы
-
     logic clk;
     logic rst;
     logic start;
+    // Входные сигналы
+    logic [31:0]            pulse_width;    // config reg
+    logic [31:0]            pulse_period;   // config reg
+    logic [DATA_WIDTH-1:0]  pulse_height;   // config reg
+    logic [15:0]            pulse_num;      // config reg
+    logic sampler_done;             // sampler request for synchronization
+    // Выходные сигналы
+    wire dac_wrt;                   // DAC wrt singnal
+    wire [DATA_WIDTH-1:0] dac_out;  // DAC input logic signal
+    wire generator_done;            // generator request for synchronization
 
-    logic [31:0] pulse_width;
+    // === Переменные ===
-    logic [31:0] pulse_period;
+    int current_zero_level;
-    logic [DATA_WIDTH-1:0] pulse_height;
+    initial begin
-    logic [15:0] pulse_num;
+        if (ZERO_LEVEL == "true")
-
+            current_zero_level = VOLTAGE_ZERO_LEVEL;
-    logic pulse;
+        else
-    logic [DATA_WIDTH-1:0] pulse_height_out;
+            current_zero_level = LOGIC_ZERO_LEVEL;
+    end
 
     // DUT
-    generator #(
+    generate
-        .DATA_WIDTH(DATA_WIDTH)
+        if (ZERO_LEVEL == "true") begin : gen_dut_true
-    ) dut (
+            generator #(
-        .clk_in(clk),
+                .DATA_WIDTH(DATA_WIDTH),
-        .rst(rst),
+                .ZERO_LEVEL(VOLTAGE_ZERO_LEVEL)
-        .start(start),
+            ) dut (
-        .pulse_width(pulse_width),
+                .clk_dac(clk),
-        .pulse_period(pulse_period),
+                .rst(rst),
-        .pulse_height(pulse_height),
+                .start(start),
-        .pulse_num(pulse_num),
+                .pulse_width(pulse_width),
-        .pulse(pulse),
+                .pulse_period(pulse_period),
-        .pulse_height_out(pulse_height_out)
+                .pulse_height(pulse_height),
-    );
+                .pulse_num(pulse_num),
+                .dac_wrt(dac_wrt),
+                .dac_out(dac_out),
+                .done(generator_done),
+                .request(sampler_done)
+            );
+            initial $display("[TB] Generator compiled. ZERO_LEVEL: TRUE");
+        end 
+        else if (ZERO_LEVEL == "logic") begin : gen_dut_logic
+            generator #(
+                .DATA_WIDTH(DATA_WIDTH),
+                .ZERO_LEVEL(LOGIC_ZERO_LEVEL)
+            ) dut (
+                .clk_dac(clk),
+                .rst(rst),
+                .start(start),
+                .pulse_width(pulse_width),
+                .pulse_period(pulse_period),
+                .pulse_height(pulse_height),
+                .pulse_num(pulse_num),
+                .dac_wrt(dac_wrt),
+                .dac_out(dac_out),
+                .done(generator_done),
+                .request(sampler_done)
+            );
+            initial $display("[TB] Generator compiled. ZERO_LEVEL: LOGIC");
+        end
+        else begin : gen_dut_error
+            // защита от дурака
+            initial begin
+                $display("[ERROR] Unknown value ZERO_LEVEL: %s", ZERO_LEVEL);
+                $finish;
+            end
+        end
+    endgenerate
 
-    // Clock
+    // Тактовые сигналы
     initial begin
         clk = 0;
         forever #(CLK_PERIOD/2) clk = ~clk;
     end
 
-    initial begin
+    // === Таски для тестипрования ===
-        $display("\n=== GENERATOR TEST ===\n");
+    // Таска синхронизации, одно рукопожатие
+    task automatic synchronize(
+        input bit sampler_first,      // 1 - выставить sampler_done ДО генератора, 0 - ПОСЛЕ
+        input int delay_before_ack,   // Если sampler_first=0: задержка ПОСЛЕ gen_done. Если 1: задержка от НАЧАЛА цикла.
+        input int ack_duration        // сколько тактов удерживать sampler_done после встречи сигналов
+    );
+        if (sampler_first) begin
+            // --- сэмплер готов до генератора ---
+            repeat(delay_before_ack) @(posedge clk);
+            sampler_done <= 1;
+            wait(generator_done == 1);
+            repeat(ack_duration) @(posedge clk);
+            sampler_done <= 0;
+        end 
+        else begin
+            // --- генератора готов до сэмплер ---
+            wait(generator_done == 1);
+            repeat(delay_before_ack) @(posedge clk);
+            sampler_done <= 1;
+            repeat(ack_duration) @(posedge clk);
+            sampler_done <= 0;
+        end
+    endtask
 
+    // Таска сброса DUT
+    task automatic reset_dut(
+        input int rst_duration    // сколько тактов держать сброс
+    );
+        rst <= 1;
+        repeat(rst_duration) @(posedge clk);
+        rst <= 0;
+    endtask
+
+    // Таска запуска DUT
+    task automatic start_dut(
+        input int start_duration    // сколько тактов держать импульс
+    );
+        start <= 1;
+        repeat(start_duration) @(posedge clk);
+        start <= 0;
+    endtask
+
+    // Таска конфигурации DUT
+    task automatic set_config(
+        input logic [31:0]              w,  // ширина импульса
+        input logic [31:0]              p,  // период импульса
+        input logic [15:0]              n,  // количество импульсов
+        input logic [DATA_WIDTH-1:0]    h   // высота импульса
+    );
+        // Задаем конфигурационные регистры
+        @(posedge clk);
+        pulse_width  <= w;
+        pulse_period <= p;
+        pulse_num    <= n;
+        pulse_height <= h;
+    endtask
+
+    // Таска проверки устойчивости к долгим управляющим импульсам
+    task automatic check_impulses;
+        // Локальные переменные для хранения случайных параметров
+        int rand_start_duration;
+        int rand_delay;
+        int rand_ack;
+        bit rand_first;
+        int total_impulse_cycles = 0;
+
+        int pulse_w = 11;
+        int pulse_p = 31;
+        int pulse_n = 5;
+        int pulse_h = 1024;
+
+        $display("[TB] -check_impulses- Check system stability under random latencies");
+
+        // Установка конфигурации
+        set_config(
+            .w(pulse_w), 
+            .p(pulse_p), 
+            .n(pulse_n), 
+            .h(pulse_h)
+        );
+
+        reset_dut(5);
+        repeat(2) @(posedge clk);
+
+        // Старт норме 1 такт. Сделаем случайным от 5 до 25 тактов.
+        rand_start_duration = $urandom_range(5, 25);
+        $display("[TB] Long start: %0d clocks", rand_start_duration);
+
+        // Фоновый процесс подсчета тактов импульса
+        fork 
+            begin : counter_proc
+                forever begin
+                    @(posedge dac_wrt);
+                    if (dac_out == pulse_h) begin
+                        total_impulse_cycles++;
+                    end
+                end
+            end
+        join_none
+        
+        // Параллельный запуск длинного старта и обработки синхронизации
+        fork
+            // Поток 1: Удерживаем старт аномально долго
+            begin
+                start_dut(rand_start_duration);
+            end
+            // Поток 2: Обслуживаем n=4 циклов синхронизации со случайными задержками
+            begin
+                repeat(pulse_n) begin
+                    // Рандомизируем параметры для каждого из 4-х рукопожатий
+                    rand_first = $urandom;               // Случайно: Самплер первый (1) или Генератор первый (0)
+                    rand_delay = $urandom_range(1, 8);   // Случайная задержка ожидания (1..8 тактов)
+                    rand_ack   = $urandom_range(5, 10); // Аномально долгий удерживаемый импульс sampler_done (10..30 тактов)
+
+                    synchronize(
+                        .sampler_first(rand_first),
+                        .delay_before_ack(rand_delay),
+                        .ack_duration(rand_ack)
+                    );
+                end
+            end
+        join
+        repeat(pulse_p+5) @(posedge clk);
+        disable counter_proc;
+        // Ожидание завершения переходных процессов
+        repeat(10) @(posedge clk);
+        if (total_impulse_cycles == pulse_w*pulse_n)
+            $display("[TB] -check_impulses- Pulse generation CORRECT");
+        else begin
+                $display("[ERROR] -check_impulses- Pulse generation INCORRECT. Total number of pulses: %d, must be: %d", total_impulse_cycles, pulse_w*pulse_n);
+                $finish;
+        end
+        $display("[TB] -check_impulses- Done");
+    endtask
+
+    task automatic run_test_case(
+        input int pulse_w,
+        input int pulse_p,
+        input int pulse_n,
+        input int pulse_h,
+        input bit skip_reset,   // skip reset sequence on demand
+        input bit count_level   // count ticks of amplitude == pulse_h or amplitude != pulse_h
+    );
+        int total_impulse_cycles = 0;
+
+        if (!skip_reset) begin
+            reset_dut(1);
+            @(posedge clk);
+        end
+
+        set_config(
+            .w(pulse_w), 
+            .p(pulse_p), 
+            .n(pulse_n), 
+            .h(pulse_h)
+        );
+        @(posedge clk);
+
+        start_dut(1);
+        
+        // Фоновый процесс подсчета тактов импульса
+        fork
+            begin : counter_proc
+                forever begin
+                    @(posedge dac_wrt);
+                    if (count_level) begin
+                        if (dac_out == pulse_h) begin
+                            total_impulse_cycles++;
+                        end
+                    end
+                    else begin
+                        if (dac_out != current_zero_level) begin
+                            total_impulse_cycles++;
+                        end
+                    end
+                end
+            end
+        join_none
+
+        repeat(pulse_n) begin
+            synchronize(
+                .sampler_first(0),
+                .delay_before_ack(1),
+                .ack_duration(2)
+            );
+        end
+        repeat(pulse_p+5) @(posedge clk);
+        disable counter_proc;
+        repeat(10) @(posedge clk);
+
+        if (count_level) begin
+            if (total_impulse_cycles == pulse_w*pulse_n)
+                $display("[TB] -run_test_case- Pulse generation CORRECT");
+            else begin
+                    $display("[ERROR] -run_test_case- Pulse generation INCORRECT. Total number of pulses: %d, must be: %d", total_impulse_cycles, pulse_w*pulse_n);
+                    $finish;
+            end
+        end
+        else begin
+            if (total_impulse_cycles == 0)
+                $display("[TB] -run_test_case- Pulse generation CORRECT");
+            else begin
+                    $display("[ERROR] -run_test_case- Pulse generation INCORRECT. Total number of pulses: %d, must be: %d", total_impulse_cycles, 0);
+                    $finish;
+            end
+        end
+    endtask
+
+    // --- ОСНОВНОЙ ПРОЦЕСС ТЕСТИРОВАНИЯ ---
+    initial begin
+        $display("[TB] Tests start");
+
+        // Инициализация
         rst = 1;
         start = 0;
-
         pulse_width  = 0;
         pulse_period = 0;
         pulse_height = 0;
         pulse_num    = 0;
+        sampler_done = 0;
 
-        repeat(5) @(posedge clk);
+        $display("[TB] Test 1. Random latency for control signals");
-        rst = 0;
+        check_impulses();
+        $display("[TB] Test 1 complete");
 
-        // --- Test 1 ---
+        $display("[TB] Test 2. Random configs");
-        // 3 clk 1, 5 clk 0,  4 pulses
+        for (int i = 0; i < 25; i++) begin
-       repeat(2) @(posedge clk);
+            int r_w, r_p, r_n, r_h;
-        pulse_width  = 3;
+            bit r_skip;
-        pulse_period = 8;
-        pulse_num    = 4;
-        pulse_height = 14'h3FF;
-        start = 1;
 
-       repeat(1) @(posedge clk);
+            // Генерируем параметры
-        start = 0;
+            r_p    = $urandom_range(5, 50);          // Период от 5 до 50
+            r_w    = $urandom_range(0, r_p);         // Ширина не больше периода
+            r_n    = $urandom_range(1, 10);          // Количество импульсов
+            r_h    = $urandom_range(1, 2**DATA_WIDTH-1);       // Высота (для 14 бит)
+            r_skip = $urandom_range(0, 1);           // Случайный сброс (0 - сброс, 1 - пропуск)
 
-        repeat(50) @(posedge clk);
+            // Защита от "нулевого" импульса. Невозможно проверить длительность.
+            if (r_h == current_zero_level) begin
+                r_h += $urandom_range(1, 10);
+            end
 
-        // --- Test 2 ---
+            $display("[TB] --- Test #%0d (Config: W=%0d, P=%0d, N=%0d, H=%0d, SkipReset=%0b) ---", 
-        $display("\n--- SECOND RUN ---\n");
+                      i+1, r_w, r_p, r_n, r_h, r_skip);
 
-        @(posedge clk);
+            run_test_case(
-        pulse_width  = 2;
+                .pulse_w(r_w), 
-        pulse_period = 5;
+                .pulse_p(r_p), 
-        pulse_num    = 3;
+                .pulse_n(r_n), 
-        pulse_height = 14'h155;
+                .pulse_h(r_h), 
-        start = 1;
+                .skip_reset(r_skip),
+                .count_level(1)
+            );
+        end
+        $display("[TB] Test 2 complete");
 
-        @(posedge clk);
+        $display("[TB] Test 3. Zero level of pulse height");
-        start = 0;
+        run_test_case(
+            .pulse_w(77), 
+            .pulse_p(131), 
+            .pulse_n(13), 
+            .pulse_h(current_zero_level), 
+            .skip_reset(0),
+            .count_level(0)
+        );
+        $display("[TB] Test 3 complete");
 
-        repeat(40) @(posedge clk);
+        $display("[TB] ALL PASSED");
-        
-         pulse_width  = 3;
-        pulse_period = 8;
-        pulse_num    = 4;
-        pulse_height = 14'h3FF;
-        start = 1;
-
-       repeat(1) @(posedge clk);
-        start = 0;
-
-        repeat(50) @(posedge clk);
-
-        $display("\n=== TEST FINISHED ===");
         $finish;
     end
 
-    // Display
-    always @(posedge clk) begin
-        $display("t=%0t | pulse=%0b | height=%h",
-                  $time, pulse, pulse_height_out);
-    end
-
 endmodule

rtl/sampler/README.md

@@ -1,23 +1,139 @@
 # Сэмплер
-Модуль выполняет задачу сбора данных с выхода АЦП, их обработку, упаковку, и передачу дальше с помощью AXI Stream интерфейса.
 
-## Cписок параметров
+Модуль выполняет задачу сбора данных с выхода АЦП, их обработки, упаковки и передачи дальше с помощью AXI Stream интерфейса.  
-DATA_WIDTH - ширина входных данных, получаемых с АЦП.
+Дополнительно реализован механизм синхронизации с внешним генератором через сигналы `sample_req` и `sample_done`, позволяющий запускать сбор строго по запросу и подтверждать завершение выборки.
-PACK_FACTOR - количество отсчетов, собираемых в один выходной пакет.
+
-PROCESS_MODE - режим интерпретации входного кода. 0 - прямой код, 1 - дополнительный код.
+---
+
+## Список параметров
+
+DATA_WIDTH
+Ширина входных данных, получаемых с АЦП.
+
+PACK_FACTOR
+Количество отсчетов, собираемых в один выходной пакет.
+
+PROCESS_MODE
+Режим интерпретации входного кода:
+
+- `0` — прямой код
+- `1` — дополнительный код
+
+---
 
 ## Список входных портов
-clk_in - сигнал тактирования выходного интерфейса.
+
-rst - сброс модуля и остановка подачи импульсов.
+clk_in
-[DATA_WIDTH-1:0] data_in - входной сигнал с АЦП.
+Сигнал тактирования выходного интерфейса.
-out_of_range - флаг выхода значений данных за допустимый диапазон. 0 - валидны, 1 - не валидны.
+
+rst
+Сброс модуля и остановка работы.
+
+[DATA_WIDTH-1:0] data_in
+Входной сигнал с АЦП.
+
+out_of_range
+Флаг выхода значений данных за допустимый диапазон:
+
+- `0` — данные валидны
+- `1` — данные невалидны и игнорируются
+
+[31:0] smp_num
+Количество валидных отсчетов, которое необходимо собрать после получения запроса на выборку.
+
+sample_req
+Сигнал запроса на запуск выборки.  
+При его активации модуль начинает сбор данных и переходит в активное состояние (`enable = 1`).
+
+---
 
 ## Список выходных портов
-[DATA_WIDTH*PACK_FACTOR-1:0]  m_axis_tdata - урезанный axis формат, выходные данные. Ширина шины считается исходя из битности данных и фактора упаковки.
+
-m_axis_tvalid - урезанный axis формат, валидность выходных данных.
+[DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata
+Урезанный AXI Stream формат, выходные данные.  
+Ширина шины определяется как произведение битности данных и фактора упаковки.
+
+m_axis_tvalid
+Урезанный AXI Stream формат, сигнал валидности выходных данных.  
+Формируется при готовности очередного пакета.
+
+sample_done
+Сигнал завершения выборки.  
+Поднимается после того, как модуль собрал количество валидных отсчетов, равное `smp_num`.
+
+---
 
 ## Логика работы
-На каждом такте принимаются data_in (значение АЦП) и out_of_range (флаг выхода значений данных за допустимый диапазон). Если out_of_range = 1, то данные игнорируются и не попадают во внутренний буффер. В противном случае, модуль накапливает данные во внутреннем буффере, идет его заполнение до количества данных, равное PACK_FACTOR. Когда буффер оказывается заполненным, он выдает пакет упакованных данных, сопровождая их импульсом m_axis_tvalid (готовность пакета). Если PROCESS_MODE = 1, данные выдаются в дополнительном коде, если PROCESS_MODE = 0 - в прямом.
+
+На каждом такте принимаются:
+
+- `data_in` — значение АЦП
+- `out_of_range` — флаг допустимости значения
+
+Если `out_of_range = 1`, данные считаются невалидными, игнорируются и не попадают во внутренний буфер.
+
+Если `out_of_range = 0`, данные считаются корректными и используются для дальнейшей обработки.
+
+---
+
+### Преобразование данных
+
+Если `PROCESS_MODE = 1`, входные данные интерпретируются как дополнительный код и преобразуются перед упаковкой.
+
+Если `PROCESS_MODE = 0`, данные передаются без преобразования (прямой код).
+
+---
+
+### Запуск выборки
+
+Сбор данных начинается только после прихода сигнала `sample_req`.
+
+При этом:
+
+- фиксируется значение `smp_num`
+- внутренний счетчик собранных отсчетов обнуляется
+- модуль переходит в активное состояние (`enable = 1`)
+
+Пока `enable = 1`, модуль принимает только валидные отсчеты и считает их.
+
+---
+
+### Упаковка данных
+
+Внутренний буфер заполняется до количества данных, равного `PACK_FACTOR`.
+
+#### Если `PACK_FACTOR = 1`
+
+Каждый валидный отсчет сразу формирует выходной пакет:
+
+- данные передаются в `m_axis_tdata`
+- формируется импульс `m_axis_tvalid`
+
+#### Если `PACK_FACTOR > 1`
+
+Данные последовательно накапливаются во внутреннем сдвиговом буфере.
+
+Когда буфер полностью заполнен:
+
+- формируется пакет упакованных данных
+- поднимается `m_axis_tvalid`
+
+После этого начинается сбор следующего пакета.
+
+---
+
+### Завершение выборки
+
+Когда количество собранных валидных отсчетов достигает значения `smp_num`:
+
+- поднимается сигнал `sample_done`
+- внутренние счетчики сбрасываются
+- буфер очищается
+- `enable` сбрасывается в `0`
+
+Это означает полное завершение текущего цикла выборки.
+
+---
 
 ## Симуляция
 Тесты запускаются автоматически через make.

rtl/sampler/src/sampler.sv

@@ -1,7 +1,5 @@
 `timescale 1ns / 1ps
 
-
-
 module sampler
 #(
     parameter DATA_WIDTH = 12,
@@ -14,16 +12,16 @@ module sampler
     input [DATA_WIDTH-1:0] data_in,
     input out_of_range,
     input [31:0] smp_num,
-    input sample_req,
+    input done,
 
     output logic [DATA_WIDTH*PACK_FACTOR-1:0]  m_axis_tdata,
     output logic                              m_axis_tvalid,
-    output logic sample_done
+    output logic request
     );
    (* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] data_converted;
    (* MARK_DEBUG="true" *) logic out_of_range_reg;
     (* MARK_DEBUG="true" *) logic [31:0] smp_num_reg, cnt_smp_num;
-   (* MARK_DEBUG="true" *) logic enable;
+   (* MARK_DEBUG="true" *) logic enable, enable_d;
     
     generate
        if (PROCESS_MODE) begin 
@@ -68,20 +66,22 @@ module sampler
                 buffer_ready <= 0;
                 cnt_smp_num <= '0;
                 smp_num_reg <= '0;
-                enable <= '0;
+                enable <= 0;
-                sample_done <= 0;
+                request <= 0;
             end
             else begin
                 buffer_ready <= 0;
-                if (sample_done && !sample_req) begin
+                enable_d <= enable;
-                    sample_done <= 1'b0;
+                if (!enable) begin
-                end
+                    if (request && done) begin
-                if (!enable && sample_req && !sample_done) begin
+                        enable  <= 1;
-                    enable      <= 1;
+                        request <= 0;
-                    cnt_smp_num <= 0;
+                        cnt_smp_num <= 0;
-                    smp_num_reg <= smp_num;
+                        smp_num_reg <= smp_num;
-                end
+                    end else begin
-                if (enable) begin
+                        request <= 1;
+                    end
+                end else begin
                     if (!out_of_range_reg) begin
                         if (cnt_smp_num != smp_num_reg) begin
                             buffer       <= data_converted;
@@ -90,8 +90,6 @@ module sampler
                         end 
                         else begin
                             cnt_smp_num <= '0;
-                            sample_done <= 1'b1;
-                            buffer_ready <= 0;
                             buffer <= '0;
                             enable <= 0;
                         end
@@ -108,21 +106,21 @@ module sampler
                 cnt_smp_num <= '0;
                 smp_num_reg <= '0;
                 enable <= 0;
-                sample_done <= 0;
+                request <= 0;
             end
             else begin
                 buffer_ready <= 0;
-                if (sample_done && !sample_req) begin
+                if (!enable) begin
-                    sample_done <= 1'b0;
+                    if (!request) request <= 1;
-                end
+                    if (request && done) begin
-                if (!enable && sample_req && !sample_done) begin
+                        enable      <= 1;
-                    enable      <= 1;
+                        request <= 0;
-                    cnt_smp_num <= 0;
+                        cnt_smp_num <= 0;
-                    smp_num_reg <= smp_num;
+                        smp_num_reg <= smp_num;
-                end
+                    end
-                if (enable) begin
+                end else begin
                     if (!out_of_range_reg) begin
-                        if (cnt_smp_num != smp_num_reg) begin
+                        if (cnt_smp_num < smp_num_reg) begin
                             cnt_smp_num <= cnt_smp_num +1;
                             buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
                             if (cnt == PACK_FACTOR-1) begin
@@ -135,7 +133,6 @@ module sampler
                             end
                         end 
                         else begin
-                            sample_done <= 1'b1;
                             cnt_smp_num <= '0;
                             buffer_ready <= 0;
                             buffer <= '0;

rtl/sampler/tests/sampler_main_tb.sv

@@ -2,130 +2,209 @@
 
 module sampler_tb;
 
-    parameter DATA_WIDTH   = 12;
+    // =========================================================
-    parameter PROCESS_MODE = 0;
+    // PARAMETERS
-    parameter CLK_PERIOD   = 15.3846;
+    // =========================================================
-    parameter TEST_NUM     = 1000;
+    localparam DATA_WIDTH  = 12;
+    localparam PACK_FACTOR = 1;
+    localparam PROCESS_MODE = 0;
+    localparam CLK_PERIOD = 15.3846;
 
+    // =========================================================
+    // SIGNALS
+    // =========================================================
     logic clk;
     logic rst;
 
     logic [DATA_WIDTH-1:0] data_in;
     logic out_of_range;
 
-    logic [DATA_WIDTH-1:0] m_axis_tdata;
+    logic [31:0] smp_num;
+
+    logic done;
+    logic request;
+
+    logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
     logic m_axis_tvalid;
 
-    integer errors = 0;
+    // =========================================================
-
+    // DUT
+    // =========================================================
     sampler #(
         .DATA_WIDTH(DATA_WIDTH),
+        .PACK_FACTOR(PACK_FACTOR),
         .PROCESS_MODE(PROCESS_MODE)
     ) dut (
         .clk_in(clk),
         .rst(rst),
+
         .data_in(data_in),
         .out_of_range(out_of_range),
+
+        .smp_num(smp_num),
+        .done(done),
+
         .m_axis_tdata(m_axis_tdata),
-        .m_axis_tvalid(m_axis_tvalid)
+        .m_axis_tvalid(m_axis_tvalid),
+
+        .request(request)
     );
 
+    // =========================================================
+    // CLOCK
+    // =========================================================
     initial begin
         clk = 0;
         forever #(CLK_PERIOD/2) clk = ~clk;
     end
 
-    function automatic [DATA_WIDTH-1:0] ref_convert(input [DATA_WIDTH-1:0] din);
+    // =========================================================
-        if (PROCESS_MODE == 0)
+    // RESET (ONLY ONCE)
-            return din;
+    // =========================================================
-        else if (din == {1'b1, {(DATA_WIDTH-1){1'b0}}})
-            return din;
-        else
-            return din[DATA_WIDTH-1] ?
-                   {1'b1, (~din[DATA_WIDTH-2:0] + 1'b1)} :
-                   din;
-    endfunction
-
-    task send(input [DATA_WIDTH-1:0] word, input bit oor);
-        @(posedge clk);
-        data_in      <= word;
-        out_of_range <= oor;
-    endtask
-
-    logic [DATA_WIDTH-1:0] exp_d0, exp_d1, exp_d2;
-    logic oor_d0, oor_d1, oor_d2;
-
     initial begin
-        $display("\n=== RANDOM SAMPLER TEST===\n");
-
         rst = 1;
+        done = 0;
         data_in = 0;
         out_of_range = 0;
-
+        smp_num = 0;
-        exp_d0 = 0;
-        exp_d1 = 0;
-        exp_d2 = 0;
-
-        oor_d0 = 1;
-        oor_d1 = 1;
-        oor_d2 = 1;
 
         repeat(5) @(posedge clk);
         rst = 0;
-        repeat(2) @(posedge clk);
+    end
 
-        repeat (TEST_NUM) begin
+    // =========================================================
-            logic [DATA_WIDTH-1:0] rand_data;
+    // CONFIG
-            bit rand_oor;
+    // =========================================================
+    task automatic set_config(
+        input int n,
+        input int init_delay
+    );
+        smp_num = n;
+        repeat(init_delay) @(posedge clk);
+    endtask
 
-            rand_data = $urandom_range(0, (1 << DATA_WIDTH) - 1);
+    // =========================================================
-            rand_oor  = ($urandom_range(0, 99) < 20);
+    // HANDSHAKE (DONE/REQUEST)
+    // =========================================================
+    task automatic synchronize_sampler(
+        input bit sampler_first,
+        input int delay_before_ack,
+        input int ack_duration
+    );
+        if (sampler_first) begin
+            repeat(delay_before_ack) @(posedge clk);
 
-            @(negedge clk);
+            done <= 1'b1;
+            wait(request == 1'b1);
 
-            if (!oor_d2) begin
+            repeat(ack_duration) @(posedge clk);
-                if (m_axis_tvalid !== 1) begin
-                    $display("ERROR: valid=0");
-                    errors++;
-                end
 
-                if (m_axis_tdata !== exp_d2) begin
+            done <= 1'b0;
-                    $display("ERROR: data mismatch");
-                    $display(" expected = %h", exp_d2);
-                    $display(" got      = %h", m_axis_tdata);
-                    errors++;
-                end
-            end
-
-            send(rand_data, rand_oor);
-
-            exp_d2 = exp_d1;
-            exp_d1 = exp_d0;
-            exp_d0 = ref_convert(rand_data);
-
-            oor_d2 = oor_d1;
-            oor_d1 = oor_d0;
-            oor_d0 = rand_oor;
         end
+        else begin
+            wait(request == 1'b1);
 
-        @(posedge clk);
+            repeat(delay_before_ack) @(posedge clk);
 
+            done <= 1'b1;
 
-        if (!oor_d2) begin
+            repeat(ack_duration) @(posedge clk);
 
-            if (m_axis_tdata !== exp_d2) begin
+            done <= 1'b0;
-                $display("ERROR: final mismatch");
-                $display(" expected = %h", exp_d2);
-                $display(" got      = %h", m_axis_tdata);
-                errors++;
-            end
         end
+    endtask
 
-        if (errors == 0)
+    // =========================================================
-            $display("\n========== ALL PASSED ==========\n");
+    // DATA STREAM (STARTS AFTER SYNC)
+    // =========================================================
+    task automatic feed_data_stream(
+        input int num_words,
+        input bit random_mode
+    );
+        logic [DATA_WIDTH-1:0] val;
+        val = 1;
+
+        for (int i = 0; i < num_words; i++) begin
+            @(posedge clk);
+
+            if (random_mode)
+                val = $urandom_range(1, 2**DATA_WIDTH-1);
+            else
+                val = val + 1;
+
+            data_in <= val;
+            out_of_range <= 0;
+            
+        end
+    endtask
+
+    // =========================================================
+    // COUNTER
+    // =========================================================
+    int received_count;
+
+    always @(posedge clk) begin
+        if (m_axis_tvalid)
+            received_count++;
+    end
+
+    // =========================================================
+    // TEST CASE
+    // =========================================================
+    task automatic run_test_case(
+        input int n,
+        input int delay,
+        input int ack,
+        input bit sampler_first,
+        input bit random_stream
+    );
+        received_count = 0;
+
+        set_config(n, 2);
+
+        // 1) сначала синхронизация
+        synchronize_sampler(sampler_first, delay, ack);
+
+        // 2) СРАЗУ после sync - поток данных
+        feed_data_stream(n, random_stream);
+
+        repeat(20) @(posedge clk);
+
+        if (received_count == n)
+            $display("[OK] received %0d / %0d", received_count, n);
         else
-            $display("\n========== FAILED: %0d errors ==========\n", errors);
+            $display("[ERROR] received %0d / %0d", received_count, n);
+    endtask
 
+    // =========================================================
+    // RANDOM STRESS TEST
+    // =========================================================
+    task automatic check_random;
+        int n, d, a;
+        bit sf;
+
+        for (int i = 0; i < 20; i++) begin
+            n  = $urandom_range(3, 10);
+            d  = $urandom_range(0, 5);
+            a  = $urandom_range(1, 5);
+            sf = $urandom_range(0, 1);
+
+            $display("\n--- TEST %0d --- n=%0d delay=%0d ack=%0d sf=%0b",
+                     i, n, d, a, sf);
+
+            run_test_case(n, d, a, sf, 1);
+        end
+    endtask
+
+    // =========================================================
+    // MAIN
+    // =========================================================
+    initial begin
+        $display("\n=== SAMPLER TEST (FIXED FLOW: NO MULTI RESET) ===\n");
+
+        check_random();
+
+        $display("\n=== TEST FINISHED ===");
         $finish;
     end
 

scripts/build.sh

@@ -1 +0,0 @@
-# mock

software/README.md

@@ -0,0 +1,20 @@
+# Software
+
+Просто скрипт на питоне, для отправки команд через ethernet и для приема и простой визуализации данных.
+
+## Использование
+Справка:
+
+```python3 --help```
+
+Положительный импульс:
+
+```python3 console.py --pulse_width 3500 --pulse_period 20000 --pulse_height 15000 --pulse_num 550 --dac-bits 14```
+
+Отрицательный импульс:
+
+```python3 console.py --pulse_width 15000 --pulse_period 20000 --pulse_height 1500 --pulse_num 550 --dac-bits 14```
+
+## Ограничения
+Максимальный pulse_period считается как аппаратный N_MAX * WINDOW_SIZE * adc_dac_ratio, в базовой конфигурации это 512000. Максимальный pulse_num зависит от подаваемых значений и от битности аккумулятора (по умолчанию - 32), с учетом усреднений по WINDOW_SIZE это получается что-то около 2^14 накоплений.
+