This commit is contained in:
Phil
2026-05-15 15:09:16 +03:00

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@ -44,19 +44,20 @@ module generator
cnt_period <= '0;
sample_req <= 0;
end else begin
if (start) begin
if (start & !enable) begin
enable <= 1'b1;
cnt_pulse_num <= '0;
cnt_period <= '0;
sample_req <= 1;
pulse_width_reg <= pulse_width;
pulse_period_reg <= pulse_period;
pulse_num_reg <= pulse_num;
pulse_height_reg <= pulse_height;
end
end
if (enable) begin
if (!sample_req && (cnt_period == 0)) begin
pulse_height_out_reg <= ZERO_LEVEL;
if (sample_done) begin