Commit Graph
14 Commits
Author SHA1 Message Date
babintsev.lv 11a9e97691 upd: reflectometer on axis bus iface + TB 2026-07-10 18:46:48 +03:00
babintsev.lv 0ba25a3541 add: vrtual DAC & ADC subsystem for TB
fix: makefile
upd: clocking wiz IP
2026-07-10 14:15:49 +03:00
babintsev.lv 64f94a90e6 add: virtual DAC (100%) and ADC (80%)
upd: makefile
2026-07-08 17:47:56 +03:00
babintsev.lv 7665afd50b add: half-baked reflectometer TB
fix: constraints port names;
ready: reflectometer top module
2026-07-08 14:56:51 +03:00
babintsev.lv c3275d5b46 upd: ref 2026-07-07 15:12:48 +03:00
babintsev.lv 725826b07c add: new reflectometer top design (not ready) 2026-07-03 16:32:48 +03:00
babintsev.lv d878bac42a upd: new top design WIP 2026-06-30 17:21:49 +03:00
babintsev.lv 771225cd77 fix: post-implementation timing sim TB passed 2026-06-23 17:27:20 +03:00
babintsev.lv c0714f271e Merge remote-tracking branch 'refs/remotes/origin/dev/design' into dev/design 2026-06-10 16:44:00 +03:00
babintsev.lv c165d346a0 update: new synchronizer + half-baked TB 2026-06-10 16:40:53 +03:00
babintsev.lv c8e11a2a1f half-baked new generator 2026-05-29 18:16:43 +03:00
babintsev.lv 0a68a753be generator quick fix 2026-05-29 18:01:31 +03:00
babintsev.lv 906d5090cd reflectometer top testbench config update 2026-05-26 18:30:51 +03:00
babintsev.lv dc761f31dc Add reflectometer testbench stable boilerplate with tasks 2026-05-22 17:07:15 +03:00