Compare commits
5 Commits
dev/contro
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966d0379b7
| Author | SHA1 | Date | |
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| 966d0379b7 | |||
| 88db70ede8 | |||
| ad6d6a4e2b | |||
| 7a1c838de3 | |||
| 221cb055f1 |
10
.gitignore
vendored
10
.gitignore
vendored
@ -12,14 +12,4 @@
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*.log
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*.log
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*.rpt
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*.rpt
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*.dcp
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*.dcp
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*.xpr
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.Xil
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.Xil
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xvlog.pb
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*vivado_pid*
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# some generated files (they annoy me)
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update_config.tcl
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create_project.tcl
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gen_ip.tcl
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defines.v
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run_sim.tcl
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@ -1,3 +0,0 @@
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# Директория с тестовыми проектами под ПЛИСу
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- eth_ctrl_debug: проект с ethernet и контроллером. Позволяет через ILA проверить, что пакет правильно принимается и что значения правильно выставляются.
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@ -1,52 +0,0 @@
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# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# FPGA settings
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FPGA_PART = xc7a35tfgg484-1
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FPGA_TOP = eth_ctrl_debug_top
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FPGA_ARCH = artix7
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RTL_DIR = ../../rtl
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include ../../scripts/vivado.mk
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SYN_FILES += eth_ctrl_debug.sv
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SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
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XCI_FILES = $(sort $(shell find ../../rtl/ethernet-udp/src -type f -name '*.xci'))
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XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
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XDC_FILES += ../../constraints/ax7a035b.xdc
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XDC_FILES += debug.xdc
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program: $(PROJECT).bit
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echo "open_hw_manager" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
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echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
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echo "exit" >> generate_mcs.tcl
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vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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COUNT=$$((COUNT-1)); \
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for x in .mcs .prm; \
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do cp $*$$x rev/$*_rev$$COUNT$$x; \
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echo "Output: rev/$*_rev$$COUNT$$x"; done;
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@ -1,7 +0,0 @@
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# Тестовый проект Eth + CTRL
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Проект состоит из AXIS Ethernet и контроллера. Для тестирования сделано три разных частотных домена: ethernet 125MHz, DAC 130MHz, ADC 65MHz для тестирования сихронизации. Есть ILA на все выходы контроллера и на шину AXIS eth -> ctrl. Для отправки пакетов используйте скрипт ```console.py --debug```.
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## Сборка
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```make all``` - собрать все до битстрима
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```make vivado``` - открыть проект в Vivado
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@ -1,147 +0,0 @@
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set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst]
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create_debug_core u_ila_0 ila
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
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set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
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set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
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set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
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set_property port_width 1 [get_debug_ports u_ila_0/clk]
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connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out2]]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
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set_property port_width 32 [get_debug_ports u_ila_0/probe0]
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connect_debug_port u_ila_0/probe0 [get_nets [list {adc_pulse_period_dbg[0]} {adc_pulse_period_dbg[1]} {adc_pulse_period_dbg[2]} {adc_pulse_period_dbg[3]} {adc_pulse_period_dbg[4]} {adc_pulse_period_dbg[5]} {adc_pulse_period_dbg[6]} {adc_pulse_period_dbg[7]} {adc_pulse_period_dbg[8]} {adc_pulse_period_dbg[9]} {adc_pulse_period_dbg[10]} {adc_pulse_period_dbg[11]} {adc_pulse_period_dbg[12]} {adc_pulse_period_dbg[13]} {adc_pulse_period_dbg[14]} {adc_pulse_period_dbg[15]} {adc_pulse_period_dbg[16]} {adc_pulse_period_dbg[17]} {adc_pulse_period_dbg[18]} {adc_pulse_period_dbg[19]} {adc_pulse_period_dbg[20]} {adc_pulse_period_dbg[21]} {adc_pulse_period_dbg[22]} {adc_pulse_period_dbg[23]} {adc_pulse_period_dbg[24]} {adc_pulse_period_dbg[25]} {adc_pulse_period_dbg[26]} {adc_pulse_period_dbg[27]} {adc_pulse_period_dbg[28]} {adc_pulse_period_dbg[29]} {adc_pulse_period_dbg[30]} {adc_pulse_period_dbg[31]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
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set_property port_width 8 [get_debug_ports u_ila_0/probe1]
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connect_debug_port u_ila_0/probe1 [get_nets [list {finish_cnt[0]} {finish_cnt[1]} {finish_cnt[2]} {finish_cnt[3]} {finish_cnt[4]} {finish_cnt[5]} {finish_cnt[6]} {finish_cnt[7]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
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set_property port_width 16 [get_debug_ports u_ila_0/probe2]
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connect_debug_port u_ila_0/probe2 [get_nets [list {adc_pulse_num_dbg[0]} {adc_pulse_num_dbg[1]} {adc_pulse_num_dbg[2]} {adc_pulse_num_dbg[3]} {adc_pulse_num_dbg[4]} {adc_pulse_num_dbg[5]} {adc_pulse_num_dbg[6]} {adc_pulse_num_dbg[7]} {adc_pulse_num_dbg[8]} {adc_pulse_num_dbg[9]} {adc_pulse_num_dbg[10]} {adc_pulse_num_dbg[11]} {adc_pulse_num_dbg[12]} {adc_pulse_num_dbg[13]} {adc_pulse_num_dbg[14]} {adc_pulse_num_dbg[15]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
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set_property port_width 1 [get_debug_ports u_ila_0/probe3]
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connect_debug_port u_ila_0/probe3 [get_nets [list adc_rst_dbg]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
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set_property port_width 1 [get_debug_ports u_ila_0/probe4]
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connect_debug_port u_ila_0/probe4 [get_nets [list adc_start_dbg]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
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set_property port_width 1 [get_debug_ports u_ila_0/probe5]
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connect_debug_port u_ila_0/probe5 [get_nets [list finish_dbg]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
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set_property port_width 1 [get_debug_ports u_ila_0/probe6]
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connect_debug_port u_ila_0/probe6 [get_nets [list finish_pending]]
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create_debug_core u_ila_1 ila
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
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set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
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set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
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set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
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set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
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set_property port_width 1 [get_debug_ports u_ila_1/clk]
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connect_debug_port u_ila_1/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
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set_property port_width 2 [get_debug_ports u_ila_1/probe0]
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connect_debug_port u_ila_1/probe0 [get_nets [list {axis_mac0/rx_state[0]} {axis_mac0/rx_state[1]}]]
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create_debug_port u_ila_1 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
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set_property port_width 16 [get_debug_ports u_ila_1/probe1]
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connect_debug_port u_ila_1/probe1 [get_nets [list {axis_mac0/udp_rec_data_length[0]} {axis_mac0/udp_rec_data_length[1]} {axis_mac0/udp_rec_data_length[2]} {axis_mac0/udp_rec_data_length[3]} {axis_mac0/udp_rec_data_length[4]} {axis_mac0/udp_rec_data_length[5]} {axis_mac0/udp_rec_data_length[6]} {axis_mac0/udp_rec_data_length[7]} {axis_mac0/udp_rec_data_length[8]} {axis_mac0/udp_rec_data_length[9]} {axis_mac0/udp_rec_data_length[10]} {axis_mac0/udp_rec_data_length[11]} {axis_mac0/udp_rec_data_length[12]} {axis_mac0/udp_rec_data_length[13]} {axis_mac0/udp_rec_data_length[14]} {axis_mac0/udp_rec_data_length[15]}]]
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create_debug_port u_ila_1 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
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set_property port_width 96 [get_debug_ports u_ila_1/probe2]
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connect_debug_port u_ila_1/probe2 [get_nets [list {udp_ctrl_inst/cfg_bus_eth[0]} {udp_ctrl_inst/cfg_bus_eth[1]} {udp_ctrl_inst/cfg_bus_eth[2]} {udp_ctrl_inst/cfg_bus_eth[3]} {udp_ctrl_inst/cfg_bus_eth[4]} {udp_ctrl_inst/cfg_bus_eth[5]} {udp_ctrl_inst/cfg_bus_eth[6]} {udp_ctrl_inst/cfg_bus_eth[7]} {udp_ctrl_inst/cfg_bus_eth[8]} {udp_ctrl_inst/cfg_bus_eth[9]} {udp_ctrl_inst/cfg_bus_eth[10]} {udp_ctrl_inst/cfg_bus_eth[11]} {udp_ctrl_inst/cfg_bus_eth[12]} {udp_ctrl_inst/cfg_bus_eth[13]} {udp_ctrl_inst/cfg_bus_eth[14]} {udp_ctrl_inst/cfg_bus_eth[15]} {udp_ctrl_inst/cfg_bus_eth[16]} {udp_ctrl_inst/cfg_bus_eth[17]} {udp_ctrl_inst/cfg_bus_eth[18]} {udp_ctrl_inst/cfg_bus_eth[19]} {udp_ctrl_inst/cfg_bus_eth[20]} {udp_ctrl_inst/cfg_bus_eth[21]} {udp_ctrl_inst/cfg_bus_eth[22]} {udp_ctrl_inst/cfg_bus_eth[23]} {udp_ctrl_inst/cfg_bus_eth[24]} {udp_ctrl_inst/cfg_bus_eth[25]} {udp_ctrl_inst/cfg_bus_eth[26]} {udp_ctrl_inst/cfg_bus_eth[27]} {udp_ctrl_inst/cfg_bus_eth[28]} {udp_ctrl_inst/cfg_bus_eth[29]} {udp_ctrl_inst/cfg_bus_eth[30]} {udp_ctrl_inst/cfg_bus_eth[31]} {udp_ctrl_inst/cfg_bus_eth[32]} {udp_ctrl_inst/cfg_bus_eth[33]} {udp_ctrl_inst/cfg_bus_eth[34]} {udp_ctrl_inst/cfg_bus_eth[35]} {udp_ctrl_inst/cfg_bus_eth[36]} {udp_ctrl_inst/cfg_bus_eth[37]} {udp_ctrl_inst/cfg_bus_eth[38]} {udp_ctrl_inst/cfg_bus_eth[39]} {udp_ctrl_inst/cfg_bus_eth[40]} {udp_ctrl_inst/cfg_bus_eth[41]} {udp_ctrl_inst/cfg_bus_eth[42]} {udp_ctrl_inst/cfg_bus_eth[43]} {udp_ctrl_inst/cfg_bus_eth[44]} {udp_ctrl_inst/cfg_bus_eth[45]} {udp_ctrl_inst/cfg_bus_eth[46]} {udp_ctrl_inst/cfg_bus_eth[47]} {udp_ctrl_inst/cfg_bus_eth[48]} {udp_ctrl_inst/cfg_bus_eth[49]} {udp_ctrl_inst/cfg_bus_eth[50]} {udp_ctrl_inst/cfg_bus_eth[51]} {udp_ctrl_inst/cfg_bus_eth[52]} {udp_ctrl_inst/cfg_bus_eth[53]} {udp_ctrl_inst/cfg_bus_eth[54]} {udp_ctrl_inst/cfg_bus_eth[55]} {udp_ctrl_inst/cfg_bus_eth[56]} {udp_ctrl_inst/cfg_bus_eth[57]} {udp_ctrl_inst/cfg_bus_eth[58]} {udp_ctrl_inst/cfg_bus_eth[59]} {udp_ctrl_inst/cfg_bus_eth[60]} {udp_ctrl_inst/cfg_bus_eth[61]} {udp_ctrl_inst/cfg_bus_eth[62]} {udp_ctrl_inst/cfg_bus_eth[63]} {udp_ctrl_inst/cfg_bus_eth[64]} {udp_ctrl_inst/cfg_bus_eth[65]} {udp_ctrl_inst/cfg_bus_eth[66]} {udp_ctrl_inst/cfg_bus_eth[67]} {udp_ctrl_inst/cfg_bus_eth[68]} {udp_ctrl_inst/cfg_bus_eth[69]} {udp_ctrl_inst/cfg_bus_eth[70]} {udp_ctrl_inst/cfg_bus_eth[71]} {udp_ctrl_inst/cfg_bus_eth[72]} {udp_ctrl_inst/cfg_bus_eth[73]} {udp_ctrl_inst/cfg_bus_eth[74]} {udp_ctrl_inst/cfg_bus_eth[75]} {udp_ctrl_inst/cfg_bus_eth[76]} {udp_ctrl_inst/cfg_bus_eth[77]} {udp_ctrl_inst/cfg_bus_eth[78]} {udp_ctrl_inst/cfg_bus_eth[79]} {udp_ctrl_inst/cfg_bus_eth[80]} {udp_ctrl_inst/cfg_bus_eth[81]} {udp_ctrl_inst/cfg_bus_eth[82]} {udp_ctrl_inst/cfg_bus_eth[83]} {udp_ctrl_inst/cfg_bus_eth[84]} {udp_ctrl_inst/cfg_bus_eth[85]} {udp_ctrl_inst/cfg_bus_eth[86]} {udp_ctrl_inst/cfg_bus_eth[87]} {udp_ctrl_inst/cfg_bus_eth[88]} {udp_ctrl_inst/cfg_bus_eth[89]} {udp_ctrl_inst/cfg_bus_eth[90]} {udp_ctrl_inst/cfg_bus_eth[91]} {udp_ctrl_inst/cfg_bus_eth[92]} {udp_ctrl_inst/cfg_bus_eth[93]} {udp_ctrl_inst/cfg_bus_eth[94]} {udp_ctrl_inst/cfg_bus_eth[95]}]]
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|
||||||
create_debug_port u_ila_1 probe
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|
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
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set_property port_width 16 [get_debug_ports u_ila_1/probe3]
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|
||||||
connect_debug_port u_ila_1/probe3 [get_nets [list {axis_mac0/rx_payload_len[0]} {axis_mac0/rx_payload_len[1]} {axis_mac0/rx_payload_len[2]} {axis_mac0/rx_payload_len[3]} {axis_mac0/rx_payload_len[4]} {axis_mac0/rx_payload_len[5]} {axis_mac0/rx_payload_len[6]} {axis_mac0/rx_payload_len[7]} {axis_mac0/rx_payload_len[8]} {axis_mac0/rx_payload_len[9]} {axis_mac0/rx_payload_len[10]} {axis_mac0/rx_payload_len[11]} {axis_mac0/rx_payload_len[12]} {axis_mac0/rx_payload_len[13]} {axis_mac0/rx_payload_len[14]} {axis_mac0/rx_payload_len[15]}]]
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|
||||||
create_debug_port u_ila_1 probe
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|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
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|
||||||
set_property port_width 8 [get_debug_ports u_ila_1/probe4]
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||||||
connect_debug_port u_ila_1/probe4 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]}]]
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|
||||||
create_debug_port u_ila_1 probe
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|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
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||||||
set_property port_width 3 [get_debug_ports u_ila_1/probe5]
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||||||
connect_debug_port u_ila_1/probe5 [get_nets [list {udp_ctrl_inst/eth_state[0]} {udp_ctrl_inst/eth_state[1]} {udp_ctrl_inst/eth_state[2]}]]
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|
||||||
create_debug_port u_ila_1 probe
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|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
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|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe6]
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|
||||||
connect_debug_port u_ila_1/probe6 [get_nets [list axis_mac0/arp_found]]
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|
||||||
create_debug_port u_ila_1 probe
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|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
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|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe7]
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||||||
connect_debug_port u_ila_1/probe7 [get_nets [list udp_ctrl_inst/axis_hs]]
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|
||||||
create_debug_port u_ila_1 probe
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|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
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|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe8]
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||||||
connect_debug_port u_ila_1/probe8 [get_nets [list udp_ctrl_inst/busy_flag_eth]]
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|
||||||
create_debug_port u_ila_1 probe
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|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
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|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe9]
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|
||||||
connect_debug_port u_ila_1/probe9 [get_nets [list axis_mac0/m_axis_rx_tlast]]
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|
||||||
create_debug_port u_ila_1 probe
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|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe10]
|
|
||||||
connect_debug_port u_ila_1/probe10 [get_nets [list m_axis_rx_tlast]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe11]
|
|
||||||
connect_debug_port u_ila_1/probe11 [get_nets [list axis_mac0/m_axis_rx_tready]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe12]
|
|
||||||
connect_debug_port u_ila_1/probe12 [get_nets [list m_axis_rx_tready]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe13]
|
|
||||||
connect_debug_port u_ila_1/probe13 [get_nets [list axis_mac0/req_ready]]
|
|
||||||
create_debug_core u_ila_2 ila
|
|
||||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
|
|
||||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
|
|
||||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
|
|
||||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2]
|
|
||||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
|
|
||||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
|
|
||||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
|
|
||||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_2/clk]
|
|
||||||
connect_debug_port u_ila_2/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out1]]
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
|
|
||||||
set_property port_width 12 [get_debug_ports u_ila_2/probe0]
|
|
||||||
connect_debug_port u_ila_2/probe0 [get_nets [list {dac_pulse_height_dbg[0]} {dac_pulse_height_dbg[1]} {dac_pulse_height_dbg[2]} {dac_pulse_height_dbg[3]} {dac_pulse_height_dbg[4]} {dac_pulse_height_dbg[5]} {dac_pulse_height_dbg[6]} {dac_pulse_height_dbg[7]} {dac_pulse_height_dbg[8]} {dac_pulse_height_dbg[9]} {dac_pulse_height_dbg[10]} {dac_pulse_height_dbg[11]}]]
|
|
||||||
create_debug_port u_ila_2 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
|
|
||||||
set_property port_width 16 [get_debug_ports u_ila_2/probe1]
|
|
||||||
connect_debug_port u_ila_2/probe1 [get_nets [list {dac_pulse_num_dbg[0]} {dac_pulse_num_dbg[1]} {dac_pulse_num_dbg[2]} {dac_pulse_num_dbg[3]} {dac_pulse_num_dbg[4]} {dac_pulse_num_dbg[5]} {dac_pulse_num_dbg[6]} {dac_pulse_num_dbg[7]} {dac_pulse_num_dbg[8]} {dac_pulse_num_dbg[9]} {dac_pulse_num_dbg[10]} {dac_pulse_num_dbg[11]} {dac_pulse_num_dbg[12]} {dac_pulse_num_dbg[13]} {dac_pulse_num_dbg[14]} {dac_pulse_num_dbg[15]}]]
|
|
||||||
create_debug_port u_ila_2 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2]
|
|
||||||
set_property port_width 32 [get_debug_ports u_ila_2/probe2]
|
|
||||||
connect_debug_port u_ila_2/probe2 [get_nets [list {dac_pulse_period_dbg[0]} {dac_pulse_period_dbg[1]} {dac_pulse_period_dbg[2]} {dac_pulse_period_dbg[3]} {dac_pulse_period_dbg[4]} {dac_pulse_period_dbg[5]} {dac_pulse_period_dbg[6]} {dac_pulse_period_dbg[7]} {dac_pulse_period_dbg[8]} {dac_pulse_period_dbg[9]} {dac_pulse_period_dbg[10]} {dac_pulse_period_dbg[11]} {dac_pulse_period_dbg[12]} {dac_pulse_period_dbg[13]} {dac_pulse_period_dbg[14]} {dac_pulse_period_dbg[15]} {dac_pulse_period_dbg[16]} {dac_pulse_period_dbg[17]} {dac_pulse_period_dbg[18]} {dac_pulse_period_dbg[19]} {dac_pulse_period_dbg[20]} {dac_pulse_period_dbg[21]} {dac_pulse_period_dbg[22]} {dac_pulse_period_dbg[23]} {dac_pulse_period_dbg[24]} {dac_pulse_period_dbg[25]} {dac_pulse_period_dbg[26]} {dac_pulse_period_dbg[27]} {dac_pulse_period_dbg[28]} {dac_pulse_period_dbg[29]} {dac_pulse_period_dbg[30]} {dac_pulse_period_dbg[31]}]]
|
|
||||||
create_debug_port u_ila_2 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3]
|
|
||||||
set_property port_width 32 [get_debug_ports u_ila_2/probe3]
|
|
||||||
connect_debug_port u_ila_2/probe3 [get_nets [list {dac_pulse_width_dbg[0]} {dac_pulse_width_dbg[1]} {dac_pulse_width_dbg[2]} {dac_pulse_width_dbg[3]} {dac_pulse_width_dbg[4]} {dac_pulse_width_dbg[5]} {dac_pulse_width_dbg[6]} {dac_pulse_width_dbg[7]} {dac_pulse_width_dbg[8]} {dac_pulse_width_dbg[9]} {dac_pulse_width_dbg[10]} {dac_pulse_width_dbg[11]} {dac_pulse_width_dbg[12]} {dac_pulse_width_dbg[13]} {dac_pulse_width_dbg[14]} {dac_pulse_width_dbg[15]} {dac_pulse_width_dbg[16]} {dac_pulse_width_dbg[17]} {dac_pulse_width_dbg[18]} {dac_pulse_width_dbg[19]} {dac_pulse_width_dbg[20]} {dac_pulse_width_dbg[21]} {dac_pulse_width_dbg[22]} {dac_pulse_width_dbg[23]} {dac_pulse_width_dbg[24]} {dac_pulse_width_dbg[25]} {dac_pulse_width_dbg[26]} {dac_pulse_width_dbg[27]} {dac_pulse_width_dbg[28]} {dac_pulse_width_dbg[29]} {dac_pulse_width_dbg[30]} {dac_pulse_width_dbg[31]}]]
|
|
||||||
create_debug_port u_ila_2 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_2/probe4]
|
|
||||||
connect_debug_port u_ila_2/probe4 [get_nets [list dac_rst_dbg]]
|
|
||||||
create_debug_port u_ila_2 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_2/probe5]
|
|
||||||
connect_debug_port u_ila_2/probe5 [get_nets [list dac_start_dbg]]
|
|
||||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
|
||||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
|
||||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
|
||||||
connect_debug_port dbg_hub/clk [get_nets dac_clk]
|
|
||||||
@ -1,298 +0,0 @@
|
|||||||
`timescale 1 ns / 1 ns
|
|
||||||
|
|
||||||
module eth_ctrl_debug_top #(
|
|
||||||
parameter int unsigned DAC_DATA_WIDTH = 12
|
|
||||||
)(
|
|
||||||
input sys_clk_p,
|
|
||||||
input sys_clk_n,
|
|
||||||
input rst_n,
|
|
||||||
|
|
||||||
output [3:0] led,
|
|
||||||
|
|
||||||
output e_reset,
|
|
||||||
output e_mdc,
|
|
||||||
inout e_mdio,
|
|
||||||
|
|
||||||
output [3:0] rgmii_txd,
|
|
||||||
output rgmii_txctl,
|
|
||||||
output rgmii_txc,
|
|
||||||
input [3:0] rgmii_rxd,
|
|
||||||
input rgmii_rxctl,
|
|
||||||
input rgmii_rxc
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Internal GMII-side signals
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
wire [7:0] gmii_txd;
|
|
||||||
wire gmii_tx_en;
|
|
||||||
wire gmii_tx_er;
|
|
||||||
wire gmii_tx_clk;
|
|
||||||
wire gmii_crs;
|
|
||||||
wire gmii_col;
|
|
||||||
wire [7:0] gmii_rxd_i;
|
|
||||||
wire gmii_rx_dv;
|
|
||||||
wire gmii_rx_er;
|
|
||||||
wire gmii_rx_clk;
|
|
||||||
|
|
||||||
wire [31:0] pack_total_len;
|
|
||||||
|
|
||||||
wire e_rx_dv;
|
|
||||||
wire [7:0] e_rxd;
|
|
||||||
wire e_tx_en;
|
|
||||||
wire [7:0] e_txd;
|
|
||||||
wire e_rst_n;
|
|
||||||
wire sys_clk;
|
|
||||||
|
|
||||||
wire duplex_mode;
|
|
||||||
|
|
||||||
assign duplex_mode = 1'b1;
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// System clock buffer (200 MHz differential input)
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
IBUFDS sys_clk_ibufgds (
|
|
||||||
.O (sys_clk),
|
|
||||||
.I (sys_clk_p),
|
|
||||||
.IB (sys_clk_n)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// IDELAYCTRL
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
(* IODELAY_GROUP = "rgmii_idelay_group" *)
|
|
||||||
IDELAYCTRL IDELAYCTRL_inst (
|
|
||||||
.RDY (),
|
|
||||||
.REFCLK (sys_clk),
|
|
||||||
.RST (1'b0)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Generated clocks for controller
|
|
||||||
// Need to create this IP in Vivado:
|
|
||||||
// input : 200 MHz
|
|
||||||
// output0: 130 MHz
|
|
||||||
// output1: 65 MHz
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
wire dac_clk;
|
|
||||||
wire adc_clk;
|
|
||||||
wire clk_wiz_locked;
|
|
||||||
|
|
||||||
clk_wiz_ctrl_inst clk_wiz_ctrl_inst (
|
|
||||||
.clk_in1 (sys_clk),
|
|
||||||
.reset (~rst_n),
|
|
||||||
.clk_out1 (dac_clk), // 130 MHz
|
|
||||||
.clk_out2 (adc_clk), // 65 MHz
|
|
||||||
.locked (clk_wiz_locked)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// GMII <-> RGMII conversion
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
util_gmii_to_rgmii util_gmii_to_rgmii_m0 (
|
|
||||||
.reset (1'b0),
|
|
||||||
.rgmii_td (rgmii_txd),
|
|
||||||
.rgmii_tx_ctl (rgmii_txctl),
|
|
||||||
.rgmii_txc (rgmii_txc),
|
|
||||||
.rgmii_rd (rgmii_rxd),
|
|
||||||
.rgmii_rx_ctl (rgmii_rxctl),
|
|
||||||
.gmii_rx_clk (gmii_rx_clk),
|
|
||||||
.gmii_txd (e_txd),
|
|
||||||
.gmii_tx_en (e_tx_en),
|
|
||||||
.gmii_tx_er (1'b0),
|
|
||||||
.gmii_tx_clk (gmii_tx_clk),
|
|
||||||
.gmii_crs (gmii_crs),
|
|
||||||
.gmii_col (gmii_col),
|
|
||||||
.gmii_rxd (gmii_rxd_i),
|
|
||||||
.rgmii_rxc (rgmii_rxc),
|
|
||||||
.gmii_rx_dv (gmii_rx_dv),
|
|
||||||
.gmii_rx_er (gmii_rx_er),
|
|
||||||
.speed_selection (2'b10),
|
|
||||||
.duplex_mode (duplex_mode)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// GMII arbitration / adaptation
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
gmii_arbi arbi_inst (
|
|
||||||
.clk (gmii_tx_clk),
|
|
||||||
.rst_n (rst_n),
|
|
||||||
.speed (2'b10),
|
|
||||||
.link (1'b1),
|
|
||||||
.pack_total_len (pack_total_len),
|
|
||||||
.e_rst_n (e_rst_n),
|
|
||||||
.gmii_rx_dv (gmii_rx_dv),
|
|
||||||
.gmii_rxd (gmii_rxd_i),
|
|
||||||
.gmii_tx_en (gmii_tx_en),
|
|
||||||
.gmii_txd (gmii_txd),
|
|
||||||
.e_rx_dv (e_rx_dv),
|
|
||||||
.e_rxd (e_rxd),
|
|
||||||
.e_tx_en (e_tx_en),
|
|
||||||
.e_txd (e_txd)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// axis_mac interface
|
|
||||||
// RX stream from Ethernet goes into controller
|
|
||||||
// TX stream is unused for now
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
wire req_ready;
|
|
||||||
|
|
||||||
reg send_req;
|
|
||||||
reg [15:0] data_length;
|
|
||||||
|
|
||||||
reg [7:0] s_axis_tx_tdata;
|
|
||||||
reg s_axis_tx_tvalid;
|
|
||||||
wire s_axis_tx_tready;
|
|
||||||
reg s_axis_tx_tlast;
|
|
||||||
|
|
||||||
(* MARK_DEBUG="true" *) wire [7:0] m_axis_rx_tdata;
|
|
||||||
(* MARK_DEBUG="true" *) wire m_axis_rx_tvalid;
|
|
||||||
(* MARK_DEBUG="true" *) wire m_axis_rx_tlast;
|
|
||||||
(* MARK_DEBUG="true" *) wire m_axis_rx_tready;
|
|
||||||
|
|
||||||
// Always ready to accept RX payload bytes
|
|
||||||
assign m_axis_rx_tready = 1'b1;
|
|
||||||
|
|
||||||
// TX disabled
|
|
||||||
always @(*) begin
|
|
||||||
send_req = 1'b0;
|
|
||||||
data_length = 16'd0;
|
|
||||||
s_axis_tx_tdata = 8'd0;
|
|
||||||
s_axis_tx_tvalid= 1'b0;
|
|
||||||
s_axis_tx_tlast = 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
axis_mac axis_mac0 (
|
|
||||||
.gmii_tx_clk (gmii_tx_clk),
|
|
||||||
.gmii_rx_clk (gmii_rx_clk),
|
|
||||||
.rst_n (e_rst_n),
|
|
||||||
|
|
||||||
.gmii_rx_dv (e_rx_dv),
|
|
||||||
.gmii_rxd (e_rxd),
|
|
||||||
.gmii_tx_en (gmii_tx_en),
|
|
||||||
.gmii_txd (gmii_txd),
|
|
||||||
|
|
||||||
.send_req (send_req),
|
|
||||||
.data_length (data_length),
|
|
||||||
.req_ready (req_ready),
|
|
||||||
|
|
||||||
.s_axis_tx_tdata (s_axis_tx_tdata),
|
|
||||||
.s_axis_tx_tvalid (s_axis_tx_tvalid),
|
|
||||||
.s_axis_tx_tready (s_axis_tx_tready),
|
|
||||||
.s_axis_tx_tlast (s_axis_tx_tlast),
|
|
||||||
|
|
||||||
.m_axis_rx_tdata (m_axis_rx_tdata),
|
|
||||||
.m_axis_rx_tvalid (m_axis_rx_tvalid),
|
|
||||||
.m_axis_rx_tready (m_axis_rx_tready),
|
|
||||||
.m_axis_rx_tlast (m_axis_rx_tlast)
|
|
||||||
);
|
|
||||||
|
|
||||||
// PHY reset helper from your original example
|
|
||||||
reset reset_m0 (
|
|
||||||
.clk (sys_clk),
|
|
||||||
.key1 (rst_n),
|
|
||||||
.rst_n (e_reset)
|
|
||||||
);
|
|
||||||
|
|
||||||
// MDIO lines are not driven here yet
|
|
||||||
assign e_mdc = 1'b0;
|
|
||||||
assign e_mdio = 1'bz;
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Controller reset
|
|
||||||
// Use both external reset and clk_wiz lock
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
wire ctrl_rst_n = rst_n & clk_wiz_locked;
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Debug finish generator
|
|
||||||
//
|
|
||||||
// After each adc_start pulse generates one finish pulse after some delay.
|
|
||||||
// This is just for first bring-up so the controller can leave busy state
|
|
||||||
// If you don't want this, replace with:
|
|
||||||
// wire finish_dbg = 1'b0;
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
(* MARK_DEBUG="true" *) logic finish_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) logic [7:0] finish_cnt;
|
|
||||||
(* MARK_DEBUG="true" *) logic finish_pending;
|
|
||||||
|
|
||||||
// Controller outputs to debug
|
|
||||||
(* MARK_DEBUG="true" *) wire [31:0] dac_pulse_width_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire [31:0] dac_pulse_period_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire [DAC_DATA_WIDTH-1:0] dac_pulse_height_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire [15:0] dac_pulse_num_dbg;
|
|
||||||
|
|
||||||
(* MARK_DEBUG="true" *) wire [31:0] adc_pulse_period_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire [15:0] adc_pulse_num_dbg;
|
|
||||||
|
|
||||||
(* MARK_DEBUG="true" *) wire dac_start_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire adc_start_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire dac_rst_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire adc_rst_dbg;
|
|
||||||
|
|
||||||
always_ff @(posedge adc_clk or negedge ctrl_rst_n) begin
|
|
||||||
if (!ctrl_rst_n) begin
|
|
||||||
finish_dbg <= 1'b0;
|
|
||||||
finish_cnt <= 8'd0;
|
|
||||||
finish_pending <= 1'b0;
|
|
||||||
end else begin
|
|
||||||
finish_dbg <= 1'b0;
|
|
||||||
|
|
||||||
if (adc_start_dbg) begin
|
|
||||||
finish_pending <= 1'b1;
|
|
||||||
finish_cnt <= 8'd80;
|
|
||||||
end else if (finish_pending) begin
|
|
||||||
if (finish_cnt == 8'd0) begin
|
|
||||||
finish_dbg <= 1'b1;
|
|
||||||
finish_pending <= 1'b0;
|
|
||||||
end else begin
|
|
||||||
finish_cnt <= finish_cnt - 8'd1;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Controller
|
|
||||||
// ETH domain = gmii_rx_clk, because RX AXI master comes from axis_mac RX side
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
control #(
|
|
||||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
|
|
||||||
) udp_ctrl_inst (
|
|
||||||
.eth_clk_in (gmii_rx_clk),
|
|
||||||
.dac_clk_in (dac_clk),
|
|
||||||
.adc_clk_in (adc_clk),
|
|
||||||
.rst_n (ctrl_rst_n),
|
|
||||||
|
|
||||||
.s_axis_tdata (m_axis_rx_tdata),
|
|
||||||
.s_axis_tvalid (m_axis_rx_tvalid),
|
|
||||||
.s_axis_tready (), // controller internally always ready in current version
|
|
||||||
.s_axis_tlast (m_axis_rx_tlast),
|
|
||||||
|
|
||||||
.finish (finish_dbg),
|
|
||||||
|
|
||||||
.dac_pulse_width (dac_pulse_width_dbg),
|
|
||||||
.dac_pulse_period (dac_pulse_period_dbg),
|
|
||||||
.dac_pulse_height (dac_pulse_height_dbg),
|
|
||||||
.dac_pulse_num (dac_pulse_num_dbg),
|
|
||||||
|
|
||||||
.adc_pulse_period (adc_pulse_period_dbg),
|
|
||||||
.adc_pulse_num (adc_pulse_num_dbg),
|
|
||||||
|
|
||||||
.dac_start (dac_start_dbg),
|
|
||||||
.adc_start (adc_start_dbg),
|
|
||||||
|
|
||||||
.dac_rst (dac_rst_dbg),
|
|
||||||
.adc_rst (adc_rst_dbg)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Simple LED status
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
assign led[0] = clk_wiz_locked;
|
|
||||||
assign led[1] = m_axis_rx_tvalid;
|
|
||||||
assign led[2] = dac_start_dbg;
|
|
||||||
assign led[3] = adc_rst_dbg;
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
@ -1,689 +0,0 @@
|
|||||||
{
|
|
||||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
|
||||||
"ip_inst": {
|
|
||||||
"xci_name": "clk_wiz_ctrl_inst",
|
|
||||||
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
|
|
||||||
"ip_revision": "16",
|
|
||||||
"gen_directory": "../../../../eth_ctrl_debug_top.gen/sources_1/ip/clk_wiz_ctrl_inst",
|
|
||||||
"parameters": {
|
|
||||||
"component_parameters": {
|
|
||||||
"Component_Name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PRIM_IN_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKIN1_JITTER_PS": [ { "value": "50.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"NUM_OUT_CLKS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "130.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "7.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT1_DIVIDE": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT1_JITTER": [ { "value": "102.676", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT1_PHASE_ERROR": [ { "value": "87.159", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT2_JITTER": [ { "value": "117.878", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT2_PHASE_ERROR": [ { "value": "87.159", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
|
||||||
},
|
|
||||||
"model_parameters": {
|
|
||||||
"C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"c_component_name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PRIM_IN_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_USE_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_NUM_OUT_CLKS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_INCLK_SUM_ROW1": [ { "value": "__primary_________200.000____________0.010", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__130.00000______0.000______50.0______102.676_____87.159", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__65.00000______0.000______50.0______117.878_____87.159", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "130.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "130.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_OUT_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
|
||||||
"C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "7.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKIN1_JITTER_PS": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE2_AUTO": [ { "value": "2.0", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE3_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE4_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE5_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE6_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE7_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "130.00000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_D_MAX": [ { "value": "80.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_VCO_MAX": [ { "value": "1200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
|
||||||
},
|
|
||||||
"project_parameters": {
|
|
||||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
|
||||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
|
||||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
|
||||||
"DEVICE": [ { "value": "xc7a35t" } ],
|
|
||||||
"PACKAGE": [ { "value": "fgg484" } ],
|
|
||||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
|
||||||
"SILICON_REVISION": [ { "value": "" } ],
|
|
||||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
|
||||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
|
||||||
"STATIC_POWER": [ { "value": "" } ],
|
|
||||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
|
||||||
},
|
|
||||||
"runtime_parameters": {
|
|
||||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
|
||||||
"IPREVISION": [ { "value": "16" } ],
|
|
||||||
"MANAGED": [ { "value": "TRUE" } ],
|
|
||||||
"OUTPUTDIR": [ { "value": "../../../../eth_ctrl_debug_top.gen/sources_1/ip/clk_wiz_ctrl_inst" } ],
|
|
||||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
|
||||||
"SHAREDDIR": [ { "value": "." } ],
|
|
||||||
"SWVERSION": [ { "value": "2025.1" } ],
|
|
||||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"boundary": {
|
|
||||||
"ports": {
|
|
||||||
"reset": [ { "direction": "in", "driver_value": "0" } ],
|
|
||||||
"clk_in1": [ { "direction": "in" } ],
|
|
||||||
"clk_out1": [ { "direction": "out" } ],
|
|
||||||
"clk_out2": [ { "direction": "out" } ],
|
|
||||||
"locked": [ { "direction": "out" } ]
|
|
||||||
},
|
|
||||||
"interfaces": {
|
|
||||||
"reset": {
|
|
||||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
|
||||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
|
||||||
"mode": "slave",
|
|
||||||
"parameters": {
|
|
||||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
|
||||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ],
|
|
||||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
|
||||||
},
|
|
||||||
"port_maps": {
|
|
||||||
"RST": [ { "physical_name": "reset" } ]
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"clock_CLK_IN1": {
|
|
||||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
|
||||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
|
||||||
"mode": "slave",
|
|
||||||
"parameters": {
|
|
||||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
|
|
||||||
},
|
|
||||||
"port_maps": {
|
|
||||||
"CLK_IN1": [ { "physical_name": "clk_in1" } ]
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"clock_CLK_OUT1": {
|
|
||||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
|
||||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
|
||||||
"mode": "master",
|
|
||||||
"parameters": {
|
|
||||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
|
||||||
},
|
|
||||||
"port_maps": {
|
|
||||||
"CLK_OUT1": [ { "physical_name": "clk_out1" } ]
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"clock_CLK_OUT2": {
|
|
||||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
|
||||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
|
||||||
"mode": "master",
|
|
||||||
"parameters": {
|
|
||||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
|
||||||
},
|
|
||||||
"port_maps": {
|
|
||||||
"CLK_OUT2": [ { "physical_name": "clk_out2" } ]
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@ -1,62 +0,0 @@
|
|||||||
# Системный контроллер
|
|
||||||
|
|
||||||
Контроллер принимает входные пакеты udp с ethernet, передаваемые по axi stream, и выполняет настройку выходных регистров в соотвествии с содержимым этого пакета, а также синхронизирует сигналы между тремя clock domains - есть clk от ethernet, clk для ЦАП и clk для АЦП
|
|
||||||
|
|
||||||
## Список параметров:
|
|
||||||
- dac_data_width - битность данных ЦАП, <= 16bit
|
|
||||||
|
|
||||||
## Список входных портов:
|
|
||||||
- eth_clk_in - базовая входная частота
|
|
||||||
- dac_clk_in - входная частота ЦАП
|
|
||||||
- adc_clk_in - входная частота АЦП
|
|
||||||
- rst_n - общий reset
|
|
||||||
- s_axis [8 bit] - AXI stream slave для приема данных от ethernet udp (уже разобранный payload по байтам) - домен eth_clk
|
|
||||||
- finish - сигнал окончания приема данных с АЦП, домен adc_clk !
|
|
||||||
|
|
||||||
## Список выходных портов:
|
|
||||||
- dac_pulse_width[31:0] - выход pulse_width в домене dac_clk
|
|
||||||
- dac_pulse_period[31:0] - выход pulse_period в домене dac_clk
|
|
||||||
- dac_pulse_height[dac_data_width-1:0] - выход pulse_height в домене dac_clk
|
|
||||||
- dac_pulse_num[15:0] - выход pulse_num в домене dac_clk
|
|
||||||
---
|
|
||||||
- adc_pulse_period[31:0] - выход pulse_period в домене adc_clk
|
|
||||||
- adc_pulse_num[15:0] - выход pulse_num в домене adc_clk
|
|
||||||
---
|
|
||||||
- dac_start - start в домене dac_clk
|
|
||||||
- adc_start - start в домене adc_clk
|
|
||||||
---
|
|
||||||
- dac_rst - rst в домене dac_clk
|
|
||||||
- adc_rst - rst в домене adc_clk
|
|
||||||
|
|
||||||
## Логика работы:
|
|
||||||
по умолчанию после инициализации блок встает в состояние ожидания (*idle*), и становится *ready* для приема данных по axis.
|
|
||||||
далее ждет контрольный пакет. всего есть 3 вариации контрольных пакетов (в любом порядке), получаемых по axi stream:
|
|
||||||
```
|
|
||||||
8'b00001111 - soft reset
|
|
||||||
8'b11110000 - start
|
|
||||||
8'b10001000 - set_data
|
|
||||||
```
|
|
||||||
|
|
||||||
*soft reset* отправляет пульс rst на dac_rst и adc_rst, синхронизировав пульсы в их доменах. при этом сброс самого контроллера не происходит, значения остаются как и были
|
|
||||||
|
|
||||||
*start* отправляет пульс start на dac_start и adc_start в их доменах. при этом после этого блок перестает быть ready и ждет, пока не придет пульс finish, после этого он возвращается снова в *idle* состояние
|
|
||||||
|
|
||||||
*set_data* значит, что следующие 96 бит = 12*8 байт, пришедшии по axis - это конфигурационная информация и ее нужно записать в внутренний регистр на 96 бит.
|
|
||||||
|
|
||||||
конфигурационный регистр на 96 бит делится так:
|
|
||||||
```
|
|
||||||
reg[31:0] - pulse_width
|
|
||||||
reg[63:32] - pulse_period
|
|
||||||
reg[79:64] - pulse_num
|
|
||||||
reg[79+dac_data_width:80] - pulse_height
|
|
||||||
```
|
|
||||||
|
|
||||||
соотвественно эти записанные значения выставляются на соотвествующие выходные сигналы в доменах dac_clk и adc_clk. выходы обновляются каждый раз, когда происходит set_data, и сигналы сохраняют своё значение до следующего set_data.
|
|
||||||
|
|
||||||
## Симуляция
|
|
||||||
Тесты запускаются автоматически через make.
|
|
||||||
```
|
|
||||||
cd tests
|
|
||||||
make sim
|
|
||||||
```
|
|
||||||
Должно выдать "All tests done" в конце симуляции.
|
|
||||||
@ -1,462 +0,0 @@
|
|||||||
module control #(
|
|
||||||
parameter int unsigned DAC_DATA_WIDTH = 12
|
|
||||||
) (
|
|
||||||
input logic eth_clk_in,
|
|
||||||
input logic dac_clk_in,
|
|
||||||
input logic adc_clk_in,
|
|
||||||
input logic rst_n,
|
|
||||||
|
|
||||||
// AXI stream slave, eth_clk_in domain
|
|
||||||
input logic [7:0] s_axis_tdata,
|
|
||||||
input logic s_axis_tvalid,
|
|
||||||
output logic s_axis_tready,
|
|
||||||
input logic s_axis_tlast,
|
|
||||||
|
|
||||||
// adc_clk_in domain
|
|
||||||
input logic finish,
|
|
||||||
|
|
||||||
// dac_clk_in domain outputs
|
|
||||||
output logic [31:0] dac_pulse_width,
|
|
||||||
output logic [31:0] dac_pulse_period,
|
|
||||||
output logic [DAC_DATA_WIDTH-1:0] dac_pulse_height,
|
|
||||||
output logic [15:0] dac_pulse_num,
|
|
||||||
|
|
||||||
// adc_clk_in domain outputs
|
|
||||||
output logic [31:0] adc_pulse_period,
|
|
||||||
output logic [15:0] adc_pulse_num,
|
|
||||||
|
|
||||||
// pulse outputs
|
|
||||||
output logic dac_start,
|
|
||||||
output logic adc_start,
|
|
||||||
output logic dac_rst,
|
|
||||||
output logic adc_rst
|
|
||||||
);
|
|
||||||
|
|
||||||
// static checks
|
|
||||||
initial begin
|
|
||||||
if (DAC_DATA_WIDTH > 16) begin
|
|
||||||
$error("DAC_DATA_WIDTH must be <= 16");
|
|
||||||
end
|
|
||||||
if (DAC_DATA_WIDTH == 0) begin
|
|
||||||
$error("DAC_DATA_WIDTH must be > 0");
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// command constants
|
|
||||||
localparam logic [7:0] CMD_SOFT_RESET = 8'h0F;
|
|
||||||
localparam logic [7:0] CMD_START = 8'hF0;
|
|
||||||
localparam logic [7:0] CMD_SET_DATA = 8'h88;
|
|
||||||
|
|
||||||
// reset synchronizers: async assert, sync deassert in each domain
|
|
||||||
logic eth_rst_ff1, eth_rst_ff2;
|
|
||||||
logic dac_rst_ff1, dac_rst_ff2;
|
|
||||||
logic adc_rst_ff1, adc_rst_ff2;
|
|
||||||
|
|
||||||
logic eth_rst;
|
|
||||||
logic dac_rst_int;
|
|
||||||
logic adc_rst_int;
|
|
||||||
|
|
||||||
always_ff @(posedge eth_clk_in or negedge rst_n) begin
|
|
||||||
if (!rst_n) begin
|
|
||||||
eth_rst_ff1 <= 1'b1;
|
|
||||||
eth_rst_ff2 <= 1'b1;
|
|
||||||
end else begin
|
|
||||||
eth_rst_ff1 <= 1'b0;
|
|
||||||
eth_rst_ff2 <= eth_rst_ff1;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always_ff @(posedge dac_clk_in or negedge rst_n) begin
|
|
||||||
if (!rst_n) begin
|
|
||||||
dac_rst_ff1 <= 1'b1;
|
|
||||||
dac_rst_ff2 <= 1'b1;
|
|
||||||
end else begin
|
|
||||||
dac_rst_ff1 <= 1'b0;
|
|
||||||
dac_rst_ff2 <= dac_rst_ff1;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always_ff @(posedge adc_clk_in or negedge rst_n) begin
|
|
||||||
if (!rst_n) begin
|
|
||||||
adc_rst_ff1 <= 1'b1;
|
|
||||||
adc_rst_ff2 <= 1'b1;
|
|
||||||
end else begin
|
|
||||||
adc_rst_ff1 <= 1'b0;
|
|
||||||
adc_rst_ff2 <= adc_rst_ff1;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
assign eth_rst = eth_rst_ff2;
|
|
||||||
assign dac_rst_int = dac_rst_ff2;
|
|
||||||
assign adc_rst_int = adc_rst_ff2;
|
|
||||||
|
|
||||||
// axi stream is always accepted. If packet is not needed, it is discarded.
|
|
||||||
assign s_axis_tready = 1'b1;
|
|
||||||
|
|
||||||
(* MARK_DEBUG="true" *) wire axis_hs = s_axis_tvalid & s_axis_tready;
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Shared 96-bit config bus in ETH domain
|
|
||||||
//
|
|
||||||
// Byte order for SET_DATA payload, little-endian:
|
|
||||||
// payload byte 0 -> cfg_bus_eth[7:0]
|
|
||||||
// payload byte 1 -> cfg_bus_eth[15:8]
|
|
||||||
// ...etc...
|
|
||||||
// payload byte 11 -> cfg_bus_eth[95:88]
|
|
||||||
//
|
|
||||||
// Field layout inside cfg_bus_eth:
|
|
||||||
// [31:0] pulse_width
|
|
||||||
// [63:32] pulse_period
|
|
||||||
// [79:64] pulse_num
|
|
||||||
// [95:80] pulse_height_raw[15:0]
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
(* MARK_DEBUG="true" *) logic [95:0] cfg_bus_eth;
|
|
||||||
logic [95:0] cfg_shift_eth;
|
|
||||||
|
|
||||||
// ETH-domain parser and control
|
|
||||||
typedef enum logic [2:0] {
|
|
||||||
ST_IDLE = 3'd0,
|
|
||||||
ST_RECV_CFG = 3'd1,
|
|
||||||
ST_WAIT_CFG_ACK = 3'd2,
|
|
||||||
ST_DISCARD = 3'd3
|
|
||||||
} eth_state_t;
|
|
||||||
|
|
||||||
(* MARK_DEBUG="true" *) eth_state_t eth_state;
|
|
||||||
|
|
||||||
logic [3:0] cfg_byte_cnt;
|
|
||||||
|
|
||||||
// Busy flag: set by START command, cleared by finish event from ADC domain
|
|
||||||
(* MARK_DEBUG="true" *) logic busy_flag_eth;
|
|
||||||
|
|
||||||
// Pending ACKs for config delivery
|
|
||||||
logic cfg_wait_dac_ack;
|
|
||||||
logic cfg_wait_adc_ack;
|
|
||||||
|
|
||||||
// Event toggles ETH -> DAC/ADC
|
|
||||||
logic start_toggle_eth;
|
|
||||||
logic rst_toggle_eth;
|
|
||||||
|
|
||||||
// Config request toggles ETH -> DAC/ADC
|
|
||||||
logic cfg_req_toggle_dac_eth;
|
|
||||||
logic cfg_req_toggle_adc_eth;
|
|
||||||
|
|
||||||
// ACK toggles DAC/ADC -> ETH
|
|
||||||
logic cfg_ack_toggle_dac;
|
|
||||||
logic cfg_ack_toggle_adc;
|
|
||||||
|
|
||||||
(* ASYNC_REG = "TRUE" *) logic cfg_ack_toggle_dac_meta, cfg_ack_toggle_dac_sync, cfg_ack_toggle_dac_sync_d;
|
|
||||||
(* ASYNC_REG = "TRUE" *) logic cfg_ack_toggle_adc_meta, cfg_ack_toggle_adc_sync, cfg_ack_toggle_adc_sync_d;
|
|
||||||
|
|
||||||
wire cfg_ack_pulse_dac_eth = cfg_ack_toggle_dac_sync ^ cfg_ack_toggle_dac_sync_d;
|
|
||||||
wire cfg_ack_pulse_adc_eth = cfg_ack_toggle_adc_sync ^ cfg_ack_toggle_adc_sync_d;
|
|
||||||
|
|
||||||
always_ff @(posedge eth_clk_in or posedge eth_rst) begin
|
|
||||||
if (eth_rst) begin
|
|
||||||
cfg_ack_toggle_dac_meta <= 1'b0;
|
|
||||||
cfg_ack_toggle_dac_sync <= 1'b0;
|
|
||||||
cfg_ack_toggle_dac_sync_d <= 1'b0;
|
|
||||||
|
|
||||||
cfg_ack_toggle_adc_meta <= 1'b0;
|
|
||||||
cfg_ack_toggle_adc_sync <= 1'b0;
|
|
||||||
cfg_ack_toggle_adc_sync_d <= 1'b0;
|
|
||||||
end else begin
|
|
||||||
cfg_ack_toggle_dac_meta <= cfg_ack_toggle_dac;
|
|
||||||
cfg_ack_toggle_dac_sync <= cfg_ack_toggle_dac_meta;
|
|
||||||
cfg_ack_toggle_dac_sync_d <= cfg_ack_toggle_dac_sync;
|
|
||||||
|
|
||||||
cfg_ack_toggle_adc_meta <= cfg_ack_toggle_adc;
|
|
||||||
cfg_ack_toggle_adc_sync <= cfg_ack_toggle_adc_meta;
|
|
||||||
cfg_ack_toggle_adc_sync_d <= cfg_ack_toggle_adc_sync;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// finish event: ADC -> ETH via toggle CDC
|
|
||||||
logic finish_toggle_adc;
|
|
||||||
logic finish_meta_eth, finish_sync_eth, finish_sync_eth_d;
|
|
||||||
|
|
||||||
wire finish_pulse_eth = finish_sync_eth ^ finish_sync_eth_d;
|
|
||||||
|
|
||||||
always_ff @(posedge adc_clk_in or posedge adc_rst_int) begin
|
|
||||||
if (adc_rst_int) begin
|
|
||||||
finish_toggle_adc <= 1'b0;
|
|
||||||
end else if (finish) begin
|
|
||||||
finish_toggle_adc <= ~finish_toggle_adc;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always_ff @(posedge eth_clk_in or posedge eth_rst) begin
|
|
||||||
if (eth_rst) begin
|
|
||||||
finish_meta_eth <= 1'b0;
|
|
||||||
finish_sync_eth <= 1'b0;
|
|
||||||
finish_sync_eth_d <= 1'b0;
|
|
||||||
end else begin
|
|
||||||
finish_meta_eth <= finish_toggle_adc;
|
|
||||||
finish_sync_eth <= finish_meta_eth;
|
|
||||||
finish_sync_eth_d <= finish_sync_eth;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// ETH FSM
|
|
||||||
always_ff @(posedge eth_clk_in or posedge eth_rst) begin
|
|
||||||
if (eth_rst) begin
|
|
||||||
eth_state <= ST_IDLE;
|
|
||||||
cfg_byte_cnt <= '0;
|
|
||||||
cfg_shift_eth <= '0;
|
|
||||||
cfg_bus_eth <= '0;
|
|
||||||
|
|
||||||
busy_flag_eth <= 1'b0;
|
|
||||||
|
|
||||||
start_toggle_eth <= 1'b0;
|
|
||||||
rst_toggle_eth <= 1'b0;
|
|
||||||
|
|
||||||
cfg_req_toggle_dac_eth <= 1'b0;
|
|
||||||
cfg_req_toggle_adc_eth <= 1'b0;
|
|
||||||
|
|
||||||
cfg_wait_dac_ack <= 1'b0;
|
|
||||||
cfg_wait_adc_ack <= 1'b0;
|
|
||||||
end else begin
|
|
||||||
// finish always clears busy
|
|
||||||
if (finish_pulse_eth) begin
|
|
||||||
busy_flag_eth <= 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
// config acks
|
|
||||||
if (cfg_ack_pulse_dac_eth) begin
|
|
||||||
cfg_wait_dac_ack <= 1'b0;
|
|
||||||
end
|
|
||||||
if (cfg_ack_pulse_adc_eth) begin
|
|
||||||
cfg_wait_adc_ack <= 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
case (eth_state)
|
|
||||||
ST_IDLE: begin
|
|
||||||
cfg_byte_cnt <= '0;
|
|
||||||
cfg_shift_eth <= cfg_shift_eth;
|
|
||||||
|
|
||||||
if (axis_hs) begin
|
|
||||||
// if busy, drop the whole packet
|
|
||||||
if (busy_flag_eth) begin
|
|
||||||
if (!s_axis_tlast) begin
|
|
||||||
eth_state <= ST_DISCARD;
|
|
||||||
end
|
|
||||||
end else begin
|
|
||||||
unique case (s_axis_tdata)
|
|
||||||
CMD_SOFT_RESET: begin
|
|
||||||
rst_toggle_eth <= ~rst_toggle_eth;
|
|
||||||
end
|
|
||||||
|
|
||||||
CMD_START: begin
|
|
||||||
start_toggle_eth <= ~start_toggle_eth;
|
|
||||||
busy_flag_eth <= 1'b1;
|
|
||||||
end
|
|
||||||
|
|
||||||
CMD_SET_DATA: begin
|
|
||||||
// expect exactly 12 bytes after command
|
|
||||||
if (s_axis_tlast) begin
|
|
||||||
// no payload, invalid packet
|
|
||||||
eth_state <= ST_IDLE;
|
|
||||||
end else begin
|
|
||||||
cfg_byte_cnt <= 4'd0;
|
|
||||||
cfg_shift_eth <= '0;
|
|
||||||
eth_state <= ST_RECV_CFG;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
default: begin
|
|
||||||
// unknown command: discard packet remainder if any
|
|
||||||
if (!s_axis_tlast) begin
|
|
||||||
eth_state <= ST_DISCARD;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
ST_RECV_CFG: begin
|
|
||||||
if (axis_hs) begin
|
|
||||||
// little endian packing
|
|
||||||
cfg_shift_eth[cfg_byte_cnt*8 +: 8] <= s_axis_tdata;
|
|
||||||
|
|
||||||
if (cfg_byte_cnt == 4'd11) begin
|
|
||||||
// this must be the final payload byte
|
|
||||||
if (s_axis_tlast) begin
|
|
||||||
cfg_bus_eth <= {s_axis_tdata, cfg_shift_eth[87:0]};
|
|
||||||
cfg_req_toggle_dac_eth <= ~cfg_req_toggle_dac_eth;
|
|
||||||
cfg_req_toggle_adc_eth <= ~cfg_req_toggle_adc_eth;
|
|
||||||
cfg_wait_dac_ack <= 1'b1;
|
|
||||||
cfg_wait_adc_ack <= 1'b1;
|
|
||||||
eth_state <= ST_WAIT_CFG_ACK;
|
|
||||||
end else begin
|
|
||||||
// too many bytes in packet
|
|
||||||
eth_state <= ST_DISCARD;
|
|
||||||
end
|
|
||||||
end else begin
|
|
||||||
// early tlast means packet too short!!
|
|
||||||
if (s_axis_tlast) begin
|
|
||||||
eth_state <= ST_IDLE;
|
|
||||||
end else begin
|
|
||||||
cfg_byte_cnt <= cfg_byte_cnt + 4'd1;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
ST_WAIT_CFG_ACK: begin
|
|
||||||
// any incoming packet while waiting ack is discarded
|
|
||||||
if (cfg_ack_pulse_dac_eth || cfg_ack_pulse_adc_eth) begin
|
|
||||||
if ((~cfg_wait_dac_ack || cfg_ack_pulse_dac_eth) &&
|
|
||||||
(~cfg_wait_adc_ack || cfg_ack_pulse_adc_eth)) begin
|
|
||||||
eth_state <= ST_IDLE;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
if (axis_hs && !s_axis_tlast) begin
|
|
||||||
eth_state <= ST_DISCARD;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
ST_DISCARD: begin
|
|
||||||
if (axis_hs && s_axis_tlast) begin
|
|
||||||
eth_state <= ST_IDLE;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
default: begin
|
|
||||||
eth_state <= ST_IDLE;
|
|
||||||
end
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// ETH -> DAC: start/reset event sync
|
|
||||||
(* ASYNC_REG = "TRUE" *) logic start_meta_dac, start_sync_dac;
|
|
||||||
logic start_sync_dac_d;
|
|
||||||
(* ASYNC_REG = "TRUE" *) logic rst_meta_dac, rst_sync_dac;
|
|
||||||
logic rst_sync_dac_d;
|
|
||||||
|
|
||||||
wire dac_start_pulse = start_sync_dac ^ start_sync_dac_d;
|
|
||||||
wire dac_rst_pulse = rst_sync_dac ^ rst_sync_dac_d;
|
|
||||||
|
|
||||||
always_ff @(posedge dac_clk_in or posedge dac_rst_int) begin
|
|
||||||
if (dac_rst_int) begin
|
|
||||||
start_meta_dac <= 1'b0;
|
|
||||||
start_sync_dac <= 1'b0;
|
|
||||||
start_sync_dac_d <= 1'b0;
|
|
||||||
|
|
||||||
rst_meta_dac <= 1'b0;
|
|
||||||
rst_sync_dac <= 1'b0;
|
|
||||||
rst_sync_dac_d <= 1'b0;
|
|
||||||
|
|
||||||
dac_start <= 1'b0;
|
|
||||||
dac_rst <= 1'b0;
|
|
||||||
end else begin
|
|
||||||
start_meta_dac <= start_toggle_eth;
|
|
||||||
start_sync_dac <= start_meta_dac;
|
|
||||||
start_sync_dac_d <= start_sync_dac;
|
|
||||||
|
|
||||||
rst_meta_dac <= rst_toggle_eth;
|
|
||||||
rst_sync_dac <= rst_meta_dac;
|
|
||||||
rst_sync_dac_d <= rst_sync_dac;
|
|
||||||
|
|
||||||
dac_start <= dac_start_pulse;
|
|
||||||
dac_rst <= dac_rst_pulse;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// ETH -> ADC: start/reset event sync
|
|
||||||
(* ASYNC_REG = "TRUE" *) logic start_meta_adc, start_sync_adc;
|
|
||||||
logic start_sync_adc_d;
|
|
||||||
(* ASYNC_REG = "TRUE" *) logic rst_meta_adc, rst_sync_adc;
|
|
||||||
logic rst_sync_adc_d;
|
|
||||||
|
|
||||||
wire adc_start_pulse = start_sync_adc ^ start_sync_adc_d;
|
|
||||||
wire adc_rst_pulse = rst_sync_adc ^ rst_sync_adc_d;
|
|
||||||
|
|
||||||
always_ff @(posedge adc_clk_in or posedge adc_rst_int) begin
|
|
||||||
if (adc_rst_int) begin
|
|
||||||
start_meta_adc <= 1'b0;
|
|
||||||
start_sync_adc <= 1'b0;
|
|
||||||
start_sync_adc_d <= 1'b0;
|
|
||||||
|
|
||||||
rst_meta_adc <= 1'b0;
|
|
||||||
rst_sync_adc <= 1'b0;
|
|
||||||
rst_sync_adc_d <= 1'b0;
|
|
||||||
|
|
||||||
adc_start <= 1'b0;
|
|
||||||
adc_rst <= 1'b0;
|
|
||||||
end else begin
|
|
||||||
start_meta_adc <= start_toggle_eth;
|
|
||||||
start_sync_adc <= start_meta_adc;
|
|
||||||
start_sync_adc_d <= start_sync_adc;
|
|
||||||
|
|
||||||
rst_meta_adc <= rst_toggle_eth;
|
|
||||||
rst_sync_adc <= rst_meta_adc;
|
|
||||||
rst_sync_adc_d <= rst_sync_adc;
|
|
||||||
|
|
||||||
adc_start <= adc_start_pulse;
|
|
||||||
adc_rst <= adc_rst_pulse;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// ETH -> DAC config CDC
|
|
||||||
// cfg_bus_eth is kept stable in ETH domain until DAC and ADC both ACK.
|
|
||||||
(* ASYNC_REG = "TRUE" *) logic cfg_req_meta_dac, cfg_req_sync_dac;
|
|
||||||
logic cfg_req_sync_dac_d;
|
|
||||||
wire cfg_req_pulse_dac = cfg_req_sync_dac ^ cfg_req_sync_dac_d;
|
|
||||||
|
|
||||||
always_ff @(posedge dac_clk_in or posedge dac_rst_int) begin
|
|
||||||
if (dac_rst_int) begin
|
|
||||||
cfg_req_meta_dac <= 1'b0;
|
|
||||||
cfg_req_sync_dac <= 1'b0;
|
|
||||||
cfg_req_sync_dac_d<= 1'b0;
|
|
||||||
cfg_ack_toggle_dac<= 1'b0;
|
|
||||||
|
|
||||||
dac_pulse_width <= '0;
|
|
||||||
dac_pulse_period <= '0;
|
|
||||||
dac_pulse_num <= '0;
|
|
||||||
dac_pulse_height <= '0;
|
|
||||||
end else begin
|
|
||||||
cfg_req_meta_dac <= cfg_req_toggle_dac_eth;
|
|
||||||
cfg_req_sync_dac <= cfg_req_meta_dac;
|
|
||||||
cfg_req_sync_dac_d <= cfg_req_sync_dac;
|
|
||||||
|
|
||||||
if (cfg_req_pulse_dac) begin
|
|
||||||
dac_pulse_width <= cfg_bus_eth[31:0];
|
|
||||||
dac_pulse_period <= cfg_bus_eth[63:32];
|
|
||||||
dac_pulse_num <= cfg_bus_eth[79:64];
|
|
||||||
dac_pulse_height <= cfg_bus_eth[80 +: DAC_DATA_WIDTH];
|
|
||||||
|
|
||||||
cfg_ack_toggle_dac <= ~cfg_ack_toggle_dac;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// ETH -> ADC config CDC
|
|
||||||
logic cfg_req_meta_adc, cfg_req_sync_adc, cfg_req_sync_adc_d;
|
|
||||||
wire cfg_req_pulse_adc = cfg_req_sync_adc ^ cfg_req_sync_adc_d;
|
|
||||||
|
|
||||||
always_ff @(posedge adc_clk_in or posedge adc_rst_int) begin
|
|
||||||
if (adc_rst_int) begin
|
|
||||||
cfg_req_meta_adc <= 1'b0;
|
|
||||||
cfg_req_sync_adc <= 1'b0;
|
|
||||||
cfg_req_sync_adc_d <= 1'b0;
|
|
||||||
cfg_ack_toggle_adc <= 1'b0;
|
|
||||||
|
|
||||||
adc_pulse_period <= '0;
|
|
||||||
adc_pulse_num <= '0;
|
|
||||||
end else begin
|
|
||||||
cfg_req_meta_adc <= cfg_req_toggle_adc_eth;
|
|
||||||
cfg_req_sync_adc <= cfg_req_meta_adc;
|
|
||||||
cfg_req_sync_adc_d <= cfg_req_sync_adc;
|
|
||||||
|
|
||||||
if (cfg_req_pulse_adc) begin
|
|
||||||
adc_pulse_period <= cfg_bus_eth[63:32];
|
|
||||||
adc_pulse_num <= cfg_bus_eth[79:64];
|
|
||||||
|
|
||||||
cfg_ack_toggle_adc <= ~cfg_ack_toggle_adc;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
@ -1,52 +0,0 @@
|
|||||||
# SPDX-License-Identifier: MIT
|
|
||||||
#
|
|
||||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
|
||||||
#
|
|
||||||
# Authors:
|
|
||||||
# - Alex Forencich
|
|
||||||
#
|
|
||||||
|
|
||||||
# FPGA settings
|
|
||||||
FPGA_PART = xc7a35tfgg484-1
|
|
||||||
FPGA_TOP = control
|
|
||||||
FPGA_ARCH = artix7
|
|
||||||
|
|
||||||
RTL_DIR = ../src
|
|
||||||
|
|
||||||
|
|
||||||
include ../../../scripts/vivado.mk
|
|
||||||
|
|
||||||
SYN_FILES += $(sort $(shell find ../src -type f \( -name '*.v' -o -name '*.sv' \)))
|
|
||||||
|
|
||||||
XCI_FILES = $(sort $(shell find ../src -type f -name '*.xci'))
|
|
||||||
|
|
||||||
XDC_FILES += ../../../constraints/ax7a035b.xdc
|
|
||||||
XDC_FILES += test_timing.xdc
|
|
||||||
|
|
||||||
SYN_FILES += controller_tb.sv
|
|
||||||
SIM_TOP = control_tb
|
|
||||||
|
|
||||||
|
|
||||||
program: $(PROJECT).bit
|
|
||||||
echo "open_hw_manager" > program.tcl
|
|
||||||
echo "connect_hw_server" >> program.tcl
|
|
||||||
echo "open_hw_target" >> program.tcl
|
|
||||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
|
||||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
|
||||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
|
||||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
|
||||||
echo "exit" >> program.tcl
|
|
||||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
|
||||||
|
|
||||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
|
||||||
echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
|
||||||
echo "exit" >> generate_mcs.tcl
|
|
||||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
|
||||||
mkdir -p rev
|
|
||||||
COUNT=100; \
|
|
||||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
|
||||||
do COUNT=$$((COUNT+1)); done; \
|
|
||||||
COUNT=$$((COUNT-1)); \
|
|
||||||
for x in .mcs .prm; \
|
|
||||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
|
||||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
|
||||||
@ -1,377 +0,0 @@
|
|||||||
`timescale 1ns/1ps
|
|
||||||
|
|
||||||
module tb_control;
|
|
||||||
|
|
||||||
localparam int unsigned DAC_DATA_WIDTH = 12;
|
|
||||||
|
|
||||||
|
|
||||||
// Clocks / reset
|
|
||||||
logic eth_clk_in;
|
|
||||||
logic dac_clk_in;
|
|
||||||
logic adc_clk_in;
|
|
||||||
logic rst_n;
|
|
||||||
|
|
||||||
// axi stream (input)
|
|
||||||
logic [7:0] s_axis_tdata;
|
|
||||||
logic s_axis_tvalid;
|
|
||||||
logic s_axis_tready;
|
|
||||||
logic s_axis_tlast;
|
|
||||||
|
|
||||||
// ADC side input
|
|
||||||
logic finish;
|
|
||||||
|
|
||||||
// DUT outputs
|
|
||||||
logic [31:0] dac_pulse_width;
|
|
||||||
logic [31:0] dac_pulse_period;
|
|
||||||
logic [DAC_DATA_WIDTH-1:0] dac_pulse_height;
|
|
||||||
logic [15:0] dac_pulse_num;
|
|
||||||
|
|
||||||
logic [31:0] adc_pulse_period;
|
|
||||||
logic [15:0] adc_pulse_num;
|
|
||||||
|
|
||||||
logic dac_start;
|
|
||||||
logic adc_start;
|
|
||||||
logic dac_rst;
|
|
||||||
logic adc_rst;
|
|
||||||
|
|
||||||
|
|
||||||
// DUT
|
|
||||||
control #(
|
|
||||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
|
|
||||||
) dut (
|
|
||||||
.eth_clk_in (eth_clk_in),
|
|
||||||
.dac_clk_in (dac_clk_in),
|
|
||||||
.adc_clk_in (adc_clk_in),
|
|
||||||
.rst_n (rst_n),
|
|
||||||
|
|
||||||
.s_axis_tdata (s_axis_tdata),
|
|
||||||
.s_axis_tvalid (s_axis_tvalid),
|
|
||||||
.s_axis_tready (s_axis_tready),
|
|
||||||
.s_axis_tlast (s_axis_tlast),
|
|
||||||
|
|
||||||
.finish (finish),
|
|
||||||
|
|
||||||
.dac_pulse_width (dac_pulse_width),
|
|
||||||
.dac_pulse_period (dac_pulse_period),
|
|
||||||
.dac_pulse_height (dac_pulse_height),
|
|
||||||
.dac_pulse_num (dac_pulse_num),
|
|
||||||
|
|
||||||
.adc_pulse_period (adc_pulse_period),
|
|
||||||
.adc_pulse_num (adc_pulse_num),
|
|
||||||
|
|
||||||
.dac_start (dac_start),
|
|
||||||
.adc_start (adc_start),
|
|
||||||
.dac_rst (dac_rst),
|
|
||||||
.adc_rst (adc_rst)
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
// Clock generation
|
|
||||||
initial begin
|
|
||||||
eth_clk_in = 1'b0;
|
|
||||||
forever #(1 * 4.000) eth_clk_in = ~eth_clk_in; // 125 MHz
|
|
||||||
end
|
|
||||||
|
|
||||||
initial begin
|
|
||||||
dac_clk_in = 1'b0;
|
|
||||||
forever #(1 * 3.846153846) dac_clk_in = ~dac_clk_in; // ~130 MHz
|
|
||||||
end
|
|
||||||
|
|
||||||
initial begin
|
|
||||||
adc_clk_in = 1'b0;
|
|
||||||
forever #(1 * 7.692307692) adc_clk_in = ~adc_clk_in; // ~65 MHz
|
|
||||||
end
|
|
||||||
|
|
||||||
|
|
||||||
// pulse counters and monitors for testing
|
|
||||||
int dac_rst_count;
|
|
||||||
int adc_rst_count;
|
|
||||||
int dac_start_count;
|
|
||||||
int adc_start_count;
|
|
||||||
|
|
||||||
always_ff @(posedge dac_clk_in) begin
|
|
||||||
if (!rst_n) begin
|
|
||||||
dac_rst_count <= 0;
|
|
||||||
dac_start_count <= 0;
|
|
||||||
end else begin
|
|
||||||
if (dac_rst) dac_rst_count <= dac_rst_count + 1;
|
|
||||||
if (dac_start) dac_start_count <= dac_start_count + 1;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always_ff @(posedge adc_clk_in) begin
|
|
||||||
if (!rst_n) begin
|
|
||||||
adc_rst_count <= 0;
|
|
||||||
adc_start_count <= 0;
|
|
||||||
end else begin
|
|
||||||
if (adc_rst) adc_rst_count <= adc_rst_count + 1;
|
|
||||||
if (adc_start) adc_start_count <= adc_start_count + 1;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
|
|
||||||
// some helpers for axi
|
|
||||||
task automatic axis_send_byte(input logic [7:0] data, input logic last);
|
|
||||||
begin
|
|
||||||
@(negedge eth_clk_in);
|
|
||||||
s_axis_tdata <= data;
|
|
||||||
s_axis_tvalid <= 1'b1;
|
|
||||||
s_axis_tlast <= last;
|
|
||||||
|
|
||||||
@(posedge eth_clk_in);
|
|
||||||
while (!s_axis_tready) begin
|
|
||||||
@(posedge eth_clk_in);
|
|
||||||
end
|
|
||||||
|
|
||||||
s_axis_tvalid <= 1'b0;
|
|
||||||
s_axis_tlast <= 1'b0;
|
|
||||||
s_axis_tdata <= '0;
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
task automatic send_cmd(input logic [7:0] cmd);
|
|
||||||
begin
|
|
||||||
axis_send_byte(cmd, 1'b1);
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
task automatic send_set_data(
|
|
||||||
input logic [31:0] pulse_width,
|
|
||||||
input logic [31:0] pulse_period,
|
|
||||||
input logic [15:0] pulse_num,
|
|
||||||
input logic [15:0] pulse_height_raw
|
|
||||||
);
|
|
||||||
logic [95:0] payload;
|
|
||||||
int i;
|
|
||||||
begin
|
|
||||||
// little-endian payload layout:
|
|
||||||
// [31:0] pulse_width
|
|
||||||
// [63:32] pulse_period
|
|
||||||
// [79:64] pulse_num
|
|
||||||
// [95:80] pulse_height_raw
|
|
||||||
payload = {pulse_height_raw, pulse_num, pulse_period, pulse_width};
|
|
||||||
|
|
||||||
axis_send_byte(8'h88, 1'b0); // CMD_SET_DATA
|
|
||||||
|
|
||||||
for (i = 0; i < 12; i++) begin
|
|
||||||
axis_send_byte(payload[i*8 +: 8], (i == 11));
|
|
||||||
end
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
task automatic pulse_finish;
|
|
||||||
begin
|
|
||||||
@(posedge adc_clk_in);
|
|
||||||
finish <= 1'b1;
|
|
||||||
@(posedge adc_clk_in);
|
|
||||||
finish <= 1'b0;
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
|
|
||||||
// waiters
|
|
||||||
task automatic wait_dac_rst_count(input int expected, input int max_cycles = 100);
|
|
||||||
int i;
|
|
||||||
begin
|
|
||||||
for (i = 0; i < max_cycles; i++) begin
|
|
||||||
@(posedge dac_clk_in);
|
|
||||||
if (dac_rst_count >= expected) return;
|
|
||||||
end
|
|
||||||
$fatal(1, "Timeout waiting for dac_rst_count >= %0d, current=%0d", expected, dac_rst_count);
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
task automatic wait_adc_rst_count(input int expected, input int max_cycles = 100);
|
|
||||||
int i;
|
|
||||||
begin
|
|
||||||
for (i = 0; i < max_cycles; i++) begin
|
|
||||||
@(posedge adc_clk_in);
|
|
||||||
if (adc_rst_count >= expected) return;
|
|
||||||
end
|
|
||||||
$fatal(1, "Timeout waiting for adc_rst_count >= %0d, current=%0d", expected, adc_rst_count);
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
task automatic wait_dac_start_count(input int expected, input int max_cycles = 100);
|
|
||||||
int i;
|
|
||||||
begin
|
|
||||||
for (i = 0; i < max_cycles; i++) begin
|
|
||||||
@(posedge dac_clk_in);
|
|
||||||
if (dac_start_count >= expected) return;
|
|
||||||
end
|
|
||||||
$fatal(1, "Timeout waiting for dac_start_count >= %0d, current=%0d", expected, dac_start_count);
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
task automatic wait_adc_start_count(input int expected, input int max_cycles = 100);
|
|
||||||
int i;
|
|
||||||
begin
|
|
||||||
for (i = 0; i < max_cycles; i++) begin
|
|
||||||
@(posedge adc_clk_in);
|
|
||||||
if (adc_start_count >= expected) return;
|
|
||||||
end
|
|
||||||
$fatal(1, "Timeout waiting for adc_start_count >= %0d, current=%0d", expected, adc_start_count);
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
task automatic wait_cfg_applied(
|
|
||||||
input logic [31:0] exp_pulse_width,
|
|
||||||
input logic [31:0] exp_pulse_period,
|
|
||||||
input logic [15:0] exp_pulse_num,
|
|
||||||
input logic [15:0] exp_pulse_height_raw,
|
|
||||||
input int max_cycles = 200
|
|
||||||
);
|
|
||||||
logic [DAC_DATA_WIDTH-1:0] exp_dac_height;
|
|
||||||
int i;
|
|
||||||
begin
|
|
||||||
exp_dac_height = exp_pulse_height_raw[DAC_DATA_WIDTH-1:0];
|
|
||||||
|
|
||||||
for (i = 0; i < max_cycles; i++) begin
|
|
||||||
@(posedge eth_clk_in);
|
|
||||||
if ((dac_pulse_width === exp_pulse_width ) &&
|
|
||||||
(dac_pulse_period === exp_pulse_period) &&
|
|
||||||
(dac_pulse_num === exp_pulse_num ) &&
|
|
||||||
(dac_pulse_height === exp_dac_height ) &&
|
|
||||||
(adc_pulse_period === exp_pulse_period) &&
|
|
||||||
(adc_pulse_num === exp_pulse_num )) begin
|
|
||||||
return;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
$fatal(1,
|
|
||||||
"Timeout waiting config outputs. Got: dac_width=%h dac_period=%h dac_num=%h dac_height=%h adc_period=%h adc_num=%h",
|
|
||||||
dac_pulse_width, dac_pulse_period, dac_pulse_num, dac_pulse_height,
|
|
||||||
adc_pulse_period, adc_pulse_num
|
|
||||||
);
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
|
|
||||||
// Test sequence
|
|
||||||
logic [31:0] test_pulse_width;
|
|
||||||
logic [31:0] test_pulse_period;
|
|
||||||
logic [15:0] test_pulse_num;
|
|
||||||
logic [15:0] test_pulse_height_raw;
|
|
||||||
|
|
||||||
initial begin
|
|
||||||
// defaults
|
|
||||||
rst_n = 1'b0;
|
|
||||||
s_axis_tdata = '0;
|
|
||||||
s_axis_tvalid = 1'b0;
|
|
||||||
s_axis_tlast = 1'b0;
|
|
||||||
finish = 1'b0;
|
|
||||||
|
|
||||||
test_pulse_width = 32'h11223344;
|
|
||||||
test_pulse_period = 32'h55667788;
|
|
||||||
test_pulse_num = 16'hA1B2;
|
|
||||||
test_pulse_height_raw = 16'h0CDE; // for DAC_DATA_WIDTH=12 => 12'hCDE
|
|
||||||
|
|
||||||
repeat (10) @(posedge eth_clk_in);
|
|
||||||
rst_n = 1'b1;
|
|
||||||
|
|
||||||
repeat (10) @(posedge eth_clk_in);
|
|
||||||
|
|
||||||
$display("[%0t] TEST 1: soft_reset", $time);
|
|
||||||
send_cmd(8'h0F);
|
|
||||||
|
|
||||||
wait_dac_rst_count(1);
|
|
||||||
wait_adc_rst_count(1);
|
|
||||||
|
|
||||||
if (dac_rst_count != 1) begin
|
|
||||||
$fatal(1, "Expected exactly one dac_rst pulse after first soft_reset, got %0d", dac_rst_count);
|
|
||||||
end
|
|
||||||
if (adc_rst_count != 1) begin
|
|
||||||
$fatal(1, "Expected exactly one adc_rst pulse after first soft_reset, got %0d", adc_rst_count);
|
|
||||||
end
|
|
||||||
|
|
||||||
$display("[%0t] TEST 1 passed", $time);
|
|
||||||
|
|
||||||
$display("[%0t] TEST 2: set_data", $time);
|
|
||||||
send_set_data(
|
|
||||||
test_pulse_width,
|
|
||||||
test_pulse_period,
|
|
||||||
test_pulse_num,
|
|
||||||
test_pulse_height_raw
|
|
||||||
);
|
|
||||||
|
|
||||||
wait_cfg_applied(
|
|
||||||
test_pulse_width,
|
|
||||||
test_pulse_period,
|
|
||||||
test_pulse_num,
|
|
||||||
test_pulse_height_raw
|
|
||||||
);
|
|
||||||
|
|
||||||
if (dac_pulse_width !== 32'h11223344) begin
|
|
||||||
$fatal(1, "dac_pulse_width mismatch: got %h expected %h", dac_pulse_width, 32'h11223344);
|
|
||||||
end
|
|
||||||
if (dac_pulse_period !== 32'h55667788) begin
|
|
||||||
$fatal(1, "dac_pulse_period mismatch: got %h expected %h", dac_pulse_period, 32'h55667788);
|
|
||||||
end
|
|
||||||
if (dac_pulse_num !== 16'hA1B2) begin
|
|
||||||
$fatal(1, "dac_pulse_num mismatch: got %h expected %h", dac_pulse_num, 16'hA1B2);
|
|
||||||
end
|
|
||||||
if (dac_pulse_height !== 12'hCDE) begin
|
|
||||||
$fatal(1, "dac_pulse_height mismatch: got %h expected %h", dac_pulse_height, 12'hCDE);
|
|
||||||
end
|
|
||||||
if (adc_pulse_period !== 32'h55667788) begin
|
|
||||||
$fatal(1, "adc_pulse_period mismatch: got %h expected %h", adc_pulse_period, 32'h55667788);
|
|
||||||
end
|
|
||||||
if (adc_pulse_num !== 16'hA1B2) begin
|
|
||||||
$fatal(1, "adc_pulse_num mismatch: got %h expected %h", adc_pulse_num, 16'hA1B2);
|
|
||||||
end
|
|
||||||
|
|
||||||
$display("[%0t] TEST 2 passed", $time);
|
|
||||||
|
|
||||||
repeat (20) @(posedge eth_clk_in);
|
|
||||||
|
|
||||||
$display("[%0t] TEST 3: start", $time);
|
|
||||||
send_cmd(8'hF0);
|
|
||||||
|
|
||||||
wait_dac_start_count(1);
|
|
||||||
wait_adc_start_count(1);
|
|
||||||
|
|
||||||
if (dac_start_count != 1) begin
|
|
||||||
$fatal(1, "Expected exactly one dac_start pulse after first start, got %0d", dac_start_count);
|
|
||||||
end
|
|
||||||
if (adc_start_count != 1) begin
|
|
||||||
$fatal(1, "Expected exactly one adc_start pulse after first start, got %0d", adc_start_count);
|
|
||||||
end
|
|
||||||
|
|
||||||
$display("[%0t] TEST 3 start pulses passed", $time);
|
|
||||||
|
|
||||||
// release busy by finish pulse from ADC domain
|
|
||||||
$display("[%0t] Sending finish pulse", $time);
|
|
||||||
pulse_finish();
|
|
||||||
|
|
||||||
// a bit of wait for finish CDC back to ETH
|
|
||||||
repeat (20) @(posedge eth_clk_in);
|
|
||||||
|
|
||||||
// sanity check that commands are accepted again after finish
|
|
||||||
$display("[%0t] TEST 4: soft_reset after finish", $time);
|
|
||||||
send_cmd(8'h0F);
|
|
||||||
|
|
||||||
wait_dac_rst_count(2);
|
|
||||||
wait_adc_rst_count(2);
|
|
||||||
|
|
||||||
if (dac_rst_count != 2) begin
|
|
||||||
$fatal(1, "Expected exactly two dac_rst pulses total, got %0d", dac_rst_count);
|
|
||||||
end
|
|
||||||
if (adc_rst_count != 2) begin
|
|
||||||
$fatal(1, "Expected exactly two adc_rst pulses total, got %0d", adc_rst_count);
|
|
||||||
end
|
|
||||||
|
|
||||||
$display("[%0t] TEST 4 passed", $time);
|
|
||||||
|
|
||||||
$display("==============================================");
|
|
||||||
$display("ALL BASIC TESTS PASSED");
|
|
||||||
$display("dac_rst_count = %0d", dac_rst_count);
|
|
||||||
$display("adc_rst_count = %0d", adc_rst_count);
|
|
||||||
$display("dac_start_count = %0d", dac_start_count);
|
|
||||||
$display("adc_start_count = %0d", adc_start_count);
|
|
||||||
$display("==============================================");
|
|
||||||
|
|
||||||
#100;
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
@ -1,13 +0,0 @@
|
|||||||
# Primary clocks
|
|
||||||
create_clock -name eth_clk -period 8.000 [get_ports eth_clk_in]
|
|
||||||
create_clock -name dac_clk -period 7.692 [get_ports dac_clk_in]
|
|
||||||
create_clock -name adc_clk -period 15.385 [get_ports adc_clk_in]
|
|
||||||
|
|
||||||
|
|
||||||
# Asynchronous clock groups
|
|
||||||
# eth, dac, adc are independent domains
|
|
||||||
|
|
||||||
set_clock_groups -name ASYNC_ETH_DAC_ADC -asynchronous \
|
|
||||||
-group [get_clocks eth_clk] \
|
|
||||||
-group [get_clocks dac_clk] \
|
|
||||||
-group [get_clocks adc_clk]
|
|
||||||
@ -0,0 +1,99 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
|
||||||
|
module generator
|
||||||
|
#(
|
||||||
|
parameter DATA_WIDTH = 14
|
||||||
|
)
|
||||||
|
(
|
||||||
|
input clk_in,
|
||||||
|
input rst,
|
||||||
|
input start,
|
||||||
|
input [31:0] pulse_width,
|
||||||
|
input [31:0] pulse_period,
|
||||||
|
input [DATA_WIDTH-1:0] pulse_height,
|
||||||
|
input [15:0] pulse_num,
|
||||||
|
|
||||||
|
output pulse,
|
||||||
|
output[DATA_WIDTH-1:0] pulse_height_out
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
logic [DATA_WIDTH-1:0] pulse_height_reg, pulse_height_out_reg;
|
||||||
|
logic pulse_reg;
|
||||||
|
|
||||||
|
logic [31:0] pulse_width_reg, pulse_period_reg;
|
||||||
|
logic [15:0] pulse_num_reg;
|
||||||
|
|
||||||
|
logic enable;
|
||||||
|
logic [15:0] cnt_pulse_num;
|
||||||
|
logic [31:0] cnt_period;
|
||||||
|
|
||||||
|
logic start_d;
|
||||||
|
|
||||||
|
always @(posedge clk_in) begin
|
||||||
|
start_d <= start;
|
||||||
|
end
|
||||||
|
|
||||||
|
wire start_pulse = start & ~start_d;
|
||||||
|
|
||||||
|
|
||||||
|
always @(posedge clk_in) begin
|
||||||
|
if (rst) begin
|
||||||
|
pulse_reg <= '0;
|
||||||
|
pulse_height_reg <= 0;
|
||||||
|
pulse_height_out_reg <= '0;
|
||||||
|
|
||||||
|
pulse_width_reg <= '0;
|
||||||
|
pulse_period_reg <= '0;
|
||||||
|
pulse_num_reg <= '0;
|
||||||
|
enable <= 0;
|
||||||
|
cnt_pulse_num <= '0;
|
||||||
|
cnt_period <= '0;
|
||||||
|
end else begin
|
||||||
|
if (start) begin
|
||||||
|
enable <= 1'b1;
|
||||||
|
// pulse_width_reg <= pulse_width;
|
||||||
|
// pulse_period_reg <= pulse_period;
|
||||||
|
// pulse_num_reg <= pulse_num;
|
||||||
|
// pulse_height_reg <= pulse_height;
|
||||||
|
|
||||||
|
cnt_pulse_num <= '0;
|
||||||
|
cnt_period <= '0;
|
||||||
|
end
|
||||||
|
if (enable) begin
|
||||||
|
pulse_reg <= 1;
|
||||||
|
|
||||||
|
pulse_width_reg <= pulse_width;
|
||||||
|
pulse_period_reg <= pulse_period;
|
||||||
|
pulse_num_reg <= pulse_num;
|
||||||
|
pulse_height_reg <= pulse_height;
|
||||||
|
|
||||||
|
if (pulse_reg) begin
|
||||||
|
|
||||||
|
if (cnt_period < pulse_width_reg) begin
|
||||||
|
pulse_height_out_reg <= pulse_height_reg;
|
||||||
|
end else begin
|
||||||
|
pulse_height_out_reg <= '0;
|
||||||
|
end
|
||||||
|
if (cnt_period == pulse_period_reg - 1) begin
|
||||||
|
cnt_period <= 0;
|
||||||
|
if (cnt_pulse_num == pulse_num_reg - 1) begin
|
||||||
|
enable <= 0;
|
||||||
|
pulse_reg <= 0;
|
||||||
|
end else begin
|
||||||
|
cnt_pulse_num <= cnt_pulse_num + 1;
|
||||||
|
end
|
||||||
|
end else begin
|
||||||
|
cnt_period <= cnt_period + 1;
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
assign pulse_height_out = pulse_height_out_reg;
|
||||||
|
assign pulse = pulse_reg;
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|||||||
105
rtl/generator/tests/generator_tb.sv
Normal file
105
rtl/generator/tests/generator_tb.sv
Normal file
@ -0,0 +1,105 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
module generator_tb;
|
||||||
|
|
||||||
|
parameter DATA_WIDTH = 14;
|
||||||
|
parameter CLK_PERIOD = 16;
|
||||||
|
|
||||||
|
logic clk;
|
||||||
|
logic rst;
|
||||||
|
logic start;
|
||||||
|
|
||||||
|
logic [31:0] pulse_width;
|
||||||
|
logic [31:0] pulse_period;
|
||||||
|
logic [DATA_WIDTH-1:0] pulse_height;
|
||||||
|
logic [15:0] pulse_num;
|
||||||
|
|
||||||
|
logic pulse;
|
||||||
|
logic [DATA_WIDTH-1:0] pulse_height_out;
|
||||||
|
|
||||||
|
// DUT
|
||||||
|
generator #(
|
||||||
|
.DATA_WIDTH(DATA_WIDTH)
|
||||||
|
) dut (
|
||||||
|
.clk_in(clk),
|
||||||
|
.rst(rst),
|
||||||
|
.start(start),
|
||||||
|
.pulse_width(pulse_width),
|
||||||
|
.pulse_period(pulse_period),
|
||||||
|
.pulse_height(pulse_height),
|
||||||
|
.pulse_num(pulse_num),
|
||||||
|
.pulse(pulse),
|
||||||
|
.pulse_height_out(pulse_height_out)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Clock
|
||||||
|
initial begin
|
||||||
|
clk = 0;
|
||||||
|
forever #(CLK_PERIOD/2) clk = ~clk;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
$display("\n=== GENERATOR TEST ===\n");
|
||||||
|
|
||||||
|
rst = 1;
|
||||||
|
start = 0;
|
||||||
|
|
||||||
|
pulse_width = 0;
|
||||||
|
pulse_period = 0;
|
||||||
|
pulse_height = 0;
|
||||||
|
pulse_num = 0;
|
||||||
|
|
||||||
|
repeat(5) @(posedge clk);
|
||||||
|
rst = 0;
|
||||||
|
|
||||||
|
// --- Test 1 ---
|
||||||
|
// 3 clk 1, 5 clk 0, 4 pulses
|
||||||
|
repeat(2) @(posedge clk);
|
||||||
|
pulse_width = 3;
|
||||||
|
pulse_period = 8;
|
||||||
|
pulse_num = 4;
|
||||||
|
pulse_height = 14'h3FF;
|
||||||
|
start = 1;
|
||||||
|
|
||||||
|
repeat(1) @(posedge clk);
|
||||||
|
start = 0;
|
||||||
|
|
||||||
|
repeat(50) @(posedge clk);
|
||||||
|
|
||||||
|
// --- Test 2 ---
|
||||||
|
$display("\n--- SECOND RUN ---\n");
|
||||||
|
|
||||||
|
@(posedge clk);
|
||||||
|
pulse_width = 2;
|
||||||
|
pulse_period = 5;
|
||||||
|
pulse_num = 3;
|
||||||
|
pulse_height = 14'h155;
|
||||||
|
start = 1;
|
||||||
|
|
||||||
|
@(posedge clk);
|
||||||
|
start = 0;
|
||||||
|
|
||||||
|
repeat(40) @(posedge clk);
|
||||||
|
|
||||||
|
pulse_width = 3;
|
||||||
|
pulse_period = 8;
|
||||||
|
pulse_num = 4;
|
||||||
|
pulse_height = 14'h3FF;
|
||||||
|
start = 1;
|
||||||
|
|
||||||
|
repeat(1) @(posedge clk);
|
||||||
|
start = 0;
|
||||||
|
|
||||||
|
repeat(50) @(posedge clk);
|
||||||
|
|
||||||
|
$display("\n=== TEST FINISHED ===");
|
||||||
|
$finish;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Display
|
||||||
|
always @(posedge clk) begin
|
||||||
|
$display("t=%0t | pulse=%0b | height=%h",
|
||||||
|
$time, pulse, pulse_height_out);
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
@ -0,0 +1,72 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
module sampler
|
||||||
|
#(
|
||||||
|
parameter DATA_WIDTH = 12,
|
||||||
|
parameter PACK_FACTOR = 3,
|
||||||
|
parameter PROCESS_MODE = 1
|
||||||
|
)
|
||||||
|
(
|
||||||
|
input clk_in,
|
||||||
|
input rst,
|
||||||
|
input [DATA_WIDTH-1:0] data_in,
|
||||||
|
input out_of_range,
|
||||||
|
|
||||||
|
output logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
|
||||||
|
output logic m_axis_tvalid
|
||||||
|
);
|
||||||
|
logic [DATA_WIDTH-1:0] data_converted;
|
||||||
|
logic out_of_range_reg;
|
||||||
|
|
||||||
|
always @( posedge clk_in) begin
|
||||||
|
if (rst) begin
|
||||||
|
data_converted <= '0;
|
||||||
|
end else begin
|
||||||
|
out_of_range_reg <= out_of_range;
|
||||||
|
if (PROCESS_MODE) begin
|
||||||
|
if (data_in == 12'b100000000000) begin
|
||||||
|
data_converted <= data_in;
|
||||||
|
end else begin
|
||||||
|
data_converted <= data_in[DATA_WIDTH-1] ? {1'b1, (~data_in[DATA_WIDTH-2:0] + 1'b1)} : data_in;
|
||||||
|
|
||||||
|
end
|
||||||
|
end else begin
|
||||||
|
data_converted <= data_in;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
|
||||||
|
logic buffer_ready;
|
||||||
|
|
||||||
|
logic [$clog2(PACK_FACTOR):0] cnt;
|
||||||
|
|
||||||
|
always @(posedge clk_in) begin
|
||||||
|
if (rst) begin
|
||||||
|
buffer <= '0;
|
||||||
|
cnt <= -1; //
|
||||||
|
buffer_ready <= 0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
buffer_ready <= 0;
|
||||||
|
if (!out_of_range_reg) begin
|
||||||
|
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
|
||||||
|
if (cnt == PACK_FACTOR-1) begin
|
||||||
|
cnt <= 0;
|
||||||
|
buffer_ready <= 1;
|
||||||
|
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cnt <= cnt + 1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
assign m_axis_tdata = buffer;
|
||||||
|
assign m_axis_tvalid = buffer_ready;
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|||||||
120
rtl/sampler/tests/sampler_tb_advanced.sv
Normal file
120
rtl/sampler/tests/sampler_tb_advanced.sv
Normal file
@ -0,0 +1,120 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
module sampler_tb;
|
||||||
|
|
||||||
|
parameter DATA_WIDTH = 12;
|
||||||
|
parameter PACK_FACTOR = 3;
|
||||||
|
parameter PROCESS_MODE = 1;
|
||||||
|
parameter CLK_PERIOD = 15.3846; // 65 MHz
|
||||||
|
|
||||||
|
logic clk;
|
||||||
|
logic rst;
|
||||||
|
logic [DATA_WIDTH-1:0] data_in;
|
||||||
|
logic out_of_range;
|
||||||
|
logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
|
||||||
|
logic m_axis_tvalid;
|
||||||
|
|
||||||
|
sampler #(
|
||||||
|
.DATA_WIDTH(DATA_WIDTH),
|
||||||
|
.PACK_FACTOR(PACK_FACTOR),
|
||||||
|
.PROCESS_MODE(PROCESS_MODE)
|
||||||
|
) dut (
|
||||||
|
.clk_in(clk),
|
||||||
|
.rst(rst),
|
||||||
|
.data_in(data_in),
|
||||||
|
.out_of_range(out_of_range),
|
||||||
|
.m_axis_tdata(m_axis_tdata),
|
||||||
|
.m_axis_tvalid(m_axis_tvalid)
|
||||||
|
);
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
clk = 0;
|
||||||
|
forever #(CLK_PERIOD/2) clk = ~clk;
|
||||||
|
end
|
||||||
|
|
||||||
|
task send(input [DATA_WIDTH-1:0] word, input bit oor);
|
||||||
|
@(posedge clk);
|
||||||
|
data_in <= word;
|
||||||
|
out_of_range <= oor;
|
||||||
|
$display("Send: %h (%0d) OOR=%b", word, word, oor);
|
||||||
|
endtask
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
$display("\n=== SAMPLER TEST (MODE=%0d) ===\n", PROCESS_MODE);
|
||||||
|
|
||||||
|
// Reset
|
||||||
|
rst = 1;
|
||||||
|
out_of_range = 0;
|
||||||
|
data_in = 0;
|
||||||
|
// send(12'h001, 0);
|
||||||
|
repeat(5) @(posedge clk);
|
||||||
|
rst = 0;
|
||||||
|
send(12'h001, 0);
|
||||||
|
repeat(1) @(posedge clk);
|
||||||
|
|
||||||
|
// 1. Positive
|
||||||
|
$display("\n--- Positive numbers ---");
|
||||||
|
// send(12'h001, 0);
|
||||||
|
send(12'h002, 0);
|
||||||
|
send(12'h003, 0);
|
||||||
|
|
||||||
|
send(12'h004, 0);
|
||||||
|
send(12'h005, 0);
|
||||||
|
send(12'h806, 0);
|
||||||
|
|
||||||
|
// 2. Negative
|
||||||
|
$display("\n--- Negative numbers ---");
|
||||||
|
send(12'hFFF, 0); // -1
|
||||||
|
send(12'hFFE, 0); // -2
|
||||||
|
send(12'hFFD, 0); // -3
|
||||||
|
|
||||||
|
send(12'h800, 0); // -2048
|
||||||
|
send(12'h801, 0); // -2047
|
||||||
|
send(12'h802, 0); // -2046
|
||||||
|
|
||||||
|
// 3. Boundary
|
||||||
|
$display("\n--- Boundary values ---");
|
||||||
|
send(12'h000, 0); // 0
|
||||||
|
send(12'h001, 0); // 1
|
||||||
|
send(12'h7FF, 0); // 2047 (max positive)
|
||||||
|
|
||||||
|
send(12'h7FE, 0); // 2046
|
||||||
|
send(12'h800, 0); // -2048 (min negative)
|
||||||
|
send(12'hFFF, 0); // -1
|
||||||
|
|
||||||
|
// 4. Out of range tests
|
||||||
|
$display("\n--- Out of range tests ---");
|
||||||
|
|
||||||
|
|
||||||
|
send(12'h00A, 0);
|
||||||
|
send(12'h00B, 1); //
|
||||||
|
send(12'h00C, 0);
|
||||||
|
send(12'h00D, 0);
|
||||||
|
send(12'h00E, 0);
|
||||||
|
send(12'h00F, 0);
|
||||||
|
|
||||||
|
send(12'h010, 0);
|
||||||
|
send(12'h011, 0);
|
||||||
|
send(12'h012, 1); //
|
||||||
|
|
||||||
|
send(12'h013, 0);
|
||||||
|
send(12'h014, 0);
|
||||||
|
send(12'h015, 0);
|
||||||
|
|
||||||
|
repeat(10) @(posedge clk);
|
||||||
|
$display("\n=== TEST FINISHED ===");
|
||||||
|
$finish;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Results
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (m_axis_tvalid) begin
|
||||||
|
$display("\n>>> PACKET RECEIVED at %0t ns:", $time);
|
||||||
|
$display(" Full: %h", m_axis_tdata);
|
||||||
|
$display(" Word0: %h", m_axis_tdata[11:0]);
|
||||||
|
$display(" Word1: %h", m_axis_tdata[23:12]);
|
||||||
|
$display(" Word2: %h\n", m_axis_tdata[35:24]);
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
67
rtl/sampler/tests/sampler_tb_basic.sv
Normal file
67
rtl/sampler/tests/sampler_tb_basic.sv
Normal file
@ -0,0 +1,67 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
module sampler_tb;
|
||||||
|
|
||||||
|
parameter DATA_WIDTH = 12;
|
||||||
|
parameter PACK_FACTOR = 3;
|
||||||
|
parameter PROCESS_MODE = 0;
|
||||||
|
|
||||||
|
parameter CLK_PERIOD = 15.3846;
|
||||||
|
|
||||||
|
logic clk;
|
||||||
|
logic rst;
|
||||||
|
logic [DATA_WIDTH-1:0] data_in;
|
||||||
|
logic out_of_range;
|
||||||
|
|
||||||
|
logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
|
||||||
|
logic m_axis_tvalid;
|
||||||
|
|
||||||
|
// DUT
|
||||||
|
sampler #(
|
||||||
|
.DATA_WIDTH(DATA_WIDTH),
|
||||||
|
.PACK_FACTOR(PACK_FACTOR),
|
||||||
|
.PROCESS_MODE(PROCESS_MODE)
|
||||||
|
) dut (
|
||||||
|
.clk_in(clk),
|
||||||
|
.rst(rst),
|
||||||
|
.data_in(data_in),
|
||||||
|
.out_of_range(out_of_range),
|
||||||
|
.m_axis_tdata(m_axis_tdata),
|
||||||
|
.m_axis_tvalid(m_axis_tvalid)
|
||||||
|
);
|
||||||
|
|
||||||
|
// clock
|
||||||
|
initial begin
|
||||||
|
clk = 0;
|
||||||
|
forever #(CLK_PERIOD/2) clk = ~clk;
|
||||||
|
end
|
||||||
|
|
||||||
|
integer i;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
clk = 0;
|
||||||
|
rst = 1;
|
||||||
|
data_in = 0;
|
||||||
|
out_of_range = 0;
|
||||||
|
|
||||||
|
#20;
|
||||||
|
rst = 0;
|
||||||
|
repeat(5) @(posedge clk);
|
||||||
|
|
||||||
|
for (i = 1; i < 20; i++) begin
|
||||||
|
@(posedge clk);
|
||||||
|
|
||||||
|
data_in <= i;
|
||||||
|
end
|
||||||
|
|
||||||
|
#50;
|
||||||
|
$finish;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (m_axis_tvalid) begin
|
||||||
|
$display("TIME=%0t PACKED DATA = %h", $time, m_axis_tdata);
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
@ -110,13 +110,6 @@ create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
|
|||||||
for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
|
for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
|
||||||
for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
|
for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
|
||||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||||
if [ -n "$(TB_FILES)" ]; then \
|
|
||||||
echo "add_files -fileset sim_1 defines.v $(TB_FILES)" >> $@; \
|
|
||||||
echo "set_property top $(SIM_TOP) [get_filesets sim_1]" >> $@; \
|
|
||||||
echo "set_property top_lib xil_defaultlib [get_filesets sim_1]" >> $@; \
|
|
||||||
fi
|
|
||||||
echo "update_compile_order -fileset sources_1" >> $@
|
|
||||||
echo "update_compile_order -fileset sim_1" >> $@
|
|
||||||
|
|
||||||
# source config TCL scripts if any source file has changed
|
# source config TCL scripts if any source file has changed
|
||||||
update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
|
update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
|
||||||
@ -177,9 +170,12 @@ gen_ip:
|
|||||||
|
|
||||||
sim: $(PROJECT).xpr gen_ip
|
sim: $(PROJECT).xpr gen_ip
|
||||||
echo "open_project $(PROJECT).xpr" > run_sim.tcl
|
echo "open_project $(PROJECT).xpr" > run_sim.tcl
|
||||||
|
echo "add_files -fileset sim_1 $(TB_FILES)" >> run_sim.tcl
|
||||||
|
echo "set_property top $(SIM_TOP) [get_filesets sim_1]" >> run_sim.tcl
|
||||||
echo "update_compile_order -fileset sources_1" >> run_sim.tcl
|
echo "update_compile_order -fileset sources_1" >> run_sim.tcl
|
||||||
echo "update_compile_order -fileset sim_1" >> run_sim.tcl
|
echo "update_compile_order -fileset sim_1" >> run_sim.tcl
|
||||||
echo "launch_simulation" >> run_sim.tcl
|
echo "launch_simulation" >> run_sim.tcl
|
||||||
|
echo "run all" >> run_sim.tcl
|
||||||
vivado -mode batch -source run_sim.tcl
|
vivado -mode batch -source run_sim.tcl
|
||||||
|
|
||||||
simclean:
|
simclean:
|
||||||
|
|||||||
@ -1,94 +0,0 @@
|
|||||||
import argparse
|
|
||||||
import socket
|
|
||||||
|
|
||||||
|
|
||||||
def run_debug(args, sock):
|
|
||||||
"""Debug run: send fixed values to test eth+ctrl on fpga."""
|
|
||||||
print(f"DEBUG MODE: ip={args.ip} send_port={args.send_port}")
|
|
||||||
|
|
||||||
dest = (args.ip, args.send_port)
|
|
||||||
|
|
||||||
# reset
|
|
||||||
sock.sendto(0x0f00.to_bytes(2), dest)
|
|
||||||
print("Sent soft_reset!")
|
|
||||||
|
|
||||||
# config data
|
|
||||||
sock.sendto(format_ctrl_data(0x12345678, 0x9abcdef0,
|
|
||||||
0x0bea, 0xdead, dac_bits=args.dac_bits), dest)
|
|
||||||
print("Config data sent!")
|
|
||||||
|
|
||||||
sock.sendto(0xf000.to_bytes(2), dest)
|
|
||||||
print("Sent start!")
|
|
||||||
|
|
||||||
|
|
||||||
def format_ctrl_data(pulse_width: int, pulse_period: int,
|
|
||||||
pulse_height: int, pulse_num: int, dac_bits: int = 16) -> bytes:
|
|
||||||
"""Format data packet for set_data command."""
|
|
||||||
output = bytearray()
|
|
||||||
|
|
||||||
output += 0b10001000.to_bytes(1, 'little')
|
|
||||||
|
|
||||||
# no negative please
|
|
||||||
assert pulse_width > 0, "pulse_width should be positive"
|
|
||||||
assert pulse_period > 0, "pulse_period should be positive"
|
|
||||||
assert pulse_num > 0, "pulse_num should be positive"
|
|
||||||
assert pulse_height > 0, "pulse_height should be positive"
|
|
||||||
|
|
||||||
# overflow check
|
|
||||||
assert pulse_width < 2**32-1, "pulse_width too high"
|
|
||||||
assert pulse_period < 2**32-1, "pulse_period too high"
|
|
||||||
assert pulse_num < 2**16-1, "pulse_num too high"
|
|
||||||
assert pulse_height < 2**dac_bits-1, "pulse_height too high"
|
|
||||||
|
|
||||||
output += pulse_width.to_bytes(4, 'little')
|
|
||||||
output += pulse_period.to_bytes(4, 'little')
|
|
||||||
output += pulse_num.to_bytes(2, 'little')
|
|
||||||
output += pulse_height.to_bytes(2, 'little')
|
|
||||||
|
|
||||||
assert len(output) == 13, "Config data should be 96 bits + 8 bit header"
|
|
||||||
return output
|
|
||||||
|
|
||||||
|
|
||||||
def run(args, sock):
|
|
||||||
pass
|
|
||||||
|
|
||||||
|
|
||||||
def main():
|
|
||||||
parser = argparse.ArgumentParser(
|
|
||||||
description="Консоль для рефлектометра"
|
|
||||||
)
|
|
||||||
|
|
||||||
parser.add_argument("--debug", action='store_true',
|
|
||||||
help="отладочная отправка пакета soft_reset, пакета с данными и пакета start")
|
|
||||||
|
|
||||||
parser.add_argument("--ip", type=str, default="192.168.0.2",
|
|
||||||
help="IP рефлектометра, по умолчанию 192.168.0.2")
|
|
||||||
|
|
||||||
parser.add_argument("--send-port", type=int, default=8080,
|
|
||||||
help="Порт для отправки команд")
|
|
||||||
|
|
||||||
parser.add_argument("--recv-port", type=int,
|
|
||||||
default=8080, help="Порт для приема данных")
|
|
||||||
|
|
||||||
parser.add_argument("--dac-bits", type=int, default=12,
|
|
||||||
help="Битность ЦАП (влияет на максимальный pulse_height)")
|
|
||||||
|
|
||||||
# передача параметров через аргументы
|
|
||||||
for arg in ("pulse_width", "pulse_period", "pulse_num", "pulse_height"):
|
|
||||||
parser.add_argument(f"--{arg}", type=int,
|
|
||||||
default=0, help=f"Задать {arg}")
|
|
||||||
|
|
||||||
args = parser.parse_args()
|
|
||||||
|
|
||||||
sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
|
|
||||||
|
|
||||||
if args.debug:
|
|
||||||
run_debug(args, sock)
|
|
||||||
else:
|
|
||||||
run(args, sock)
|
|
||||||
|
|
||||||
sock.close()
|
|
||||||
|
|
||||||
|
|
||||||
if __name__ == "__main__":
|
|
||||||
main()
|
|
||||||
Reference in New Issue
Block a user