120 lines
3.0 KiB
Systemverilog
120 lines
3.0 KiB
Systemverilog
`timescale 1ns / 1ps
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module sampler_tb;
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parameter DATA_WIDTH = 12;
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parameter PACK_FACTOR = 3;
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parameter PROCESS_MODE = 1;
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parameter CLK_PERIOD = 15.3846; // 65 MHz
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logic clk;
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logic rst;
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logic [DATA_WIDTH-1:0] data_in;
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logic out_of_range;
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logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
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logic m_axis_tvalid;
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sampler #(
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.DATA_WIDTH(DATA_WIDTH),
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.PACK_FACTOR(PACK_FACTOR),
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.PROCESS_MODE(PROCESS_MODE)
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) dut (
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.clk_in(clk),
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.rst(rst),
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.data_in(data_in),
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.out_of_range(out_of_range),
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.m_axis_tdata(m_axis_tdata),
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.m_axis_tvalid(m_axis_tvalid)
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);
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initial begin
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clk = 0;
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forever #(CLK_PERIOD/2) clk = ~clk;
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end
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task send(input [DATA_WIDTH-1:0] word, input bit oor);
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@(posedge clk);
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data_in <= word;
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out_of_range <= oor;
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$display("Send: %h (%0d) OOR=%b", word, word, oor);
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endtask
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initial begin
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$display("\n=== SAMPLER TEST (MODE=%0d) ===\n", PROCESS_MODE);
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// Reset
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rst = 1;
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out_of_range = 0;
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data_in = 0;
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// send(12'h001, 0);
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repeat(5) @(posedge clk);
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rst = 0;
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send(12'h001, 0);
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repeat(1) @(posedge clk);
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// 1. Positive
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$display("\n--- Positive numbers ---");
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// send(12'h001, 0);
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send(12'h002, 0);
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send(12'h003, 0);
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send(12'h004, 0);
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send(12'h005, 0);
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send(12'h806, 0);
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// 2. Negative
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$display("\n--- Negative numbers ---");
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send(12'hFFF, 0); // -1
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send(12'hFFE, 0); // -2
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send(12'hFFD, 0); // -3
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send(12'h800, 0); // -2048
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send(12'h801, 0); // -2047
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send(12'h802, 0); // -2046
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// 3. Boundary
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$display("\n--- Boundary values ---");
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send(12'h000, 0); // 0
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send(12'h001, 0); // 1
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send(12'h7FF, 0); // 2047 (max positive)
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send(12'h7FE, 0); // 2046
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send(12'h800, 0); // -2048 (min negative)
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send(12'hFFF, 0); // -1
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// 4. Out of range tests
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$display("\n--- Out of range tests ---");
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send(12'h00A, 0);
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send(12'h00B, 1); //
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send(12'h00C, 0);
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send(12'h00D, 0);
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send(12'h00E, 0);
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send(12'h00F, 0);
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send(12'h010, 0);
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send(12'h011, 0);
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send(12'h012, 1); //
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send(12'h013, 0);
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send(12'h014, 0);
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send(12'h015, 0);
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repeat(10) @(posedge clk);
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$display("\n=== TEST FINISHED ===");
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$finish;
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end
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// Results
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always @(posedge clk) begin
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if (m_axis_tvalid) begin
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$display("\n>>> PACKET RECEIVED at %0t ns:", $time);
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$display(" Full: %h", m_axis_tdata);
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$display(" Word0: %h", m_axis_tdata[11:0]);
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$display(" Word1: %h", m_axis_tdata[23:12]);
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$display(" Word2: %h\n", m_axis_tdata[35:24]);
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end
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end
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endmodule |