reflectometer_fpga_project

Author	SHA1	Message	Date
otroubi	c121c2c103	test environment for controller and dma project	2026-07-21 22:36:55 +03:00
otroubi	56c33d2769	makefile for test project	2026-07-21 22:35:32 +03:00
otroubi	fc33aa6862	rtl: little changes	2026-07-21 14:07:44 +03:00
otroubi	490d3dcfd0	creation of project for dma tests	2026-07-20 17:29:15 +03:00
otroubi	1c2eccaf1d	rtl: reconstruction of registers for dma	2026-07-20 17:28:48 +03:00
otroubi	42df57be7d	axis flat to if / if to flat correction	2026-07-14 19:24:25 +03:00
otroubi	606d1d7f1c	little axis desc status correction	2026-07-14 19:07:32 +03:00
otroubi	8aefa4f3f6	axis dma desc and status interface	2026-07-14 18:39:48 +03:00
otroubi	984461afc0	shapper syntaxis corrected	2026-07-14 13:55:58 +03:00
otroubi	6c171c55d7	controller_wrapper_axil syntaxis corrected	2026-07-14 13:55:42 +03:00
otroubi	c1031f6a26	DMA control module	2026-07-14 13:08:10 +03:00
otroubi	d0f48ba513	controller_wrapper_axil with DMA control registers	2026-07-14 13:07:48 +03:00
otroubi	c0a2f0e403	add window_size register	2026-07-10 14:15:17 +03:00
otroubi	7bd1aa68da	add window_sizereg and cfg_bus_valid_reg	2026-07-10 14:03:07 +03:00
otroubi	061f8fe12b	debugged controller	2026-07-10 13:13:18 +03:00
otroubi	99a344d534	debugging controller	2026-07-08 17:53:25 +03:00
otroubi	e7c45101d1	rst added	2026-07-08 12:51:38 +03:00
otroubi	fc3134f2d8	controller's changes	2026-07-08 12:50:28 +03:00
otroubi	a82140feda	add send signal to start a dma transaction	2026-07-08 12:49:51 +03:00
otroubi	bafd084f0d	rtl: dma descriptor and status transmitter logic	2026-07-07 17:33:53 +03:00
otroubi	d71655885c	rtl: axil wrapper logic for controller	2026-07-07 17:33:25 +03:00
otroubi	56e31a6cc6	rtl: add window_size register	2026-07-07 17:32:42 +03:00
otroubi	14a1df8bae	rtl: controller module deconstruction	2026-07-07 17:32:13 +03:00
otroubi	a6ade44b4d	rtl: eth remove	2026-07-03 16:28:08 +03:00
otroubi	14f4a5eb2a	rtl: register map addition for DMA control	2026-06-30 17:13:00 +03:00
otroubi	1eb21b5087	rtl: controller adc_dac management register map	2026-06-30 13:12:51 +03:00
otroubi	9285ce42e1	infra: add submodule	2026-06-26 17:52:26 +03:00
otroubi	10dc60b54f	doc: README decoration	2026-05-15 16:41:18 +03:00
otroubi	966704a4de	chore: 2 starts incident	2026-05-15 14:53:00 +03:00
otroubi	b2c92070a2	chore generator little fix 2	2026-05-15 13:49:00 +03:00
otroubi	51d715a728	chore: generator little fix	2026-05-15 13:47:08 +03:00
otroubi	9efbd6586f	chore: generator evolution	2026-05-15 13:36:10 +03:00
otroubi	3a2d8eda2b	rtl: reorganised top without eth	2026-05-08 19:03:24 +03:00
otroubi	9b72dfb8d9	fix: cnt_smp_num sampler	2026-05-08 14:08:01 +03:00
otroubi	8c4154baf0	rtl: reflectometer add synchronizer logic	2026-05-06 15:38:25 +03:00
otroubi	c279f1158d	chore: clean code sync_top	2026-05-06 15:37:15 +03:00
otroubi	4fc354955c	rtl: debug synchronizer project makefile	2026-05-06 14:41:26 +03:00
otroubi	57570bea00	rtl: debug synchronizer project constraints	2026-05-06 14:41:15 +03:00
otroubi	03d0abbe86	rtl: debug synchronizer project testbench	2026-05-06 14:40:53 +03:00
otroubi	d26bc29507	rtl: debug synchronizer project	2026-05-06 14:40:33 +03:00
otroubi	e9c39ea344	rtl: generator synchronizer update	2026-05-06 14:31:37 +03:00
otroubi	7c3fe36df1	rtl: sampler synchronizer update	2026-05-06 14:30:23 +03:00
otroubi	f719533eb9	chore: generator and sampler brushed	2026-04-30 13:14:26 +03:00
otroubi	138c5d7dce	dev: full project reflectometer	2026-04-28 17:18:41 +03:00
otroubi	bd8dc9d0d3	chore: fix readme	2026-04-28 15:25:51 +03:00
otroubi	2e22eb68df	docs: add sampler_readme	2026-04-28 15:21:58 +03:00
otroubi	5f1f4e5a16	rtl: new tb	2026-04-28 13:57:28 +03:00
otroubi	264c9ecb8e	rtl: update sampler	2026-04-28 13:10:22 +03:00
otroubi	7a1c838de3	rtl: generator added	2026-04-08 15:13:57 +03:00
otroubi	221cb055f1	rtl: sampler ready	2026-04-01 11:46:59 +03:00