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c057890007
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fix: invalid signals
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2026-07-14 20:07:23 +03:00 |
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42df57be7d
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axis flat to if / if to flat correction
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2026-07-14 19:24:25 +03:00 |
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606d1d7f1c
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little axis desc status correction
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2026-07-14 19:07:32 +03:00 |
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8aefa4f3f6
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axis dma desc and status interface
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2026-07-14 18:39:48 +03:00 |
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cec4c84fd9
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fix: controller reg map invalid mapping
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2026-07-14 17:43:47 +03:00 |
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e467700368
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tests: update testbench for controller reg map
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2026-07-14 16:34:35 +03:00 |
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984461afc0
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shapper syntaxis corrected
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2026-07-14 13:55:58 +03:00 |
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6c171c55d7
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controller_wrapper_axil syntaxis corrected
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2026-07-14 13:55:42 +03:00 |
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c1031f6a26
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DMA control module
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2026-07-14 13:08:10 +03:00 |
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d0f48ba513
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controller_wrapper_axil with DMA control registers
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2026-07-14 13:07:48 +03:00 |
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126b66e4f5
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fix: port names in axi4l reg_map
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2026-07-10 17:51:30 +03:00 |
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c0a2f0e403
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add window_size register
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2026-07-10 14:15:17 +03:00 |
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7bd1aa68da
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add window_sizereg and cfg_bus_valid_reg
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2026-07-10 14:03:07 +03:00 |
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061f8fe12b
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debugged controller
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2026-07-10 13:13:18 +03:00 |
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99a344d534
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debugging controller
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2026-07-08 17:53:25 +03:00 |
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e7c45101d1
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rst added
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2026-07-08 12:51:38 +03:00 |
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fc3134f2d8
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controller's changes
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2026-07-08 12:50:28 +03:00 |
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a82140feda
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add send signal to start a dma transaction
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2026-07-08 12:49:51 +03:00 |
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bafd084f0d
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rtl: dma descriptor and status transmitter logic
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2026-07-07 17:33:53 +03:00 |
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d71655885c
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rtl: axil wrapper logic for controller
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2026-07-07 17:33:25 +03:00 |
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56e31a6cc6
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rtl: add window_size register
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2026-07-07 17:32:42 +03:00 |
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14a1df8bae
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rtl: controller module deconstruction
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2026-07-07 17:32:13 +03:00 |
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a6ade44b4d
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rtl: eth remove
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2026-07-03 16:28:08 +03:00 |
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14f4a5eb2a
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rtl: register map addition for DMA control
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2026-06-30 17:13:00 +03:00 |
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1eb21b5087
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rtl: controller adc_dac management register map
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2026-06-30 13:12:51 +03:00 |
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ecb2ed3b7f
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rtl: update controller to support different smp_num for adc/dac sides
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2026-05-08 15:59:20 +03:00 |
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c41b08f539
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fix: tricky packet check in ctrl
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2026-04-15 17:56:22 +03:00 |
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003750d972
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rtl: add controller first version
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2026-04-15 12:47:10 +03:00 |
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