|
|
a3ed4919bc
|
chore: add debug for base ethernet test
|
2026-04-10 15:40:29 +03:00 |
|
|
|
d813855224
|
tests: add test project for ethernet echo & axis_mac tests
|
2026-04-10 15:39:59 +03:00 |
|
|
|
0480642167
|
chore: little refactor in eth stack
|
2026-04-10 15:38:09 +03:00 |
|
|
|
c33afac783
|
rtl: implement axis UDP TX logic
|
2026-04-10 15:37:19 +03:00 |
|
|
|
26c627c988
|
rtl: add udp ram data count signal logic
|
2026-04-10 15:35:26 +03:00 |
|
|
|
3544e3e2dc
|
test: add sample top for axis loopback test
|
2026-04-08 19:58:34 +03:00 |
|
|
|
100feb0ea1
|
rtl: add constrains for axis eth fpga project
|
2026-04-01 18:10:17 +03:00 |
|
|
|
1310555b55
|
chore: remove old file
|
2026-04-01 18:08:50 +03:00 |
|
|
|
c75443d170
|
test: udp axis rx
|
2026-04-01 18:04:01 +03:00 |
|
|
|
3a58119960
|
rtl: eth udp rx -> axis
|
2026-04-01 18:03:47 +03:00 |
|
|
|
0b9fb64193
|
rtl: add axis eth rx prototype
|
2026-04-01 11:44:46 +03:00 |
|
|
|
7fedc36562
|
tests: add sample project for minimal eth udp echo
|
2026-03-31 15:08:12 +03:00 |
|
|
|
ded2afc0db
|
rtl: add sources for ethernet udp stack
|
2026-03-31 12:53:16 +03:00 |
|
|
|
aa1d45fe15
|
infra: init project structure
|
2026-03-25 16:17:55 +03:00 |
|
