Commit Graph

168 Commits

Author SHA1 Message Date
8648747380 debugging a module and its wrappers 2026-07-22 22:06:44 +03:00
e06ef3a16b changing the addition of interfaces 2026-07-21 22:37:24 +03:00
c121c2c103 test environment for controller and dma project 2026-07-21 22:36:55 +03:00
56c33d2769 makefile for test project 2026-07-21 22:35:32 +03:00
fc33aa6862 rtl: little changes 2026-07-21 14:07:44 +03:00
490d3dcfd0 creation of project for dma tests 2026-07-20 17:29:15 +03:00
1c2eccaf1d rtl: reconstruction of registers for dma 2026-07-20 17:28:48 +03:00
076ad542b2 test: add all controller tests 2026-07-14 20:07:52 +03:00
e685a6a9fc fix: rework wrapper for tests 2026-07-14 20:07:34 +03:00
c057890007 fix: invalid signals 2026-07-14 20:07:23 +03:00
42df57be7d axis flat to if / if to flat correction 2026-07-14 19:24:25 +03:00
606d1d7f1c little axis desc status correction 2026-07-14 19:07:32 +03:00
8aefa4f3f6 axis dma desc and status interface 2026-07-14 18:39:48 +03:00
7cf727883f test: add proper cfg tests 2026-07-14 18:06:29 +03:00
cec4c84fd9 fix: controller reg map invalid mapping 2026-07-14 17:43:47 +03:00
691e69693a infra: update makefile for cocotb 2026-07-14 16:48:45 +03:00
e467700368 tests: update testbench for controller reg map 2026-07-14 16:34:35 +03:00
984461afc0 shapper syntaxis corrected 2026-07-14 13:55:58 +03:00
6c171c55d7 controller_wrapper_axil syntaxis corrected 2026-07-14 13:55:42 +03:00
c1031f6a26 DMA control module 2026-07-14 13:08:10 +03:00
d0f48ba513 controller_wrapper_axil with DMA control registers 2026-07-14 13:07:48 +03:00
19bade1c8c infra: update rtl_libs 2026-07-14 12:18:57 +03:00
0866b5da8d tests: add minimal tests for controller axi4l 2026-07-10 17:51:48 +03:00
126b66e4f5 fix: port names in axi4l reg_map 2026-07-10 17:51:30 +03:00
1ba94690d5 infra: update rtl libs 2026-07-10 17:34:37 +03:00
c0a2f0e403 add window_size register 2026-07-10 14:15:17 +03:00
7bd1aa68da add window_sizereg and cfg_bus_valid_reg 2026-07-10 14:03:07 +03:00
061f8fe12b debugged controller 2026-07-10 13:13:18 +03:00
99a344d534 debugging controller 2026-07-08 17:53:25 +03:00
e7c45101d1 rst added 2026-07-08 12:51:38 +03:00
fc3134f2d8 controller's changes 2026-07-08 12:50:28 +03:00
a82140feda add send signal to start a dma transaction 2026-07-08 12:49:51 +03:00
bafd084f0d rtl: dma descriptor and status transmitter logic 2026-07-07 17:33:53 +03:00
d71655885c rtl: axil wrapper logic for controller 2026-07-07 17:33:25 +03:00
56e31a6cc6 rtl: add window_size register 2026-07-07 17:32:42 +03:00
14a1df8bae rtl: controller module deconstruction 2026-07-07 17:32:13 +03:00
a6ade44b4d rtl: eth remove 2026-07-03 16:28:08 +03:00
14f4a5eb2a rtl: register map addition for DMA control 2026-06-30 17:13:00 +03:00
1eb21b5087 rtl: controller adc_dac management register map 2026-06-30 13:12:51 +03:00
9285ce42e1 infra: add submodule 2026-06-26 17:52:26 +03:00
8f342eebd7 Merge pull request 'dev/sw' (#14) from dev/sw into master
Reviewed-on: #14
2026-06-19 13:20:58 +03:00
646cbb4c31 Merge branch 'master' into dev/sw 2026-06-19 13:20:44 +03:00
4938b80af6 sw: add reset scale button 2026-05-26 18:15:56 +03:00
c7216e4e8e fix normalization 2026-05-26 18:05:24 +03:00
4ecb3f5ea5 sw: fix reference and some options 2026-05-26 17:27:39 +03:00
9b5e39f3df sw: add normalization 2026-05-26 16:46:51 +03:00
99d4eb976f sw: fix gui console data recv 2026-05-26 16:36:03 +03:00
d925a4ffaa sw: update reference graph options 2026-05-26 16:16:15 +03:00
07ffb31651 sw: gui version 2026-05-26 16:11:29 +03:00
0486e16484 Merge pull request 'dev/design' (#8) from dev/design into master
Reviewed-on: #8
2026-05-15 16:43:18 +03:00