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771225cd77
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fix: post-implementation timing sim TB passed
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2026-06-23 17:27:20 +03:00 |
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b38a693676
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fix: timing. New DAC-ADC line code
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2026-06-20 09:33:33 +03:00 |
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789255fa04
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fix: add timing sim tricks
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2026-06-20 04:05:37 +03:00 |
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efcd6ef5d0
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upd:
fast fix of sampler OTR.
fix debug.xdc
Major add of full automated testing for TB.
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2026-06-20 03:07:05 +03:00 |
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4fbecd5e30
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upd: sync design log verbosity + optimal delay latency
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2026-06-19 20:49:17 +03:00 |
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4923f01322
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upd: TB automation,
DA->AD delay line for signal integrity
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2026-06-19 08:00:00 +03:00 |
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fd9280737d
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fix: refactoring
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2026-06-16 20:26:45 +03:00 |
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c165d346a0
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update: new synchronizer + half-baked TB
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2026-06-10 16:40:53 +03:00 |
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5b9469560a
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infra: update Makefile for synchronizer project
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2026-05-15 15:08:22 +03:00 |
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c279f1158d
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chore: clean code sync_top
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2026-05-06 15:37:15 +03:00 |
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4fc354955c
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rtl: debug synchronizer project makefile
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2026-05-06 14:41:26 +03:00 |
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57570bea00
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rtl: debug synchronizer project constraints
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2026-05-06 14:41:15 +03:00 |
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03d0abbe86
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rtl: debug synchronizer project testbench
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2026-05-06 14:40:53 +03:00 |
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d26bc29507
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rtl: debug synchronizer project
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2026-05-06 14:40:33 +03:00 |
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