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baulin.fa/reflectometer_fpga_project
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4fbecd5e30944a0450eb4f4bc5d4516b6610a202
reflectometer_fpga_project/designs/adc_dac_synchoronizer
History
Zer0Nu11 4fbecd5e30 upd: sync design log verbosity + optimal delay latency
2026-06-19 20:49:17 +03:00
..
debug.xdc
update: new synchronizer + half-baked TB
2026-06-10 16:40:53 +03:00
Makefile
infra: update Makefile for synchronizer project
2026-05-15 15:08:22 +03:00
sync_top.sv
upd: sync design log verbosity + optimal delay latency
2026-06-19 20:49:17 +03:00
tb_sync_top.sv
upd: sync design log verbosity + optimal delay latency
2026-06-19 20:49:17 +03:00
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