Филипп Баулин baulin.fa
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  • Joined on 2026-03-25
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baulin.fa pushed to dev/ethernet at baulin.fa/reflectometer_fpga_project 2026-04-14 15:39:58 +03:00
7d1bfe25b4 infra: update constraints to use unified ones for board and additional for debug nodes
df6c204cbd docs: add readme to ethernet-udp
8907fea8a4 fix: signal in axis_mac
1c654f4e8e tests: add tb to axis_mac project
c372dcd942 infra: add sim support to vivado.mk targets
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baulin.fa pushed to dev/ethernet at baulin.fa/reflectometer_fpga_project 2026-04-10 15:41:06 +03:00
a3ed4919bc chore: add debug for base ethernet test
d813855224 tests: add test project for ethernet echo & axis_mac tests
0480642167 chore: little refactor in eth stack
c33afac783 rtl: implement axis UDP TX logic
26c627c988 rtl: add udp ram data count signal logic
Compare 7 commits »
baulin.fa pushed to master at baulin.fa/reflectometer_fpga_project 2026-04-08 15:25:04 +03:00
ad6d6a4e2b Merge pull request 'rtl: sampler ready' (#2) from dev/sampler into master
221cb055f1 rtl: sampler ready
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baulin.fa merged pull request baulin.fa/reflectometer_fpga_project#2 2026-04-08 15:25:04 +03:00
rtl: sampler ready
baulin.fa pushed to dev/ethernet at baulin.fa/reflectometer_fpga_project 2026-04-01 18:10:32 +03:00
100feb0ea1 rtl: add constrains for axis eth fpga project
1310555b55 chore: remove old file
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baulin.fa pushed to dev/ethernet at baulin.fa/reflectometer_fpga_project 2026-04-01 18:04:22 +03:00
c75443d170 test: udp axis rx
3a58119960 rtl: eth udp rx -> axis
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baulin.fa pushed to dev/ethernet at baulin.fa/reflectometer_fpga_project 2026-04-01 11:45:20 +03:00
0b9fb64193 rtl: add axis eth rx prototype
baulin.fa pushed to dev/ethernet at baulin.fa/reflectometer_fpga_project 2026-03-31 15:09:05 +03:00
a1386fc8a4 infra: add vivado.mk target for generic builds
7fedc36562 tests: add sample project for minimal eth udp echo
0dd0006e47 infra: add gitignore
ded2afc0db rtl: add sources for ethernet udp stack
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baulin.fa created branch dev/ethernet in baulin.fa/reflectometer_fpga_project 2026-03-31 15:09:05 +03:00
0be4f35152 infra: add verilog-ethernet as a submodule
baulin.fa created branch dev/ethernet_udp_stack in baulin.fa/reflectometer_fpga_project 2026-03-25 16:28:39 +03:00
baulin.fa pushed to master at baulin.fa/reflectometer_fpga_project 2026-03-25 16:19:29 +03:00
aa1d45fe15 infra: init project structure
baulin.fa pushed to master at baulin.fa/reflectometer_fpga_project 2026-03-25 15:57:12 +03:00
1c9bce7927 chore: update readme
baulin.fa created repository baulin.fa/reflectometer_fpga_project 2026-03-25 15:48:16 +03:00