36 lines
892 B
Systemverilog
36 lines
892 B
Systemverilog
package axi4l_reg_map_example_pkg;
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localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 4;
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localparam logic [2:0] REG_BIT_RSVD = 3'd0;
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localparam logic [2:0] REG_BIT_RO = 3'd1;
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localparam logic [2:0] REG_BIT_RW = 3'd2;
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localparam logic [2:0] REG_BIT_W1S = 3'd3;
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localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0][2:0] AXI4L_REG_MAP_EXAMPLE_REG_MODE = '{
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'{
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REG_BIT_W1S,
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REG_BIT_RW,
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default: REG_BIT_RSVD
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},
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'{
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REG_BIT_RO,
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default: REG_BIT_RSVD
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},
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'{
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REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
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REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
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default: REG_BIT_RSVD
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},
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'{default: REG_BIT_RW}
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};
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localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0] AXI4L_REG_MAP_EXAMPLE_REG_RST = '{
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32'h0000_0000,
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32'h0000_0000,
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32'h0000_0000,
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32'h0000_0001
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};
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endpackage
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