baulin.fa/rtl_libs
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
13 Commits 3 Branches 0 Tags
52a2bccc7784bc4deeff007ae29df1770a8865f7
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Phil 52a2bccc77 rtl: add axis iface
2026-06-09 17:18:56 +03:00
axi
rtl: add axis iface
2026-06-09 17:18:56 +03:00
.gitignore
infra: update gitignore
2026-06-09 15:30:07 +03:00
README.md
chore: first commit
2026-05-28 16:40:47 +03:00

README.md

RTL Libs

AXI Defines

Reference in New Issue View Git Blame Copy Permalink
S
Description
universal components for FPGA development
Readme
131 KiB
Languages
SystemVerilog 83.8%
Python 13.5%
Makefile 2.7%