37 lines
1.2 KiB
Systemverilog
37 lines
1.2 KiB
Systemverilog
package dma_axil_reg_map_pkg;
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localparam int unsigned DMA_AXIL_REG_MAP_N_REGS = 4;
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localparam logic [2:0] REG_BIT_RSVD = 3'd0;
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localparam logic [2:0] REG_BIT_RO = 3'd1;
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localparam logic [2:0] REG_BIT_RW = 3'd2;
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localparam logic [2:0] REG_BIT_W1S = 3'd3;
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localparam logic [2:0] REG_BIT_W1C = 3'd4;
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localparam DMA_WRITE_DESC_CONTROL_REG = 0;
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localparam DMA_WRITE_DESC_ADDR_REG = 1;
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localparam DMA_WRITE_DESC_LEN_REG = 2;
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localparam DMA_READ_DESC_CONTROL_REG = 3;
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localparam DMA_READ_DESC_ADDR_REG = 4;
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localparam DMA_READ_DESC_LEN_REG = 5;
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localparam logic [DMA_AXIL_REG_MAP_N_REGS-1:0][31:0][2:0] DMA_AXIL_REG_MAP_REG_MODE = '{
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'{REG_BIT_RO, REG_BIT_W1S, default: REG_BIT_RSVD},
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'{32{REG_BIT_RW}, default: REG_BIT_RSVD},
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'{32{REG_BIT_RW}, default: REG_BIT_RSVD},
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'{REG_BIT_RO, REG_BIT_W1S, default: REG_BIT_RSVD},
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'{32{REG_BIT_RW}, default: REG_BIT_RSVD},
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'{32{REG_BIT_RW}, default: REG_BIT_RSVD}
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};
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localparam logic [DMA_AXIL_REG_MAP_N_REGS-1:0][31:0] DMA_AXIL_REG_MAP_REG_RST = '{
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32'h0000_0000,
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32'h0000_0000,
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32'h0000_0000,
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32'h0000_0000,
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32'h0000_0000,
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32'h0000_0000
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};
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endpackage |