18 lines
373 B
Systemverilog
18 lines
373 B
Systemverilog
`timescale 1ns/1ps
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module axi4_loopback #(
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parameter int unsigned ADDR_W = 32,
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parameter int unsigned DATA_W = 64,
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parameter int unsigned ID_W = 4,
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parameter int unsigned USER_W = 1
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)(
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axi4_if.slave s_axi,
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axi4_if.master m_axi
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);
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// compact loopback/pasthrough to test ifaces
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assign m_axi.req = s_axi.req;
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assign s_axi.resp = m_axi.resp;
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endmodule
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