`timescale 1ns/1ps

module axi4_loopback #(
  parameter int unsigned ADDR_W = 32,
  parameter int unsigned DATA_W = 64,
  parameter int unsigned ID_W   = 4,
  parameter int unsigned USER_W = 1
)(
  axi4_if.slave  s_axi,
  axi4_if.master m_axi
);

  // compact loopback/pasthrough to test ifaces
  assign m_axi.req  = s_axi.req;
  assign s_axi.resp = m_axi.resp;

endmodule