baulin.fa/rtl_libs
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Phil c18233e16a chore: add some notes
2026-06-09 18:11:27 +03:00
axi
chore: add some notes
2026-06-09 18:11:27 +03:00
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README.md
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README.md

RTL Libs

AXI Defines

Description
universal components for FPGA development
Readme 98 KiB
Languages
SystemVerilog 100%