tests: add simple read/write test

This commit is contained in:
Phil
2026-06-09 15:29:59 +03:00
parent bc91a8b3ea
commit c0fb75e7c3
2 changed files with 66 additions and 0 deletions

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@ -15,3 +15,18 @@ VERILOG_SOURCES += $(RTL_DIR)/axi_pkg.sv
VERILOG_SOURCES += $(RTL_DIR)/axi_if.sv
VERILOG_SOURCES += $(RTL_DIR)/axi4_flat_to_if.sv
VERILOG_SOURCES += $(RTL_DIR)/axi4_if_to_flat.sv
VERILOG_SOURCES += $(PWD)/tb_axi4_loopback.sv
VERILOG_SOURCES += $(PWD)/axi4_loopback.sv
TOPLEVEL = tb_axi4_loopback
MODULE = test_axi4_loopback
ifeq ($(SIM),verilator)
EXTRA_ARGS += --trace --trace-structs
EXTRA_ARGS += -I$(PWD)/rtl
COMPILE_ARGS += -Wno-fatal
COMPILE_ARGS += -I$(PWD)/rtl
endif
include $(shell cocotb-config --makefiles)/Makefile.sim