tests: add simple read/write test
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@ -15,3 +15,18 @@ VERILOG_SOURCES += $(RTL_DIR)/axi_pkg.sv
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VERILOG_SOURCES += $(RTL_DIR)/axi_if.sv
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VERILOG_SOURCES += $(RTL_DIR)/axi4_flat_to_if.sv
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VERILOG_SOURCES += $(RTL_DIR)/axi4_if_to_flat.sv
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VERILOG_SOURCES += $(PWD)/tb_axi4_loopback.sv
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VERILOG_SOURCES += $(PWD)/axi4_loopback.sv
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TOPLEVEL = tb_axi4_loopback
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MODULE = test_axi4_loopback
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ifeq ($(SIM),verilator)
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EXTRA_ARGS += --trace --trace-structs
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EXTRA_ARGS += -I$(PWD)/rtl
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COMPILE_ARGS += -Wno-fatal
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COMPILE_ARGS += -I$(PWD)/rtl
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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