From c0fb75e7c37a454bd9ae8a64717ba495d296bfa0 Mon Sep 17 00:00:00 2001
From: Phil <fabaulin_2@edu.hse.ru>
Date: Tue, 9 Jun 2026 15:29:59 +0300
Subject: [PATCH] tests: add simple read/write test

---
 axi/tb/axi_cocotb_loopback_test/Makefile      | 15 ++++++
 .../test_axi4_loopback.py                     | 51 +++++++++++++++++++
 2 files changed, 66 insertions(+)
 create mode 100644 axi/tb/axi_cocotb_loopback_test/test_axi4_loopback.py

diff --git a/axi/tb/axi_cocotb_loopback_test/Makefile b/axi/tb/axi_cocotb_loopback_test/Makefile
index 1710361..de092b7 100644
--- a/axi/tb/axi_cocotb_loopback_test/Makefile
+++ b/axi/tb/axi_cocotb_loopback_test/Makefile
@@ -15,3 +15,18 @@ VERILOG_SOURCES += $(RTL_DIR)/axi_pkg.sv
 VERILOG_SOURCES += $(RTL_DIR)/axi_if.sv
 VERILOG_SOURCES += $(RTL_DIR)/axi4_flat_to_if.sv
 VERILOG_SOURCES += $(RTL_DIR)/axi4_if_to_flat.sv
+VERILOG_SOURCES += $(PWD)/tb_axi4_loopback.sv
+VERILOG_SOURCES += $(PWD)/axi4_loopback.sv
+
+TOPLEVEL = tb_axi4_loopback
+MODULE = test_axi4_loopback
+
+
+ifeq ($(SIM),verilator)
+    EXTRA_ARGS += --trace --trace-structs
+    EXTRA_ARGS += -I$(PWD)/rtl
+    COMPILE_ARGS += -Wno-fatal
+    COMPILE_ARGS += -I$(PWD)/rtl
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
diff --git a/axi/tb/axi_cocotb_loopback_test/test_axi4_loopback.py b/axi/tb/axi_cocotb_loopback_test/test_axi4_loopback.py
new file mode 100644
index 0000000..d5b837f
--- /dev/null
+++ b/axi/tb/axi_cocotb_loopback_test/test_axi4_loopback.py
@@ -0,0 +1,51 @@
+import itertools
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer
+from cocotbext.axi import AxiBus, AxiMaster, AxiRam
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        # Forencich-style connection:
+        #   s_axi: cocotb AXI master -> flat_to_if -> compact AXI interface
+        #   m_axi: compact AXI interface -> if_to_flat -> cocotb AXI RAM
+        self.master = AxiMaster(AxiBus.from_prefix(
+            dut, "s_axi"), dut.clk, dut.rst)
+        self.ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"),
+                          dut.clk, dut.rst, size=2**20)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+@cocotb.test()
+async def run_basic_write_read_test(dut):
+    # simple loopback test..
+    tb = TB(dut)
+    await tb.reset()
+
+    test_data = bytes(range(64))
+    addr = 0x1000
+
+    await tb.master.write(addr, test_data)
+    read_data = await tb.master.read(addr, len(test_data))
+
+    assert bytes(read_data.data) == test_data