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fix: tb cases, now passes

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Phil
2026-06-17 17:54:09 +03:00
parent dffb32901f
commit 4a4c8d8ef2
1 changed files with 1 additions and 1 deletions
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axi/tb/axil_reg_cocotb/test_axi4l_reg_map.py
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@ -98,7 +98,7 @@ async def test_rw_and_w1c_bits(dut):
assert await tb.read32(REG0_CTRL) == 0x00000004 assert await tb.read32(REG0_CTRL) == 0x00000004
# Set RW bit1 while preserving W1C bit2 # Set RW bit1 while preserving W1C bit2
await tb.write32(REG0_CTRL, 0x00000006) await tb.write32(REG0_CTRL, 0x00000002)
assert await tb.read32(REG0_CTRL) == 0x00000006 assert await tb.read32(REG0_CTRL) == 0x00000006
# Write 1 to W1C bit2, keep RW bit1 set # Write 1 to W1C bit2, keep RW bit1 set