diff --git a/axi/tb/axil_reg_cocotb/test_axi4l_reg_map.py b/axi/tb/axil_reg_cocotb/test_axi4l_reg_map.py
index 8830cc7..f3ab50f 100644
--- a/axi/tb/axil_reg_cocotb/test_axi4l_reg_map.py
+++ b/axi/tb/axil_reg_cocotb/test_axi4l_reg_map.py
@@ -98,7 +98,7 @@ async def test_rw_and_w1c_bits(dut):
     assert await tb.read32(REG0_CTRL) == 0x00000004
 
     # Set RW bit1 while preserving W1C bit2
-    await tb.write32(REG0_CTRL, 0x00000006)
+    await tb.write32(REG0_CTRL, 0x00000002)
     assert await tb.read32(REG0_CTRL) == 0x00000006
 
     # Write 1 to W1C bit2, keep RW bit1 set