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Phil 4a4c8d8ef2 fix: tb cases, now passes
2026-06-17 17:54:09 +03:00
axi
fix: tb cases, now passes
2026-06-17 17:54:09 +03:00
external
infra: add forencich repository as a submodule
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.gitignore
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README.md
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2026-05-28 16:40:47 +03:00

README.md

RTL Libs

AXI Defines

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Description
universal components for FPGA development
Readme
131 KiB
Languages
SystemVerilog 83.8%
Python 13.5%
Makefile 2.7%