rtl: add AXI if defines

axi/axi_reg/axi4l_reg_map_example.sv

@@ -0,0 +1,60 @@
+module axi4l_reg_map_example #(
+  parameter int unsigned ADDR_W = 16,
+  parameter int unsigned DATA_W = 32,
+  parameter int unsigned USER_W = 1
+)(
+  input  logic clk,
+  input  logic rst_n,
+  axi4l_if.slave s_axil,
+
+  output logic       start_o,
+  output logic       enable_o,
+  input  logic       busy_i,
+  input  logic [7:0] error_code_i
+);
+  import axi4l_reg_map_example_pkg::*;
+
+  localparam int unsigned N_REGS = AXI4L_REG_MAP_EXAMPLE_N_REGS;
+
+  logic [N_REGS-1:0][31:0] reg_i;
+  logic [N_REGS-1:0][31:0] reg_o;
+  logic [N_REGS-1:0][31:0] reg_pulse;
+
+  axi4l_reg_map #(
+    .ADDR_W  (ADDR_W),
+    .DATA_W  (DATA_W),
+    .USER_W  (USER_W),
+    .N_REGS  (N_REGS),
+    .REG_MODE(AXI4L_REG_MAP_EXAMPLE_REG_MODE),
+    .REG_RST (AXI4L_REG_MAP_EXAMPLE_REG_RST)
+  ) u_reg_map (
+    .clk      (clk),
+    .rst_n    (rst_n),
+    .s_axil   (s_axil),
+    .reg_i    (reg_i),
+    .reg_o    (reg_o),
+    .reg_pulse(reg_pulse)
+  );
+
+  always_comb begin
+    reg_i = '0;
+
+    // REG1 @ 0x04: status register
+    // bit 0   : busy (RO)
+    reg_i[1][0] = busy_i;
+
+    // REG2 @ 0x08: error register
+    // bits 7:0: error_code (RO)
+    reg_i[2][7:0] = error_code_i;
+  end
+
+  // REG0 @ 0x00: control register
+  // bit 0 : start (W1S pulse)
+  // bit 1 : enable (RW)
+  assign start_o  = reg_pulse[0][0];
+  assign enable_o = reg_o[0][1];
+
+  // REG3 @ 0x0C: generic configuration register (RW)
+  // reg_o[3] can be manually connected later if needed.
+
+endmodule