rtl: add AXI if defines
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Phil
189
axi/axi_reg/axi4l_reg_map.sv
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189
axi/axi_reg/axi4l_reg_map.sv
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@ -0,0 +1,189 @@
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module axi4l_reg_map #(
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parameter int unsigned ADDR_W = 16,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1,
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parameter int unsigned N_REGS = 4,
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parameter logic [N_REGS-1:0][31:0][2:0] REG_MODE = '{default:'0},
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parameter logic [N_REGS-1:0][31:0] REG_RST = '{default:'0}
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)(
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input logic clk,
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input logic rst_n,
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axi4l_if.slave s_axil,
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input logic [N_REGS-1:0][31:0] reg_i,
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output logic [N_REGS-1:0][31:0] reg_o
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);
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import axi_pkg::*;
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typedef enum logic [2:0] {
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REG_BIT_RSVD = 3'd0,
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REG_BIT_RO = 3'd1,
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REG_BIT_RW = 3'd2,
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REG_BIT_W1S = 3'd3,
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REG_BIT_W1C = 3'd4
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} reg_bit_mode_t;
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localparam int unsigned STRB_W = DATA_W/8;
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localparam int unsigned ADDR_LSB = $clog2(DATA_W/8);
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localparam int unsigned REG_INDEX_W = (N_REGS <= 1) ? 1 : $clog2(N_REGS);
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logic [ADDR_W-1:0] awaddr_q;
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logic aw_seen_q;
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logic [DATA_W-1:0] wdata_q;
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logic [STRB_W-1:0] wstrb_q;
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logic w_seen_q;
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logic bvalid_q;
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logic [1:0] bresp_q;
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logic rvalid_q;
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logic [1:0] rresp_q;
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logic [DATA_W-1:0] rdata_q;
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logic [REG_INDEX_W-1:0] wr_idx;
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logic [REG_INDEX_W-1:0] rd_idx;
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logic wr_addr_valid;
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logic rd_addr_valid;
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integer b;
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logic [31:0] wr_mask;
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logic [31:0] wr_data32;
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logic [31:0] rw_cur;
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logic [31:0] rw_new;
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logic [31:0] rd_word;
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always_comb begin
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wr_idx = '0;
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rd_idx = '0;
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wr_addr_valid = 1'b0;
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rd_addr_valid = 1'b0;
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if (awaddr_q[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W] < N_REGS) begin
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wr_idx = awaddr_q[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W];
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wr_addr_valid = 1'b1;
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end
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if (s_axil.req.ar.addr[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W] < N_REGS) begin
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rd_idx = s_axil.req.ar.addr[ADDR_LSB + REG_INDEX_W - 1 -: REG_INDEX_W];
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rd_addr_valid = 1'b1;
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end
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end
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always_comb begin
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wr_mask = '0;
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for (int k = 0; k < STRB_W; k++) begin
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wr_mask[k*8 +: 8] = {8{wstrb_q[k]}};
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end
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wr_data32 = wdata_q[31:0];
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end
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assign s_axil.resp.aw_ready = !aw_seen_q && !bvalid_q;
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assign s_axil.resp.w_ready = !w_seen_q && !bvalid_q;
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assign s_axil.resp.ar_ready = !rvalid_q;
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assign s_axil.resp.b.valid = bvalid_q;
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assign s_axil.resp.b.resp = axi_resp_t'(bresp_q);
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assign s_axil.resp.b.user = '0;
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assign s_axil.resp.r.valid = rvalid_q;
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assign s_axil.resp.r.resp = axi_resp_t'(rresp_q);
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assign s_axil.resp.r.data = rdata_q;
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assign s_axil.resp.r.user = '0;
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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awaddr_q <= '0;
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aw_seen_q <= 1'b0;
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wdata_q <= '0;
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wstrb_q <= '0;
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w_seen_q <= 1'b0;
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bvalid_q <= 1'b0;
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bresp_q <= 2'b00;
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rvalid_q <= 1'b0;
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rresp_q <= 2'b00;
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rdata_q <= '0;
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reg_o <= REG_RST;
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end else begin
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for (int r = 0; r < N_REGS; r++) begin
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for (int bit_idx = 0; bit_idx < 32; bit_idx++) begin
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if (reg_bit_mode_t'(REG_MODE[r][bit_idx]) == REG_BIT_W1S)
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reg_o[r][bit_idx] <= 1'b0;
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end
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end
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if (s_axil.req.aw.valid && s_axil.resp.aw_ready) begin
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awaddr_q <= s_axil.req.aw.addr;
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aw_seen_q <= 1'b1;
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end
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if (s_axil.req.w.valid && s_axil.resp.w_ready) begin
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wdata_q <= s_axil.req.w.data;
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wstrb_q <= s_axil.req.w.strb;
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w_seen_q <= 1'b1;
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end
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if (aw_seen_q && w_seen_q && !bvalid_q) begin
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bvalid_q <= 1'b1;
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bresp_q <= 2'b00;
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if (!wr_addr_valid) begin
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bresp_q <= 2'b10;
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end else begin
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rw_cur = reg_o[wr_idx];
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rw_new = rw_cur;
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for (b = 0; b < 32; b = b + 1) begin
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if (wr_mask[b]) begin
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unique case (reg_bit_mode_t'(REG_MODE[wr_idx][b]))
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REG_BIT_RSVD: begin end
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REG_BIT_RO : begin bresp_q <= 2'b10; end
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REG_BIT_RW : rw_new[b] = wr_data32[b];
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REG_BIT_W1S : if (wr_data32[b]) rw_new[b] = 1'b1;
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REG_BIT_W1C : if (wr_data32[b]) rw_new[b] = 1'b0;
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default : begin end
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endcase
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end
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end
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reg_o[wr_idx] <= rw_new;
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end
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aw_seen_q <= 1'b0;
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w_seen_q <= 1'b0;
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end
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if (bvalid_q && s_axil.req.b_ready) begin
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bvalid_q <= 1'b0;
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end
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if (s_axil.req.ar.valid && s_axil.resp.ar_ready) begin
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rvalid_q <= 1'b1;
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rresp_q <= 2'b00;
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rd_word = '0;
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if (!rd_addr_valid) begin
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rresp_q <= 2'b10;
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end else begin
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for (b = 0; b < 32; b = b + 1) begin
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unique case (reg_bit_mode_t'(REG_MODE[rd_idx][b]))
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REG_BIT_RSVD: rd_word[b] = 1'b0;
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REG_BIT_RO : rd_word[b] = reg_i[rd_idx][b];
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REG_BIT_RW : rd_word[b] = reg_o[rd_idx][b];
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REG_BIT_W1S : rd_word[b] = 1'b0;
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REG_BIT_W1C : rd_word[b] = reg_o[rd_idx][b];
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default : rd_word[b] = 1'b0;
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endcase
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end
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end
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rdata_q <= rd_word;
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end
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if (rvalid_q && s_axil.req.r_ready) begin
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rvalid_q <= 1'b0;
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end
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end
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end
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endmodule
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60
axi/axi_reg/axi4l_reg_map_example.sv
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60
axi/axi_reg/axi4l_reg_map_example.sv
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@ -0,0 +1,60 @@
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module axi4l_reg_map_example #(
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parameter int unsigned ADDR_W = 16,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1
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)(
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input logic clk,
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input logic rst_n,
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axi4l_if.slave s_axil,
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output logic start_o,
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output logic enable_o,
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input logic busy_i,
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input logic [7:0] error_code_i
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);
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import axi4l_reg_map_example_pkg::*;
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localparam int unsigned N_REGS = AXI4L_REG_MAP_EXAMPLE_N_REGS;
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logic [N_REGS-1:0][31:0] reg_i;
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logic [N_REGS-1:0][31:0] reg_o;
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logic [N_REGS-1:0][31:0] reg_pulse;
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axi4l_reg_map #(
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.ADDR_W (ADDR_W),
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.DATA_W (DATA_W),
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.USER_W (USER_W),
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.N_REGS (N_REGS),
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.REG_MODE(AXI4L_REG_MAP_EXAMPLE_REG_MODE),
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.REG_RST (AXI4L_REG_MAP_EXAMPLE_REG_RST)
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) u_reg_map (
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.clk (clk),
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.rst_n (rst_n),
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.s_axil (s_axil),
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.reg_i (reg_i),
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.reg_o (reg_o),
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.reg_pulse(reg_pulse)
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);
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always_comb begin
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reg_i = '0;
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// REG1 @ 0x04: status register
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// bit 0 : busy (RO)
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reg_i[1][0] = busy_i;
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// REG2 @ 0x08: error register
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// bits 7:0: error_code (RO)
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reg_i[2][7:0] = error_code_i;
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end
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// REG0 @ 0x00: control register
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// bit 0 : start (W1S pulse)
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// bit 1 : enable (RW)
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assign start_o = reg_pulse[0][0];
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assign enable_o = reg_o[0][1];
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// REG3 @ 0x0C: generic configuration register (RW)
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// reg_o[3] can be manually connected later if needed.
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endmodule
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35
axi/axi_reg/axi4l_reg_map_example_pkg.sv
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35
axi/axi_reg/axi4l_reg_map_example_pkg.sv
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package axi4l_reg_map_example_pkg;
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localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 4;
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localparam logic [2:0] REG_BIT_RSVD = 3'd0;
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localparam logic [2:0] REG_BIT_RO = 3'd1;
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localparam logic [2:0] REG_BIT_RW = 3'd2;
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localparam logic [2:0] REG_BIT_W1S = 3'd3;
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localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0][2:0] AXI4L_REG_MAP_EXAMPLE_REG_MODE = '{
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'{
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REG_BIT_W1S,
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REG_BIT_RW,
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default: REG_BIT_RSVD
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},
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'{
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REG_BIT_RO,
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default: REG_BIT_RSVD
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},
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'{
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REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
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REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
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default: REG_BIT_RSVD
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},
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'{default: REG_BIT_RW}
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};
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localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0] AXI4L_REG_MAP_EXAMPLE_REG_RST = '{
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32'h0000_0000,
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32'h0000_0000,
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32'h0000_0000,
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32'h0000_0001
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};
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endpackage
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37
axi/axi_reg/dma_axil_reg_map_pkg.sv
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37
axi/axi_reg/dma_axil_reg_map_pkg.sv
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@ -0,0 +1,37 @@
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package dma_axil_reg_map_pkg;
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localparam int unsigned DMA_AXIL_REG_MAP_N_REGS = 4;
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localparam logic [2:0] REG_BIT_RSVD = 3'd0;
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localparam logic [2:0] REG_BIT_RO = 3'd1;
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localparam logic [2:0] REG_BIT_RW = 3'd2;
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localparam logic [2:0] REG_BIT_W1S = 3'd3;
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localparam logic [2:0] REG_BIT_W1C = 3'd4;
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localparam DMA_WRITE_DESC_CONTROL_REG = 0;
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localparam DMA_WRITE_DESC_ADDR_REG = 1;
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localparam DMA_WRITE_DESC_LEN_REG = 2;
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localparam DMA_READ_DESC_CONTROL_REG = 3;
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localparam DMA_READ_DESC_ADDR_REG = 4;
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localparam DMA_READ_DESC_LEN_REG = 5;
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localparam logic [DMA_AXIL_REG_MAP_N_REGS-1:0][31:0][2:0] DMA_AXIL_REG_MAP_REG_MODE = '{
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'{REG_BIT_RO, REG_BIT_W1S, default: REG_BIT_RSVD},
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'{32{REG_BIT_RW}, default: REG_BIT_RSVD},
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'{32{REG_BIT_RW}, default: REG_BIT_RSVD},
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'{REG_BIT_RO, REG_BIT_W1S, default: REG_BIT_RSVD},
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'{32{REG_BIT_RW}, default: REG_BIT_RSVD},
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'{32{REG_BIT_RW}, default: REG_BIT_RSVD}
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};
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localparam logic [DMA_AXIL_REG_MAP_N_REGS-1:0][31:0] DMA_AXIL_REG_MAP_REG_RST = '{
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32'h0000_0000,
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32'h0000_0000,
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32'h0000_0000,
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32'h0000_0000,
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32'h0000_0000,
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32'h0000_0000
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};
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endpackage
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